JPS60105337A - Transmission system of digital signal - Google Patents

Abstract

PURPOSE:To attain surely transmission/reception of a signal with no adjustment by controlling a frame pulse counter so as to bring the phase relation between a frame alignment pulse and a frame alignment reference pulse from a transmitter into a prescribed relation at all times in a receiver. CONSTITUTION:The system is constituted with the 1st device (receiver) 100 operated in response to the 1st clock CLK1 and the 2nd device (transmitter) 200 operated in response to the 2nd clock CLK2 phase-locked to the clock CLK1. A normal phase comparator circuit 107 of the device 100 compares and detects the timing phase between the frame alignment pulse FAP and the frame alignment reference pulse FARP from the transmitter 200, controls a multi-frame pulse counter 105 so that the relation of phase is always at a prescribed relation, the timing phase of a multi-frame pulse MFP to the transmitter 200 is set automatically thereby transmitting/receiving a serial digital signal.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a digital communication system. In particular, POM
The present invention relates to a transmission system for digital signals that are sent and received in a frame structure or multi-frame structure.

[Description of prior art]

2.048Mb/S P CM as digital No.
The details of the primary group multiplexing frame configuration are specified in 0OITT (Koukai Telegraph and Telephone Advisory Committee) Recommendation 0.732. This multiplexed frame configuration has a multi-frame configuration and is used for time slot OJ frame synchronization signals and multi-frame synchronization signals, and is used for time slot '16J monitoring signals (Super Vigorye
ignal ) and signal pulses (Signaling
It is used for transmission of pulses. Furthermore, the transmission line code format is T (DB3).

Normally, the pressure required to transmit the 2.048 Mb7's P OM signal is only the HDB 3 signal because the receiving side can detect and capture frame synchronization from the received data, but the H
Interface circuits such as DB3 interface circuit and frame synchronization circuit and multi-frame synchronization circuit are required. This HDB3 signal format was originally adopted with the intention of being used in a general long-distance transmission line interface. Devices that send and receive signals: If they are installed close to each other, it is possible to transmit without using the HDB3 (I! format).

For example, the US EIA (Klectronic In
If you use the standard Re-422 signal tri-9 striper and receiver, approximately 30
m can be transmitted.

If an R8422 interface is used, a clock signal line is required in addition to the data signal line. However, HDB
Compared to the R8422 interface circuit, the R8422 interface circuit significantly reduces the node area, so the R8
422 interface is often adopted.

The present invention relates to a transmission system for transmitting and receiving digital signals using other signal formats such as R6422, which simultaneously transmit data signals and clocks, instead of using such a normal HDB 3 interface.

In this way, 2 Mb/SPs interfacing with each other
If there is commercial data and the transmission distance is short enough, HDB
In some cases, the R8422 signal format is used instead of the 3 signal format. In this case, by simultaneously sending a clock and a multiframe signal in addition to data on the transmitting side, bit synchronization, frame synchronization, and multiframe synchronization circuits can be omitted on the receiving side. However, on the receiving side, it is necessary to predefine each timing phase of the multiframe signal, clock, and data signal on the transmitting side with respect to a preset basic multiframe. Therefore, the device becomes multi-axial.

Furthermore, even if the phase is predefined in the device, the transmission distance varies depending on the head tilting state of the device, which causes fluctuations in transmission delay and requires phase adjustment for each device.

Particularly, when the devices were manufactured at different times or when interfacing with devices from different manufacturers, phase adjustment is required each time.

Furthermore, there is a drawback that phase adjustment must be performed for short-term fluctuations such as jitter and changes due to aging of the device.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks, and eliminates the need to set strict timing phase relationship standards between transmitting and receiving devices.
Furthermore, it is an object of the present invention to provide a simple digital signal transmission system that can reliably transmit and receive signals without adjustment even with variations in installation distance, manufacturing lot, aging, jitter, etc.

[Features of the invention]

The present invention includes a first device that operates in response to a first clock, and a second device that operates in response to a second clock that is phase-synchronized with the first clock, and the second device operates in response to a second clock that is phase-synchronized with the first clock. In a digital signal transmission method in which a first device receives an output digital signal sequence, the first device receives a multi-frame signal that is sent to the second device in order to establish clock phase synchronization with the second device. a multi-frame pulse counter for generating pulses; a frame alignment reference pulse counter for generating frame alignment reference pulses for capturing frame alignment pulses arriving from a second device; and a multi-frame gate pulse for controlling said multi-frame pulses. a multi-frame gate counter that generates a multi-frame gate counter; a phase comparator that compares and verifies the timing phases of the frame alignment reference pulse and the 7-frame alignment pulse; a prohibition circuit that prohibits input; a serial-parallel converter that converts the serial digital signal string from the second device into a parallel digital signal; and a parallel converter that converts the output of the serial-parallel converter into a first clock. response (7) and a register to capture it;
The second device includes a phase-locked oscillator circuit that responds to the multi-frame pulse from the first device and generates a second clock that is phase-synchronized with the multi-frame pulse, and a phase-locked oscillation circuit that generates a second clock that is phase-synchronized with the multi-frame pulse from the first device; 7-frame alignment pulses for forming the frame timing and multi-frame timing of the output digital signal train, multi-frame alignment pulses for generating the multi-frame alignment Hals and the third clock, serial digital signal train, 7-frame alignment and a transmission path sending circuit for sending pulses and a third clock to the transmission path. By comparing and verifying the timing phases, controlling the multi-frame pulse counter so that this phase relationship is always a predetermined relationship, and automatically setting the timing phase of the multi-frame pulse to the second device, The apparatus is characterized in that it is configured to capture frame and multi-frame timing of a serial digital signal train from the device and to transmit and receive the serial digital signal train.

[Explanation based on examples]

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a digital signal transmission device according to an embodiment of the present invention. In FIG. 1, a terminal 10 of a first device 100 receives an 8.192 MHz clock CLK.
1 is a frame alignment reference pulse counter 102
1000 frequency division counter 1o21 and clock inhibition circuit 1
Connected to one input of 03.

Each tap output of the 1024 frequency division counter 102 is connected to a pulse generator 1O22. The 8 KHz pulse from the 1024 divider counter 102 is connected to a multi-frame gated pulse counter 104. The output of multi-frame gated pulse counter 104 is connected to pulse generator 1042. Clock inhibition circuits 103 to 8
．． 192MHz Oyri OLK, but Maru f 7 L/
- 1024 frequency division counter 10 of pulse counter 105
5.

connected to the 1000 frequency division counter 1o5. Gara 8KH
Two frame pulses F'P are connected to one input of the multi-frame pulse gate 1052. The multi-frame gate pulse M'FGP from the multi-frame gate pulse counter 104 is connected to the signal line 104. , is connected to the other input via the multi-frame pulse (ly'-to 1052). Multi-frame pulse gate 105
The multi-frame pulse MFP from 2 is connected to the terminal 106. A frame alignment reference pulse IPARP from the pulse generator 1022 is transmitted to the signal line 1022. ' to one input of the phase comparator 107.

Frame alignment pulse FA from second device 200
A terminal 108 to which P is input is connected to the other input of the phase comparator 107 and the buffer register load pulse generation circuit 109.
connected to the reset input of A control signal from the phase comparator 107 is connected to another input of the clock inhibit circuit 103. Second device 200-2゜048M1)/S
A terminal 110 to which the clock OLK is input is connected to the clock input of the buffer register load pulse generation circuit i09, and is also connected to the clock input of the shift register 111. A terminal 112 to which serial digital data SRD is input from the second device 200 is connected to the shift register 11.
1, and the output of the shift register 111 is connected to the buffer register 113. Pulse generator 1022
Parallel data output enable pulse from FDOF! is the signal line 1022. Also, load pulses LDP from the buffer register load pulse generation circuit 109 are connected to the buffer registers 113 respectively, and parallel digital data PAD is transmitted from the buffer register 113 to the terminal 11.
Connected to 4.

The terminal 106 of the color multi-frame pulse MFP is connected to the terminal 201 of the second device 200. The terminal 201 is connected to the phase comparator circuit 202. of the phase synchronized oscillator 202. and the phase comparator circuit 202. The output of is connected to voltage controlled oscillator 2022. The 8.194MHz clock 0LKs from the voltage controlled oscillator 202□ is sent to the 1024 frequency division counter 2031 of the multi-frame pulse counter 203.
connected to. 1024 frequency division counter 203. The output of is connected to the divide-by-16 counter 2032, and the output of
When OFF is the phase comparator circuit 202. connected to. 102
The output of the divide-by-4 counter and the output of the divide-by-16 counter are:
Connected to pulse generator 2033. 2. o4aMb/
The serial digital data SRD of s is sent to the clock insertion circuit 2.
Connected to 05. The output of pulse generator 2033 is connected to clock insertion circuit 205. Pulse generator 20
35 to 2.04 with frame alignment pulse FAP
8Mb/8 clock OLK, and transmission line sending circuit 206
are connected to terminals 207 and 208 via. Further, serial digital data 8RD of 2.048 Mb/B is connected from the clock insertion circuit 205 to the terminal 209 via the transmission path output circuit 206. Terminal 207.208.2
09 are connected to terminals 108, 110, and 112, respectively.

Here, the feature of the present invention is that the first device 100
is a multi-frame pulse counter 10 that generates a multi-frame pulse MFP to be sent to the second device 200 in order to establish clock phase synchronization with the second device 200;
5, a frame alignment reference pulse counter 102 which generates a frame alignment reference pulse FARP for capturing the frame alignment pulse F'AP arriving from the second device 200, and a multi-frame pulse counter 105't Ill Control Multi-Frame Gate pulse MFGP i generator, multi-frame gate pulse counter 104, frame alignment reference pulse FARP,! :Frame alignment pulse FA
A phase comparator 107 that compares and verifies the timing phase with P.
, an inhibiting circuit 103 that responds to the output of the phase comparator 107 and inhibits clock input to the multi-frame pulse counter 105, a shift register 111 for writing the serial digital signal string 8RD i from the second device 200, and a buffer register. Parallel digital data PAD is generated by the parallel data output enable pulse PDOF+ from the buffer register load pulse generation circuit 109 and the frame alignment reference pulse counter 102.
i output buffer register 113. ! :, s.

Input terminal 10 for inputting 194MHz clock 0LK1
1, an output terminal 106 of the multi-frame pulse MFP, and an input terminal 108 of the frame alignment pulse FAP.
．． 2.048Mb/S 07 CLKS input terminal 11
0 and an input terminal 112 for serial digital data SRD;
The second device 200 is composed of an output terminal 114 for parallel digital data PAD, and the second device 200 is a phase synchronized oscillation generator that responds to the multi-frame pulse MFP from the first device 100 and generates an 8,149 MHz clock 0LK2 that is phase-synchronized with the multi-frame pulse MFP. Circuit 202 and 8.149 MHz GI7
Serial digital signal train 8RD output from second device 200 in response to LK2 and multi-frame pulse MFP
The frame alignment pulse FAP forms frame timing and multi-frame timing.

multi-frame alignment pulse MFAP and 2.
048 Mo/E clock O'LKst - multi-frame pulse counter 203 that generates, serial digital signal train sRD, frame alignment pulse FAP O and 2.048 Mb/8 clock OLK, transmission line sending circuit 206 that sends out to the transmission line. , an input terminal 201 for the multi-frame pulse MPP, an output terminal 207 for the frame alignment pulse TAP, an output terminal 208 for the 2.048 nb/s clock OLK, and an output terminal 209 for the serial digital signal train SRD. In the first device 100, the phase comparator 107 compares and tests the timing phases of the frame alignment pulse FAP from the second device 200 and the 7-frame alignment reference pulse FARP, and this phase relationship is always a predetermined relationship. Control the multi-frame pulse counter 105 as follows,
The aim is to automatically set the timing phase of the multi-frame pulse MP'P to the second device 200.

The operation of the digital signal transmission device having such a configuration will be explained. FIGS. 2 and 3 are time charts of the signals and clocks.

In FIG. 1, a first device 100 and a second device 200
Timing and multi-frame synchronization with the system is performed using the following procedure. First, the input terminal 1 of the first device 1oo
01 is 8. j92 MHz signal is added to the frame alignment reference pulse counter 102.
and the clock inhibition circuit 103.

In the frame alignment reference pulse counter 102, the 1024 frequency division counter 1o21 is 8.192 MH
z clock 0LKI f and each tap output is provided to a pulse generator 1022 and an 8 KHz pulse to a multi-frame gated pulse counter]04. The pulse generator 1022 generates a frame alignment reference pulse FARP and connects the signal lines 1o22. is supplied to one input of the phase comparator 107 via the signal line 102, and also generates a parallel data output enable signal FDOK.
2. The data is sent to the buffer register 113 via the buffer register 113. The multi-frame gate pulse counter 104 generates the multi-frame gate pulse MFGP and receives the signal #1104.
．． It is supplied to one input of the multi-frame pulse gate 1o52 in the multi-frame pulse colorafter 105 through the multi-frame pulse color shifter 105.

On the other hand, clock prohibition circuit 103 8, 192 which passed through all
MHz frequency OLK, 4d, added to multi-frame pulse counter 105, 1024 frequency division power 9 counter 1o
5. , it is converted into an 8 KHz frame pulse FP and applied to the other input of the multi-frame pulse gate 1o52. The timing position of this 8 KHzO frame pulse FP is controlled by a control signal from phase comparator 107 applied to clock inhibit circuit 103.

In the multi-frame pulse skate 1o52, a multi-frame pulse M'PP is created from the multi-frame gate pulse MFGP from the multi-frame gate pulse counter 1o4 and the 8 KHz frame pulse IFF [, sent to.

In the second device 200, the multi-frame pulse MFF from the first device ff1OO is applied to the phase synchronized oscillation circuit 202 via the terminal 201, and the phase comparison circuit 202
．． 8°192MH2 phase synchronized to multi-frame pulse MFF by voltage controlled oscillator 2022 controlled by
R07R0LK2 is generated. 8.192MH2ria
yriOIiK2 is the 1024 frequency division counter 2o31.
16 frequency division counter 2o32 and pulse generator 2o33
The second device 200K is applied to a multi-frame pulse counter 203 to generate the required pulses in the second device 200K.

16 frequency division counter 2o32 generates Id, 500Hz multi-frame pulse 500MFF, and phase comparison circuit 2o
By supplying the multi-frame pulse MPP at an angle of 2°, the phase synchronized oscillation circuit 202 is ensured to always operate with a constant phase difference from the multi-frame pulse MPP arriving from the first device 100.

Multi-frame pulse counter 203 generation end 8KH
Frame alignment pulse FAP of z.

2.048 Mb/so7ri (!LK, and terminal 2
The 2,048 Ml)/S serial digital data string SRD applied via the transmission line output circuit 206 is sent from the terminals 207, 208, and 209, respectively, to the first device 10.
sent to 0.

This 2.048 Mb/S serial digital data string 8R
A frame synchronization signal and a multiframe synchronization signal are inserted into D by the clock insertion circuit 205.

In the first device 100, the frame alignment pulse F arriving from the second device ffi 200 via the terminal 103
APu, buffer register load pulse generation circuit 109
and reset the phase comparator 107.
added to other inputs of. In the phase comparator 107,
The timing position of the frame alignment pulse FAP is checked by the frame alignment reference pulse FARP. If the frame alignment pulse FAP does not exist at the predetermined position of the frame alignment reference pulse FARP, the clock inhibit circuit 1
A clock inhibit pulse is sent to 09, and the clock sending money to multi-frame pulse counter 05 is stopped. As a result, the generation position of the multi-frame pulse MFP is shifted, and the frame alignment pulse I! in the second device 200 is shifted. The generation point of AP can be moved. Such an operation is performed by the phase comparator 10 described above.
At 7, the frame alignment pulse FAP is stabilized within a predetermined range of the frame alignment reference pulse IPARP. In this way, by setting the timing phases of the frame alignment pulse FAP and the frame alignment reference pulse FARP in a constant relationship, the multi-frame position can be determined. 2,048 Mb/s input from terminal 112 [Column digital data column 8RD is also 2,048 Mb/s input from terminal 110]
．． After being written to the shift register 111 by the 048Mb/S clock C+'LK5, the buffer register 1
13 from the load pulse LDPK from the buffer register load pulse generation circuit 109. The parallel digital data PAD output from the buffer register 113 is sent to the frame alignment reference pulse counter 102.
Parallel data output enable pulse from PDOE 17
It is outputted via the OK signal terminal 114.

〔Effect of the invention〕

As explained above, the present invention includes a first device including a multi-frame gate pulse counter, a clock inhibit circuit, a multi-frame gate pulse counter, a multi-frame pulse counter, a phase comparison circuit, a buffer register load pulse generation circuit, and a shift counter. A register and a buffer register are provided, the second device is provided with a phase synchronized oscillator, a multi-frame alignment pulse counter, and a transmission line sending circuit, and the first device uses a phase comparison circuit to perform frame alignment pulses and frame alignment from the second device. Comparing and verifying the timing phase with a reference pulse, controlling the multi-frame pulse oscilloscope so that this phase relationship always maintains a predetermined relationship, and automatically setting the timing phase of the multi-frame pulse to the second device. This has the excellent effect of automatically ensuring word synchronization and multi-frame synchronization. This eliminates the need for timing adjustment during construction of the device, and adjustment due to phase changes due to changes over time, temperature fluctuations, etc., which has the effect of greatly contributing to improved construction and maintainability of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal transmission device according to an embodiment of the present invention. FIGS. 2 and 3 are time charts of the signals and pulses. 100...first device, 101.108.110.1
12.201.204...Input terminal, 102...Frame alignment reference pulse counter, 1021.1
054.203. ...1024 frequency division counter, 102
2.2035...Pulse generator, 103...Clock l'A output circuit, 104...Multi-frame gate pulse counter, 105.203...Multi-frame pulse counter, 1O52...Multi-frame pulse gate, 106.114.207.208.209...
- Output terminal, 107... Phase comparator, 109... Buffer register load pulse generation circuit, 111... Shift register, 113... Buffer register, 200
...Second device, 202...Phase synchronized oscillation circuit, 2
021... Phase comparison circuit, 2022... Voltage controlled oscillator, 203... Multi-frame pulse counter, 2
032... 16 frequency division counter, 205... Clock insertion circuit, 206... Transmission line sending circuit, OLK, ,
0LK2-8, 192MHz clock, OLJ =・
2, 048 Mb/8 clock, FAP...frame alignment pulse, FARP...frame alignment reference pulse, FP...frame pulse,
LDP...Load pulse, MFGP...Multi-frame gate pulse, MFP...Multi-frame pulse, PAD...Parallel digital data, PDOIii
...Parallel data output enable pulse, SRD...
Serial digital data. Patent applicant: NEC Co., Ltd. Patent attorney Naotaka Ide

Claims (1)

[Scope of claims] , in a digital signal transmission system in which the first device receives a digital signal train output from the second device, the first device has clock phase synchronization with the second device. a multi-frame pulse counter that generates multi-frame pulses to send to said second device for establishing frame alignment; and a multi-frame pulse counter that generates a seven-frame alignment reference pulse for capturing frame alignment pulses coming from said second device. an alignment reference pulse counter; a multi-frame gate pulse counter that generates a multi-frame gate pulse that controls the multi-frame pulse counter; and a phase comparison that compares and verifies the timing phases of the Fraair 2-Iment reference pulse and the 7-Frame 2-Iment pulse. a prohibition circuit that responds to the output of the phase comparator and prohibits the multi-frame pulse counter from being overloaded; and a serial-to-parallel converter that converts the serial digital signal string from the second device into a parallel digital signal. and a register that receives the parallel data output from the serial-parallel converter in response to the first clock signal, and the second device includes a register that receives the parallel data output from the serial-parallel converter in response to the multi-frame pulse from the first device. a phase-locked oscillator circuit that generates the second clock that is phase-synchronized with the second clock, and a frame alignment pulse that responds to the second clock and the multi-frame pulse to form frame timing and multi-frame timing of an output digital signal train; A multi-frame counter that generates a multi-frame alignment pulse and a third clock, a serial digital signal train, a transmission line sending circuit that sends out a frame alignment pulse and a third clock to a transmission line, and all the above-mentioned components. In the first device, the phase comparator circuit compares and verifies the timing phase between the frame alignment reference pulse and the frame timing pulse from the second device, so that this phase relationship is always a predetermined relationship. A digital signal transmission system characterized in that it is configured to control the multi-frame counter and automatically set the timing phase of the multi-frame pulse to the second device.