KR890002480B1 - Digital link telephone station sets - Google Patents

Abstract

The integrated circuit at the user's end includes a modem for modulating and demodulating signals which are carried by the twisted pair. The modem is connected to a voice data and control device. A timer synchronised with the digital signals carried by the link couples one field of each transmitted frame to the voice device, a second field to the data device and a third field to the control device. The controller provides signals not only to the voice and data device but also provides for selective communication of control signals to ports.

Description

Digital Link Device for Telephone Station Operation Set

1 is a diagram illustrating a computerized Giro switchboard and some stations receiving services by the Giro switchboard.

FIG. 2 is a diagram for explaining a digital line card which is part of the computerized giro exchanger shown in FIG.

3 is a diagram for explaining a digital transmission system used in an embodiment of the present invention.

4 is a block diagram for explaining a connection relationship between a digital link integrated circuit and a hybrid network of the present invention.

5A, 5B and 5C are block diagrams for explaining a digital link integrated circuit used as a downlink digital circuit.

6 is a block diagram for explaining various protocol levels used in the present invention.

7 is a block diagram of an integrated channel circuit used in a computerized giro switch or the like in the present invention.

8 is a block diagram of a hybrid network used in the present invention.

9 is a block diagram of a modulator / demodulator that is part of the circuit of the present invention.

10 is a block diagram of a toggle logic circuit that is part of a digital link integrated circuit.

11 is a block diagram of a timing generator in an integrated channel circuit for controlling data from link timing to exchange timing.

* Explanation of symbols for the main parts of the drawings

20: Giro Exchange 21: TDM Bus

22: CPU 23: TDM Controller

24: trunk guide 25: digital line card

26: analog card 27: card

30: twisted pair track 31: display speaker phone

32: speaker phone 33: data / voice work station (telephone station operation set)

34: phone 37: buffer memory

38: microprocessor 39: integrated channel circuit (ICC: uplink circuit)

40: hybrid network 44: digital link integrated circuit (downlink circuit)

46: keyboard module 47: track

48: display module 50: voice channel

52: data communication channel 54: modulator / demodulator

55: phase lock loop circuit (PLL circuit) 56: timing generator

61: error control circuit 67: voice means

68: data communication means 72: toggle logic circuit

73: Latch 74: Mice

75: module instruction register 76: interrupt means

77: module data register 78: free link state register

80: scanner 81: handshake circuit

83: mux 86: error retransmission latch

88: voice control register 90: ringer

91: logic circuit 92: digital / analog converter

93: Analog / Digital Converter 94: Interrupt Logic

95: MUX 97: Data Communication Scanner

100: phase lock loop circuit 102: link reset generator

104: modulator / demodulator 106: timing generator

107: data and error phase shift register

109: data and error decoder 110: frame adjustment circuit

112: error buffer 114: time conversion buffer

115: mux 116: ICC control register

118: Mode latch 128: Digital filter

129: flip-flop 130: flip-flop

135: phase lock loop circuit 136: reclock circuit

147: flip-flop 148: flip-flop

149: pattern detector 150: flip-flop

155: flip-flop 156: mux

157: flip-flop 158: phase detector

161: data waveform 164: ferrite core transformer

168: differential amplifier 171: waveform shaping circuit

180: parallel parallel register 182: command latch

183: Register selection latch

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for transmitting voice and data in a digital manner, and more particularly to a digital link apparatus for a telephone station set.

[Background]

Most telephones are connected to a central office or private branch exchange (PBX) via a pair of tracks, such as a twisted pair, which requires a lot of capital and is virtually random to change. Difficult to make Analog signals (voice signals), signaling information, and species currents are all transmitted through these pairs of lines. These twisted-pair lines are easy to install and inexpensive, so they are still coaxial even in the construction of new office buildings. It is installed more than cable.

Today, digital transmission bodies used for transmission and switching of voice signals are not new in long-distance communication where no twisted pair lines are used. Conventional twisted pair lines connected to the ends of the digital transmission bodies are digital signals. Because it is relatively unsuitable for sending it. Analog signals are used in the majority of telephone networks connected to the twisted-pair lines. On the other hand, most of the high frequency distortions that deform the front and end portions of the digital signal transmitted by the digital transmission body are generated in the twisted-pair line, and in installing typical twisted-pair lines, due to the close point coupling between adjacent lines. Power fluctuations and other problems can cause signal loss.

[Purpose of invention]

The present invention has been made in view of the above-described problems, and provides a circuit and a protocol for transmitting a digital signal on a twisted-pair line, and in particular a link device and a display for connecting various data or video paths to the twisted-pair line. It is an object of the present invention to provide a digital linkage device that has a sophisticated set of connections and connects a telephone station operation set with a private branch exchange (computerized branch exchange switch).

The link device here allows both digital data and voice transmission on a single twisted pair line. In addition, the present invention solves the problem of digital transmission occurring on a twisted-pair line according to various protocols.

Overview of the Invention

Briefly summarized the present invention for achieving the above object is as follows.

A pair of integrated circuits installed along the line drivers are used to provide digital link devices on common twisted-pair telephone lines, which enable simultaneous transmission of voice and data. In an embodiment of the invention, the linking device connects a telephone station operation set, data terminal, or similar device to the computerized branch exchange.

Specifically, among the pair of integrated circuits, an integrated circuit at the end of the user side (downlink) includes modulation means for modulating and demodulating a signal carried by a twisted-pair line. It is connected to data means and control means. Further, the timing means synchronized according to the digital signal carried by the link device connects the first field of each transmitted frame to the voice means, the second field to the data means, and the third field to the control means. Here, the control means supplies control signals to the voice and data means, and also supplies control signals to a plurality of ports for selective communication of the control signals. These ports may be connected to a series of data and control means, meaning "serial", meaning asynchronous links of other protocols than those used by voice. For example, one port connects to a keyboard scanner or display and data terminal.

Unlike the integrated circuit, the integrated circuit performs the same function as the downlink circuit in the branch line switch of the twisted-line end, and the timing from the data rate of the branch switch to the data rate of the link device. Provide additional conversion. This integrated circuit performs independent error coding and retransmits the control field to verify that the data field was received correctly.

EXAMPLE

Best Mode for Carrying Out the Invention The best embodiment of the present invention will now be described in detail with reference to the drawings.

For example, a device for providing digital links between telephone station operation sets, data terminals, or similar devices of a computerized branch exchange is as follows. The device of the present embodiment is a digital signal widely used especially in a telephone network. It is suitable for communication. Hereinafter, the components of the present invention will be described item by item, and well-known techniques will not be described in detail.

1) Connection relation of another device in the present invention in a communication network

The device according to the latest embodiment of the present invention includes a pair of integrated circuit chips made of well-known complementary MOS (CMOS) technology, one of such chips is a digital link device, which is composed of a large scale integrated circuit and includes a data terminal and It is located in the downlink similarly. The other chip is sometimes called an integrated channal crtcuit (ICC), which is typically installed in a digital line card in a computerized giro switch.

The chips provide a digital signal coupled to a hybrid network (hybrid network 40 schematically shown in FIG. 4 and specifically shown in FIG. 8).

The hybrid network provides a driving signal level for transmitting a digital signal on a twisted-pair line. In this embodiment, a typical twisted pair track is more than 5000 feet in length, and a track such as a coaxial cable may be used as such a track.

FIG. 1 is a circuit block diagram showing how the present invention is applied to a computerized giro switchboard, such as made by Rom Corporatio, located in Santa Clara, California, where a typical computerized giro switch 20 is a digitalized voice signal. And a time division multiplexing bus 21 through which data signals are switched, and the CPU 22 controls the TDM 21 through the TDM controller 23. In addition, trunk card 24 provides an interface between a public telephone network or a similar network, and other cards are connected to bus 21 and a telephone station operating set. It is also possible to employ analog techniques such as 34 and analog cards 26.

On the other hand, the card 27 is used to receive the data switched on the bus 21, and in a typical application, the analog card 26 receives the analog signal from the telephone 34 and the RDM bus 21. Convert to digital signal to switch on phase. These digital signals are converted back into analog form for connection to trunk lines or telephone stations. In addition, in the present embodiment, the integrated channel circuit 39 is included in the digital phoneard 25, thereby displaying the display speaker phone 31, the speaker phone 32, and the data / voice working station 33: DATA / VOICE WORK STATION: Signal transmission between various communication means such as telephone station operation set is allowed.

The device according to this embodiment described above is particularly adapted for operation on a conventional twisted pair track 30.

In FIG. 2, the digital line card 25 is connected to the TDM bus 21 through the buffer memory 37. The movement of the data to or from the buffer memory 37 is controlled by the microprocessor 38. In addition, each twisted-line line 30 is connected to the buffer memory 37, respectively, via an overlink circuit, that is, an integrated channel circuit 39 (ICC). This circuit will be described in more detail later with reference to FIG.

At the end of the downlink, the twisted-pair line 30 is connected to the hybrid network 40 of the work station 33. (The hybrid network 40 of the link and the downlink is the same.) The hybrid network 40 is connected to the downlink circuit, that is, the digital link integrated circuit 44, which will be described in detail later with reference to Figs. 5A to 5C. Integrated circuit 44 to be described later is to be able to communicate with the processor, the display module 48, the voice channel 50, the data communication channel 52 and the like connected to the keyboard module 46 and the line 47. Here, the keyboard module 46 coupled with the line 47 and the display module 48 is actually an asynchronous channel using a different protocol from the voice channel 50 or the data communication channel 52.

2) Outline of digital transmission system used on link device

First, the ICC 39 transmits a single pattern for activating and synchronizing the digital link IC 44 (downlink circuit). When synchronization occurs once, each frame is transmitted in the bidirectional line 30 in both directions. do. As shown in FIG. 3, each frame includes 32 bits transmitted in a cycle of 125 microseconds. The first field of 8 bits is a data field, and one parity bit. ) Follows. The second field of 8 bits is also a data field, followed by one parity bit. The next 8-bit field is a voice field, followed by one parity bit. The last field of 4 bits is a control field, followed by the last 1 bit, which becomes a parity bit. The complete control sequence requires a "super frame" consisting of eight frames shown in FIG. As will be described later in detail, the first 8 bits of each control message sent to the downlink side are echoed. In other words, the control link is returned from the digital link integrated circuit 44 to the ICC 39 on the left link side to confirm whether the control field is correctly received. On the other hand, when "framing" is lost, resynchronization occurs (errors in the transmission are detected to initiate resynchronization).

As shown in FIG. 3, the digital link apparatus in each direction transmits 64K bps of voice, 120K bps of data, 32K bps of control information, and 32K bps of error enconding. In an embodiment of the present invention, the voice is encoded using mu 255 PCM encoding, and the data uses 8 bits per character with additional 8 bits for parity and clock signaling. In addition, the control message has a length of 16 bits and is repeated once again. On the other hand, the Manchester coding method is used for transmission on the twisted-pair line 30.

The hybrid network 40 supplies a driving current for the twisted-pair line 30 and performs a duplexing function. In addition, each network 40 receives the differential transmission signal and supplies the received signal for the corresponding integrated circuit. This integrated circuit is shown as an ICC 39 and a digital link integrated circuit 44 providing XMITT + and XMITT− to the hybrid network 40 while receiving RCV signals as shown in FIG.

3) digital link integrated circuit (downlink circuit 44)

As shown in FIG. 4, the downlink circuit 44 (digital link integrated circuit) communicates with the hybrid network 40. In FIG. 5a, the XMITT lines 56 and 57 (pins 2 and 3) and the RCV are shown in FIG. The binding state between the downlink circuit 44 and the network 40 by the line 58: pin 1 is shown (the pin numbers of the integrated circuit 44 are enclosed in a quadrangle). The XMITT lines 56 and 57 receive a signal from the modulator of the modulator / demodulator 54, and the RCV line 58 is connected to the modulator / demodulator 54 while also providing a phase lock loop circuit 55 (PLL circuit). Connected. The first and second data fields of 8 bits (Fig. 3) are generally connected to the data communication means 68 shown in detail in Fig. 5C, while the 8-bit voice fields are shown in detail in Fig. 5B. 67). In addition, the control field includes i) control of the data communication means 68 shown in FIG. 5C, ii) control of the audio means 67 shown in FIG. 5B, iii) the keyboard 46 and the display 48. It is preferentially used by the circuit shown in Fig. 5A for various purposes including communication between modules coupled to digital link circuits such as the like (both data and control communication).

The phase lock loop circuit 55 is a conventional PLL circuit that allows the digital link integrated circuit 44 to remain locked by the transmitter of the bit set by the ICC 39. In this regard, when a reception error is detected by the error control means 61, the ICC 39 on the left link side retransmits the synchronization signal allowing the resynchronization of the PLL circuit 55. FIG. The PLL circuit 55 supplies 512 KHz to the timing generator 56 in addition to the link reset signal.

The modulator / demodulator 54 modulates the outgoing data into a Manchester code (basically converted by a 256 KHz square wave) and demodulates the incoming Manchester-coded signal, which demodulates the demodulator 54. It is shown in detail in the figure.

The output and input signal of the modulator / demodulator 54 are also supplied to the error control circuit 61. The bit form transmitted and received between the error control circuit 61 and the modulator / demodulator 54 is basically formed. As shown in Figure 3 (this also includes the parity error bit). The error control circuit 61 checks the parity of incoming data and voice and control signals and generates parity bits for outgoing data. In addition, the error control circuit 61 supplies an error signal on the line 87 when a parity error is detected. This error signal is connected to a suitable circuit, for example, when an error is detected in the data field, this signal is supplied to the multiplexer 95 (MUX) of the 5c.

The timing generator 56 provides priority timing for the digital link circuit, which will be described later. In this timing generator 56, for example, two fields (data fields) of 8 bits are connected from the line 63 to the data communication means. A timing signal is supplied to 68 and to ensure that the third field (voice field) is supplied to the voice means 67. The timing generator 56 also generates a control bit in each frame that is connected to the various circuits shown in FIG. 5C to perform the control functions for the modules described below. In addition, the timing generator 56 supplies a timing signal for transmission data, for example, two 8-bit data fields are supplied to the error control circuit 61 in advance of the 8-bit field from the voice means 67. Then, a timing signal is supplied to the multiplexer 83 (hereinafter, abbreviated as MUX) in order to allow the 4-bit control field to be supplied later.

As shown in FIG. 5A, the digital link integrated circuit 44 allows connection to three "modules" (three outputs from the mux 74 (pins 33 to 35) when more modules are needed. May be decrypted to provide a selection of. In this embodiment, the digital link integrated circuit 44 is adapted to provide communication with a keyboard, display, data terminal, and the like.

One of the three modules is selected via selection latch 73 and mux 74, where service requests from the selected module and data from the module are received at pin 25. In addition, the recognition signal for the module and the data for the module are sent to the selected module, and the data from the module or the data to the module is sent into the control field through the module data register 77. That is, the data from the module data register 77 is supplied to one of the modules through the mux 83, for example. In addition, the data coming from pin 25 passes through this register 77 and is then supplied to pins 2 and 3 through a passage including the line 64.

Toggle logic circuit 72 is shown in detail in FIG. 10. In general, this toggle logic circuit 72 tests a portion of the control field to determine if a change is occurring, and also the module data register 77. It controls the loading and interrupt signal on the interrupt means 76, scanning by a scanner 80, and the like.

Scanner 80 allows modules to be scanned through mux 74. In addition, when a request is received from one module, the scanner 80 stops operation and allows the overlink status register 78 to be loaded, for example by a service request from pin 25.

The keep link register 78 provides the state and characteristics of the keep link control transfer, for example, the off-hook position state from pin 5, the module interrupt, and the " activation " of data communication for the data communication means 68. Whether the power is lost or not (each component of FIG. 5A will be described in detail when explaining the operation of the circuit).

Referring to FIG. 5B, the incoming voice field is supplied to the output pin 8 through the rare retransmission latch 86 on the line 63. The digital / analog converter 92 (part number-National TP 3054) is installed outside the digital link integrated circuit 44. This is used to convert the digital signal into an analog signal. On the other hand, if an error is detected in the received signal, the error is transmitted to the error retransmission latch 86 via the line 87. This latch 86 uses the previous value when an error occurs. In addition, this latch 86 prevents sudden changes in speech waveforms that often cause unpleasant sounds when some bytes of data are lost. The incoming audio signal is converted into a digital form by an external analog / digital converter 93 and supplied to pin 7 of the digital link integrated circuit 44. Thus they are fed directly onto the track 65. Further, the timing signal from the timing generator 56 shown in FIG. 5A is supplied to the converters 92 and 93 via pins 9 to 11.

The control signal for the voice channel is supplied directly from the line 63 to the module data register 77. This control word is supplied to the voice control register 88 to provide the name signal and other functions. Three bits from this register 88 are connected to the ringer 90 to allow selection of the various ringing tones coming from pin 13, and the other line is used to operate the ringer 90. The various modes are, for example, like a fixed control signal with different power supply (pin 15) and pins 6, 12 and 29 for driving the speaker. It can be selected through the voice control register 88 and the logic circuit (91).

The off-hook switch condition is directly sensed by the overlink state register 78 and transmitted to the ICC 39 in the control field area of the line 65. In addition, the presence of a headset is also similarly recognized by the stay state register 78.

The data communication means 68 enables data transmission on the link at a relatively high transmission rate (128K bps). This data can be concentrated or transmitted to the telephone terminal of the telephone station, another data link or other means of data activation. The separate control signal is also received from or transmitted to the data communication means 68 via the control field.

As shown in FIG. 5C, the incoming data field is transferred to pin 22 via mux 95 on track 63. Control commands for the data communication means 68 from the control field are supplied to the module data register 77. Interrupt logic 94 also sends the command to pin 22 via mux 95 when an interrupt command occurs. The error signal on line 87 is also supplied to mux 95 and then to pin 22. On the other hand, the timing generator 56 controls the switching of the generator mux 95. For example, it controls to select line 87 when an error is detected in the data field.

The incoming data is supplied directly on the XMITT data line 66 from pin 21. This data is scanned by the data communication scanner 97 for instructions. The presence of such a command is recognized in the rest state register 78, and the command itself becomes part of the control field and is sent to the module data register 77 for transmission to the rest link. On the other hand, the timing signal for the data channel is supplied from the timing generator 56 to pins 23, 24 and 30.

The data communication means 68 may transmit or receive data independent of the voice data or data used as part of the voice means (e.g., a telephone capable of communication). That is, the terminal can transmit data on the twisted-pair line 30 independently of the telephone company operating set 33, and such data is computerized to or from a destination independent of the internal voice connection of the present embodiment. It may be switched to the branch exchanger (20). Clearly, there is a clear difference between data transmission and voice communication.

4) Integrated channel circuit (39: ICC)

An integrated channel circuit (ICC) 39 shown in FIG. 7 provides an interface between the hybrid network 40 and the buffer memory 37 shown in FIG. This integrated channel circuit 39 does not perform the same module interface functions as the digital link integrated circuit 44, but between the relatively late digital signal transmission on the twisted-pair line 30 and the faster transmission associated with the TDM bus 21. Provides cushioning function. This channel circuit 39 also performs a phase shift function such that all of the twisted pair lines 30 have the same delay time. In addition, any control function for the link is performed by the channel circuit 39. For example, the link reset signal is generated by this channel circuit 39. (This link reset signal synchronizes the downlink circuit 44 with the ICC 39 and the branch exchanger 20).

In the case of the ICC 39, the phase lock loop circuit 100 is directly controlled in timing by a timing signal generated from the computerized branch exchange switch 20. In the best embodiment, the timing generator 106 receives the reset signal of 1 KHz and the 512 KHz signal. Thus, the downlink circuit 4 operates synchronously with the branch exchange 20, even at a lower transmission rate.

The stream of bits received encoded by the Manchester type from the downlink circuit 44 is supplied to the modulator / demodulator 104 through the phase lock loop circuit 100, and the output of the modulator / demodulator 104 is third. It includes the demodulated error signal together with the data (including parity) received in the format shown in FIG. This error signal is a universal signal that indicates the "difficulty" that a demodulator has to detect a received signal during the decoding of a Manchester coded signal. The data and error phase shift register 107 provides a delay function which is a function according to a 3-bit signal received from the ICC control register 116. The output of this register 107 is supplied to the data and the error decoder 109 where the parity of the data is checked and then to the frame adjustment circuit 110 which provides a fixed time delay to both the error and the data. Supplied. The main data path flows from the phase lock loop circuit 100 to the time varying buffer 114 through the mux 115. The detected error is supplied from the error buffer 112 to the buffer memory 37 when it is enabled by the chip select signal.

The data passing through the time conversion buffer 114 from the branch exchange switch 20 through the buffer memory 37 is supplied to the data and the error decoder 109 which are the places where the parity bits are generated. From there, the data is passed through the mux 101 to the modulator / demodulator 104, which is encoded in Manchester before being fed to the hybrid network 40.

In initialization, the link reset generator 102 transmits a unique pattern of signals to the digital link integrated circuit 44 as described above to synchronize the phase lock loop circuit 55 of the digital link integrated circuit 44. . Then a predetermined bit flow is supplied from the buffer memory 37 to the data-in line and returned from the downlink circuit 44 to the ICC 39 of FIG. 7 (i.e., it connects the twisted-line line 30). Is sent through). Most of the delay that appears when passing through the twisted-line 30 is determined by the microprocessor 38 shown in FIG. 2, which is used to set the delay in the register 107. . That is, the delay time in the register 107 is set to a total delay time including the delay time in the twisted-line line 30, the register 107, and the regulating circuit 110 and other circuits. Since the same predetermined delay time is used for all links, it appears that all links have the same delay time for the branch exchange switch 20. Also, the frame adjustment circuit 110 is used in the present best embodiment. Provides a delay time for bringing the predetermined delay time to the total delay time If a transmission error occurs, the link is reset through the mode latch 118 and the ICC control register 116. This reset function Includes a delay reset function of the register 107.

On the other hand, the time conversion buffer 114 is a relatively late connection between the fast transfer generated by the buffer memory 37 and the TDM bus 21 and the circuit shown in FIGS. 5 and 7 and the twisted-pair line 30. Provides time conversion between transfer rates.

As mentioned above, some control fields are retransmitted to the ICC 39 to ensure that they are properly received by the digital link integrated circuit 44. In this case, a return path is provided through the ICC control register 116 and the mux 115 so as not to unnecessarily wait for the next frame for unretransmitted data.

5) Operation of the digital link integrated circuit 44

First, referring to FIG. 6 to explain the various protocols used in the present invention, it is most easily understood that the operation of the digital link is first noted that there are several protocol layers reflected between each transmission. The top level is user level 120, shown in FIG. 6, which may include, for example, the user pressing a key on the keyboard. The next level, message level 121, can be easily seen by the following analogy. In fact, the ICC 39 transmits a frame that acts as an envelope for the digital link data carried by the digital link integrated circuit 44. The letter and envelope returned require 16 bits (4 frames) with recurring 4 bits of control data. The next level, the physical layer 122, is the framing of the data and voice and control signals shown in FIG. In addition, the lowest layer, the electrical layer 123 is a signal that is actually transmitted on the twisted-line line 30, including the parity signal, Manchester-coded data and voice control signal.

Assume that one of the modules connected to the digital link integrated circuit of FIG. 5A is a keyboard microprocessor [more specifically, a commercial unit (COPS 444L)]. Such commercially available microprocessors are used to provide digital signals representing pressed keys and also to scan the keyboard. Suppose that the circuit of FIG. 5A scans (ie, the scanner 80 periodically selects a module through pins 33, 34, 34). The key may have been pressed corresponding to the user level 120 of FIG. When the keyboard is selected, pin 25 shows the service request (SRQ) signal. This signal stops scanning and causes the run-link state register 78 to load a signal from pin 25 to register 77 indicating that service has been requested by the keyboard.

The ICC 39 continues to send the frame in the format shown in FIG. 3 even if voice or data do not pass over the link. In other words, the predetermined control field is continuously monitored by the toggle logic circuit 72 to determine whether there is a service request from the ICC 39. According to the present example, the keyboard is in a state in which a predetermined pattern is included in the control field from the overlink state register 78 through the error control circuit 61, the modulator / demodulator 54 and the twisted-pair line 30. It is returned to ICC 39 to indicate that it is working. It is the microprocessor 38 of FIG. 2 that determines that the keyboard is working.

The microprocessor 38 then prepares a suitable message in the control field requiring that the current job be delivered. This message is sent to the digital link integrated circuit 44 via the ICC 39 and the twisted-pair line 30, and its control field is loaded into the registers 75 and 77. The keyboard is then selected via pin 33, the module command register 75 establishes a condition, the module data register 77 is cleared, and the interrupt means 76 issues an interrupt requesting the transfer of the job to the keyboard microprocessor. Occurs on. The keyboard microprocessor then supplies a suitable clock signal to pin 26 and the data on pin 25 is loaded into the module data register 77.

It should be noted that data is transferred to the module data register 77 at a rate compatible with the keyboard microprocessor. The handshake circuit 81 may provide other module protocols. For example, the module data register 77 contains an 8-bit word that represents a special key pressed on the keyboard. The data from the module data register 77 (in the control field) is returned to the ICC 39 and interrupted by the microprocessor 38 and stored in the buffer memory 38.

Pressing a particular key will be scanned on the TDM bus 21 via the TDM controller 23 in FIG. 1 and stored in the storage associated with the CPU 22. In a typical computerized branch exchanger 20 the CPU 22 may be operable in response to pressing a number of keys, for example, to complete the connection with the voice channel 50 shown in FIG. have.

Similar to the above, a command is sent to the display device by enabling the display through pin 34 and also supplying data through pin 28. Here, data for the module is transmitted through the control field.

6) Demodulator of the demodulator / demodulator 54

Referring to FIG. 9, in general, the received signal determines when the flow of incoming data has passed by [+ XITION, track 142] and Bucheon through [-XITION, track 141]. Differentiate to make a difference. In addition, the output of the gate 134 provides a signal for all transitions. For all the Manchester coding schemes employed in this best embodiment, the transition represents binary 1 and the secondary represents binary 0. If a transition occurs within this window or gate, the window or gate is interpreted and determined, while otherwise an error signal (output of bistable circuit 148) is generated.

는 NAND게이트(131),(132)에 공급된다. 그리고 상기 게이트(131)의 출력은 게이트(132)의 출력이 부천이신호를 제공하는 동안 정천이신호를 제공하는 바, 이 두신호는 게이트(134)의 출력(AXITION)으로 된다. 또한, 이 신호(AXITION)는 위상잠금루우프회로(135)에 공급되고 재클록회로(136)에도 공급된다.The received signal is first fed to a digital filter 128 (hysteresis filter), which removes the "skirt" leading the front edge of the data pulse and following the rear edge. The filtered received signal is digitally differentiated after being supplied through a latch. This differential operation occurs in the flip-flops 129 and 130 which are bistable circuits. In addition, the output Q of the flip-flop (129, 130) and

Is supplied to the NAND gates 131 and 132. In addition, the output of the gate 131 provides a transition signal while the output of the gate 132 provides the sub-transition signal, and the two signals become the output (AXITION) of the gate 134. This signal AXITION is also supplied to the phase lock loop circuit 135 and also to the reclock circuit 136.

In the above embodiment, the downlink circuit 44 and overlink circuit 39 which are themselves crystal-controlled are clock controlled by their timing generator while the transmission on the link is synchronized by the operation of the branch exchange 20. According to the above-described embodiment, the downlink circuit 44 uses a 6 MHz clock and the left link circuit 39 (ICC) uses an 8 MHz clock. This high frequency clock signal is usually used for phase locked loop circuits after being divided. The use of such an independent timebase can cause phase problems, especially when data is returned to the branch exchange switch 20.

The circuit for compensating the above independent timebase will be described later with reference to FIG. On the other hand, the signal in the line 138 of FIG. 9, denoted VHF, is a timing signal produced from the crystal-controlled oscillator of the digital link integrated circuit 44 or the integrated channel circuit 39. This signal is supplied to the digital filter 128 and the digital differentiators 129 and 130.

In addition, the signal AXITION from the gate 134 is reclocked through the reclock circuit 136 to adjust the timebase of the phase lock loop circuit 135. The adjusted signal is then supplied to the data terminal of the flip-flop 148 and the pattern detector 149. This pattern detector 149 is a standard circuit used for detecting a predetermined pattern for Manchester encoding. The output of the pattern detector 149 is connected to the data terminal of the flip-flop 150 through the gate 151 to provide a synchronization signal. The clock signal from the phase lock loop circuit 135 (signal used to reclock the reclock circuit 136) is also used to clock control the flip-flop 150. Furthermore, the signal at the output of the flip-flop 150 (line 152) is supplied to the gate and window used to examine the data to determine whether the filter has changed and the differential RCV signal has changed.

The data is detected through the NAND gates 142 and 143. One of the two input terminals of the gates 142 and 143 is connected to the line 152, while the other input terminal of the gate 142 receives the sub-transition signal (-XITION) through the inverter from the line 141. The other input terminal of the gate 143 receives a transition signal (+ XITION) through the inverter from the line 142. Outputs of the gates 142 and 143 are supplied to latches formed of the gates 144 and 145. Also, the flip-flop 147 at the rear end is basically used to "square up" the waveform, which is clocked by the signal of the line 152.

The final data flow appears at the output terminal Q of the flip-flop 147. (In the case of ICC 39, the flow of this data is inverted to modify the clock base through the use of the circuit shown in FIG. 11.) Meanwhile, the reclocked signal AXITION is applied to the flip-flop 148. Supplied. One input terminal of the flip-flop 148 is connected to the line 152. If the change does not fail in the window, an error signal is generated, which is recognized by the data output from flip-flop 147.

7) Timing Generator 106 of FIG.

The data transmission of the link apparatus described above is synchronized with the change of the clock multiplexed in a time division manner. The ICC 39 and the digital link integrated circuit 44 have crystal-controlled oscillators, especially for their timing generation and for phase locked loop circuits. For example, because of each of these crystals, there is a continuous drift between the time division multiplexed (TDM) bus clock and the change in the ICC clock. Data transferred from the ICC 39 to the TDM bus 21 via the buffer memory 37 in FIG. 2 must overcome the shift between these different timebases. Referring to FIG. 11, the flow of data in the ICC 39 is supplied through the flip-flop 155. The flip-flop 155 is clocked by a TDM clock (clock of the branch exchange). In the figure, the TDM clock is shown in waveform 160 with the leading edge of the TDM clock occurring after time 159. If the leading edge of the TDM clock occurs after being secured as shown in FIG. 11, the flow of data output at the Q output terminal of flip-flop 155 will probably be aligned with the time at which the TDM clock is generated. In practice, however, the data waveform 161 will be aligned with the time at which the line is generated, as indicated by the arrow 162. In practice, however, the data waveform 161 will continue to move to the left and right of the line 159 as indicated by the arrow 162 (jittering phenomenon). This causes the data waveform to be distorted by the TDM clock signal, especially when the data waveform 161 occurs on the right side of the line 159. However, the circuit of FIG. 11 prevents the above phenomenon by moving the leading edge of the data from the edge of the TDM clock 160.

That is, data is first clocked through the flip-flop 154, and the time base in the flip-flop 154 is the timing signal VG CLK of the ICC 39. The flow of output data from the flip-flop 154 is supplied to one input terminal of the mux 156 through the flip-flop 157 which receives the VG CLK signal. This flip-flop 157 is used to delay time. Thus, the two inputs of the mux 156 are the data flow itself and the delayed data flow. On the other hand, the output of the phase detector 158 is to make the mux 156 select the flow of data or the flow of delayed data. That is, the phase detector 158 receives the TDM clock and the VG CLK, and a signal for controlling the mux 156 appears based on the phase difference between the two clocks. This phase detector 158 has hysteresis characteristics to prevent continuous selection between the two inputs of the mux 156 only when a slight phase change occurs between the two inputs of the phase detector 158.

The timing generator 106 of FIG. 11 allows the leading edge of the data pulse to occur clearly before the leading edge of the TDM clock 160. Specifically, in the TDM clock waveform 160 shown in FIG. 11, data change (waveform 161) occurs on the left side of the line 159. Thus, the data pulses are not distorted when passing through the flip-flop 155, i.e., shifted toward the TDM clock. When the leading edge of the data pulse begins to approach the line 159 as determined by the phase difference between the TDM clock and the VG CLK, the phase detector 158 causes the mux 156 to delay the data from the flip-flop 157. This allows the flow to be selected, whereby waveform 161 is shifted to the left. Similarly, when the waveform drifts too far left, a non-delayed data flow is chosen.

8) Toggle Logic Circuit 72 of FIG.

One of the functions performed by the present invention is to transfer control fields from the microprocessor 38 to the module data register 77. In addition, the contents of the buffer memory 37 are continuously transmitted to the digital link integrated circuit 44 which is a downlink. In a typical case, the microprocessor 38 needs about 10 msec to generate a complete Jayfield message. On the other hand, about 1 msec is required for message transmission. Thus, a message of partially incomplete control fields will continue to be sent on the downlink. One of the purposes of the toggle logic circuit 72 of FIG. 10 is to determine when a certain control field message is completed and when to accept it.

The field is divided into three fields. Although 4 bits are designated as "toggle" fields, only 3 bits are used in this embodiment. In addition, 4 bits are used for selection of registers and latches such as (73, 75, 77, 78) in FIG. 5A, and 8 bits are used for transmitting actual data in the control field.

The toggle field is continuously compared to the toggle field of Aff. As will be explained later, the change in the toggle field is used to indicate that the control message must be completed and loaded.

The toggle field and the register selection field of the control message (control field) are supplied to the serial / parallel register 180 of FIG. 10 from the RCV data line. This register 180 is clock controlled through an AND gate 188 that receives a 256 KHz signal and a link transition clock. The previous toggle field is stored in register 181, and the current and previous toggle fields are compared via EXOR gate 184. The change in the toggle field causes a change in the output of the OR gate 186, which is reflected via the instruction latch 182 and the AND gate 187. The output of the AND gate 187 is supplied as a signal that causes the register 181 to log the current toggle field from the register 180 to cause the current toggle field to be compared with the subsequent toggle field.

The toggle field is provided through a latch 182, for example, a clock signal to the registers 75 and 77 and the latch 73 of FIG. 5A, a control signal to the voice means 67, and a NAND gate 190. Commands are supplied to the scanner 80 of FIG.

On the other hand, the register selection field is decoded through the gate 185 and supplied to the register selection latch 183. This field provides a " write signal " to the registers 75, 77 and 78, as well as a selection signal for selecting those registers respectively. For example, it allows register selection to lock an 8-bit data field from a control field (latch 73 in FIG. 5A is shown with three output lines connected to mux 74 in FIG. 10).

If an error is detected in the control message, the toggle logic circuit 72 is reset to allow the entry of a new toggle field when the control message is repeated. As mentioned above, the control field messages are typically repeated more because the contents of the buffer memory 37 are continuously sent downstream until a new message is generated.

The link device tests the echo back to the overlink to determine if the message was received correctly as described above. However, the present embodiment does not use this echo characteristic. In fact, there is no handshake between the buffer memory and the free link circuitry to confirm that the message was received correctly. That is, because the message is repeated many times, this will be more satisfactory for a more sophisticated protocol. The advantage of the toggle logic circuit 72 described above is that first, a control message generated by the microprocessor 38 can be formed asynchronously with the link logic, and second, the microprocessor 38 needs to remove the message. There is no "harm" in messages that are repeated over and over until a new message appears. In fact, the continuous repetition of the message increases the precision of self-calibration.

9) Hybrid Network 40 of FIG.

The hybrid network 40 performs the traditional function of separating the input and output signals for the twisted-pair line 30, the hybrid network 40 is to be transmitted to the twisted-pair line 30 on the lines (173, 174). A signal is received and the RCV signal from the twisted-pair line 30 is supplied from the output terminal 175 of the differential amplifier 168.

The hybrid network 40 includes a ferrite core transformer 164 having a winding ratio N ₂ / N ₁ = 2 in the present embodiment, and the entire network except the differential amplifier 168 is composed of passive elements. For explanation of the action, for example. Assume that twisted-pair line 30 has a complex impedance Zo, and assume that impedance 165 is infinity and impedance 166 is zero. Then, by analysis of the remaining circuits. Signals on lines 173 and 174 will be canceled in differential amplifier 168 and will not appear on line 175. On the other hand, when a signal is received from the continuous line 30, it is detected by the differential amplifier 168 and appears on the line 175. (In the examples, R is nearly 10 KΩ, substantially greater than Zo.)

Impedance 165: ZL is specifically used to compensate for transformer leakage inductance at high frequencies. If this impedance 165 is not used, an imbalance in the high frequency band can cause any signal appearing on line 175 from lines 173 and 174. Also, impedance 166: Zm is used to compensate for the finite magnetization inductance of the transformer in the low frequency band. On the other hand, the waveform shaping circuit 171 is a simple inductance used to limit the high frequency component of the transmitter. Therefore, mutual interference between internal devices is reduced. The desired value of Zr shown in the equation of FIG. 8 is 2Zo.

[Effects of the Invention]

The present invention described above is useful for connecting a telephone station operation set, a data terminal, and a computerized branch exchange period. In particular, such a link device is useful for a typical twisted-pair line, and the data of a digital signal system on a twisted-pair line of a model. In addition, it is possible to solve various problems that are likely to occur in transmitting voice.

Claims (32)

Computer means (38,37) connected to the branch exchange switch (20) to prepare a message in a predetermined format: a message to be received from the computer means (38,37) and transmitted to the telephone station operation set (33). Prepare circuit (ICC) 39: A pair of transmission lines 30 connected to the stay circuit 39 to receive the message, and transmit and receive control signals for the telephone station operation set 33. Control means (61, 75, 77, 78), and the voice data field of the message to the telephone station set 33 and the control data field to the control means (61, 75, 77, 78) A timing generator 56 which operates in synchronization with the message carried by the pair of transmission lines 30 for the purpose of testing, and the control means for inspecting the message to determine when a newly completed message is sent to the downlink circuit ( Earth connected to 61,75,77,78) And a logic circuit 72 to receive the message from the pair of lines 30 and to prepare a message for supplying the telephone station operation set 33 to the pair of transmission lines 30. And a down link circuit (44) to be connected: a digital link device configured to provide digital communication between the branch exchanger (20) and the telephone station operation set (33). The error retransmission latch (86) of claim 1, wherein the downlink circuit (44) uses an erotic control circuit (61) for transmitting a message to detect an error, and an error retransmission latch (86) for reusing an already transmitted voice data when an error is detected. Digital link device comprising a. The digital link device according to claim 1, wherein the pair of transmission lines (30) are twisted pair lines. The method according to claim 1, wherein a pair of hybrid circuits (40) for connecting the overlink circuit (39) to the ends of the pair of transmission lines (30) and the downlink circuit (44) at the other ends are provided. Digital link apparatus, characterized in that. The microprocessor 38 according to claim 1, wherein said computer means (38, 37) are arranged to internally connect the time division multiplexing bus (21) of the branch exchanger (20) to the overlink circuit (39). And a buffer memory (37) adapted to be provided. The modulator / demodulator (104, 54) according to claim 5, wherein the left link circuit (39) and the down link circuit (44) modulate a signal transmitted on a single transmission line (30) and demodulate the received signal. And a digital link device, respectively. 7. The digital link device according to claim 6, wherein the demodulator / demodulator (104, 54) is adapted to perform Manchester type coding on modulation. The digital communication device according to claim 1 or 6, wherein the control means of the downlink circuit 44 includes a stay-link register 78 for receiving a control signal directly from the telephone station operation set 33. Link device. 9. The digital link device according to claim 8, wherein one of the signals directly received from the telephone station operation set (33) to the overlink status register (78) is an off-hook switch signal. Computer means (38,37) connected to the branch exchanger (20) for preparing and decrypting messages in a predetermined format; and receiving or receiving messages from the computer means (38,37). 37) ICC: 39 to transmit a message to the message circuit: a transmission line 30 connected to the jam link circuit 39 to transmit and receive a message to the Chuck circuit 39: voice means (67). ), And at least one digital port (25, 28: pin), and a selection latch 73 for selectively coupling a plurality of digital circuits external to the overflow circuit 39 to the digital ports 25, 28. Control means (61,75,77,78) for transmitting and receiving a control signal to and from the voice means (67) and an external circuit and providing a control signal to the selection latch (73), the first field in synchronization with the message. To supply the voice means 67 and the second field to the control means 61, 75, 77, 78. Generator 56, including a handshake circuit 81 which allows serial asynchronous data to be transmitted and received via the digital ports 25 and 28 at a different protocol level than that used for the transmission line 30; And a downlink circuit 44 connected to the transmission line 30 so as to receive a message from the transmission line 30 and to transmit a message to the transmission line 30. A digital link device adapted to provide digital communication between a branch exchange switch (20), a voice means (67), and a digital port (25, 28 pins). 11. The digital link device according to claim 10, wherein the transmission line (30) comprises a twisted-pair line. 11. The apparatus according to claim 10, wherein the left link circuit (39) and the down link circuit (44) modulate the signals transmitted on the transmission line (30) and demodulate / demodulators (104, 54) respectively. Digital link device, characterized in that provided. 13. The digital link device according to claim 12, wherein the modulator / demodulator (104,54) is adapted to perform Manchester coding on modulation. 12. The digital link device according to claim 10, wherein said computer means (38,37) comprise a buffer memory (37) to which branch exchanges (20) are connected between overlink circuits (39). 15. The digital link device according to claim 14, wherein the data in the buffer memory (37) is continuously transmitted to the rest link circuit (39) for transmission to the down link circuit (44). 16. The system according to claim 15, wherein the downlink circuit 44 includes a toggle logic circuit 72 for examining the second field of the message to determine when the newly completed message was sent to the downlink circuit 44. Digital link apparatus, characterized in that. 17. The digital link device according to claim 16, wherein the second field of each message is transmitted to the downlink circuit at least twice. 11. The method of claim 10, wherein the transmission line 30 is composed of a pair of lines and a pair of hybrid circuit network to connect the downlink circuit 39 and the downlink circuit 44 to the transmission line 30, respectively ( 40) is provided with a digital link device. 19. The digital link device according to claim 18, wherein the over link circuit (39) and the down link circuit (44) are each manufactured on a single substrate. Computer means (38,37) connected to the branch exchanger (20) for preparing and decrypting the message in a predetermined format; and receiving a message from the computer means (38,37), a pair of transmission lines A leave link circuit 39 for preparing a message to be transmitted on the 30 and receiving a message from the pair of lines 30 and preparing a message to be transmitted to the computer means 38, 37: voice means 67. And a data communication means 68, digital data ports 25 and 28 pins, a modulator / demodulator 54 for modulating and demodulating a signal received or transmitted to the pair of transmission lines 30, the modulator / demodulator Control means (61,75,77,78) connected to (54) for receiving a control signal in or incorporating the control signal in the message, and supplying the first field in the message to the voice means (67). And supplying a second field to the data communication means 68, and supplying a third field to the control means 61,75,77,78. And a timing generator 56 connected to the modulator / demodulator 54 to operate in synchronization with the message, for receiving a message from the pair of transmission lines 30 and The downlink circuit 44 is connected to the pair of transmission lines 30 so as to transmit a message on the transmission line 30. The branch exchange 20, the voice means 67, and the data are provided. A digital link device adapted to provide digital communication between communication means (68). 21. The apparatus according to claim 20, wherein the restlink circuit (39) and the downlink circuit (44) comprise error control circuits (107, 109, 61) for detecting an error from a received message. Digital linkage, characterized in that it transmits the detected error to computer means (38,37), while the downlink circuit (44) is adapted to convey the detected error to voice means (67). 21. The computer program according to claim 20, wherein said computer means (38, 37) comprise a buffer memory (37), wherein the contents of this buffer memory (37) are continuously downlink circuits (44) via a check link (39). Digital link device characterized in that the transmission to. 23. The digital link device as claimed in claim 22, wherein the downlink circuit (44) comprises a toggle logic circuit (72) for detecting when a newly completed message is transmitted to the downlink circuit (44). . 21. The digital link device according to claim 20, wherein one of the external circuits connected to the digital data ports (25, 28: pins) is a keyboard. 25. The digital link device according to claim 24, wherein the digital data port (25, 28: pin) is adapted to provide a serial asynchronous link of a protocol different from that used in a pair of transmission lines (30). 21. The method according to claim 20, wherein the third field is passed through the pair of tracks 30 by the control means 78 to confirm that the third field is correctly received by the downlink circuit 44. 39) retransmitted to the digital link device, characterized in that. 21. The apparatus of claim 20, wherein the downlink circuitry 44 comprises a continuous frame of messages to provide control signals for voice means 67, data communication means 68, and digital data ports 25, 28 (pins). And a web link register (78) for storing at least part of the third field. 21. The digital link device according to claim 20, wherein the overlink circuit (39) includes a modulator / demodulator (104) for demodulating and demodulating a message transmitted by a pair of transmission lines (30). 29. The method according to claim 20 or 28, wherein the modulators (104) and the demodulators (104, 54) of the churlink circuit (39) and the downlink circuit (44) transmit messages on a pair of transmission lines (30). A digital link device, characterized in that for encoding. 30. The system of claim 29, wherein a hybrid network (40) is provided for connecting the overlink circuit (39) to a pair of lines (30) and for connecting the downlink circuit (44) to a pair of lines (30). Digital link device characterized in that. 31. The digital link apparatus according to claim 30, wherein the overlink circuit (39) is an integrated circuit manufactured on a single substrate, and the downlink circuit (44) is also an integrated circuit manufactured on a single substrate. In the digital link apparatus configured to provide digital communication between the branch exchange switch 20 operating by the first timing signal and the telephone station operation set 33 operating by the second timing signal, a pair of transmission lines 30 and: Stay link circuit for receiving data from the branch exchange switch 20 via the pair of transmission lines 30 and supplying the data received from the pair of transmission lines 30 to the branch switch 20. (39): a downlink circuit 44 or the like connected to the pair of transmission lines 30 for receiving data from and supplying data from the pair of transmission lines 30, wherein: The remaining link circuit 39 includes a mux 156 for receiving the speedlock data synchronized with the second timing signal, and the data is delayed by adjusting the time with the second timing signal by receiving and delaying the data. Supply to A delay delay flip-flop 157, a phase detector 158 connected to the mux 156 and comparing phases of the first timing signal and the second timing signal to control the operation of the mux 156; And a flip-flop 155 configured to perform a gate operation on the output of the mux 156 under the control of the first timing signal, the time base of the data transmitted from the downlink circuit 44. Digital Wrinkle device, characterized in that to convert the time base of the branch exchanger (20).

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