JPS60105062A - Stack control method - Google Patents

Abstract

PURPOSE:To improve the performance for control stack by providing a store area for a flag showing an address mode to each address of a stack to attain identification of difference of modes despite the presence of a different address and to allow the mixture of different modes. CONSTITUTION:An area C is provided to a segment table origin (STO) stack 10 for comparison of the (flag) bit of an address mode signal ADM. Thus an output S is set at ''0'' since the signal ADM of the read data given from the stack 10 is set at ''1'' and the signal ADM which is applied directly to a matching circuit 18 is set at ''0'' respectively. This can show the discordance. For instance, a mode flag is set up in the area to show a specific address mode of 24 or 28 bits. As a result, it is avoided that a coincidence output is produced by mistake. Then the mixture of different address modes is allowed. Thus a perge translation look-aside buffer (TLB), etc. can be omitted when the address mode is changed. This improves the performance and the effective use of the stack 10.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for controlling an STO stack in a multiple virtual storage system in which different address modes exist.

Conventional technology and problems In memory systems that use virtual memory, ST'O (Segmen
tTable Origin) stack is provided, but
In conventional memory systems, the address mode is fixed, that is, if the address is represented by 24 bits, it is always like this, and there is no case where there is an address other than 24 bits, for example, which is represented by 20 bits, so the ST○ stack also changes the address mode. There was no need to deal with it. However, recently, memory systems have been developed that have variable address modes, for example, in some cases in 24 bits and in some cases in 28 bits. In this 24/28 bit addressing system, the difference between the two is 28-24=4 bits, so
If we apply a method in which the page size and segment size are expressed in 4 bits, such as the bit address method, and assume that the page size and segment size are fixed in the case of 28 bits, so the size is not specified, then the above difference is 4. Bits can be swapped with 4 bits for size specification, and the STO stack capacity can be left unchanged.

A convenient way to make the STO stack, etc. cope with address mode changes is to clear it and switch it to only store the new address mode. One method is to clear the STO stack and TI, B (Translator Lookaside Buffer) using a barge TLB instruction. However, this results in performance degradation, and it is not possible to mix and use devices with different address modes. Note that if they are mixed without being cleared, some of the address bits are swapped in the 24/28 bit system as mentioned above, so it is not possible to distinguish between swapped and non-swapped ones, and logical contradictions can be caused by matching check etc. There is a risk that it may occur.

Purpose of the Invention The present invention makes it possible to identify mode differences even when different address modes exist, so that logical contradictions do not occur in coincidence detection, etc., and therefore, it is possible to allow different modes to coexist and eliminate the need for a purge TLB. That is.

Structure of the Invention The present invention provides a segment table in a multiple virtual memory system in which different address modes exist.In an origin stack control method, an area for storing a flag indicating an address mode is provided at each address of the stack, and a segment table is stored at each address in the origin stack. A mode flag of the address is written together with the start address, etc., and when the multiple virtual memory system is accessed, the access address, read data of the stack read by the address, and a signal indicating the mode of the address are written. The present invention is characterized in that it is input to a match circuit to obtain a signal indicating a match or a mismatch, which will be explained next with reference to embodiments.

Embodiment of the Invention FIG. 1 shows an embodiment of the invention, in which 10 is an STO stack composed of RAM (Random Access Memory);
12 is its write register (control register);
14 is a selector, 16 is a read register, 18 is a match circuit that takes a match, 20 is a register that stores the current space identifier (STO-ID) for registration in the TLB, 22 is a hash processing circuit, and 24 is an address register. be.

Register 12 consists of two parts, CRO and CRI.
Bits indicating the page size and segment size among the address bits are stored in O. These bits are the 8th to 11th 4 bits of the address. The CRI contains the origin address of the segment table, which is the 8th to 2nd
It is 18 bits and 7 bits of 5. The STO stack has three areas A, B, and C for each address, and since it uses a 2-way < 2 May) system, there are two of each area. It is controlled by bit 0 of the address register 24, and when this bit is "0'', UP-WAY,"
1'' is defined as LCI-WAY. Fig. 2 is a diagram explaining this, and A and B are shown in the figure.

Each area C is divided into upper UP and lower L0 as shown. Area A contains the 8th to 11th bits of CRO in 24-bit mode, and the 4th to 7th bits of CRI in 28-bit address mode, and area B contains the 8th to 25th bits of CRI in any mode. A bit enters. The selector 14 makes such a selection. Area C contains a one-hit address mode signal (flag) ADM that becomes 1 in the 24-bit address mode and in the 0.28-bit mode.

The STO address consists of 18 bits from 8th to 25th, and the memory space represented by these is 2+8, but the STO Sukuk address does not need to be this wide, so in this example, 18 hints are compressed to 6 bits. . The hashing processing circuit 22 performs this compression processing, takes in the 8th to 25th bits of the CRI in the register 12 through the selector 14, and performs hashing by performing an exclusive OR operation. The output of this circuit 22 enters an address register 24 to access the STO stack 10.

To explain the operation, when reading the memory system, the address is also input to the register 12, and the 8th to 25th addresses of CR1 are
The bits pass through the selector 14 and are input to the hash processing circuit 22 and the match circuit 18. More specifically, the bit group sent from the selector 14 to the match circuit 18 is
Same as the bits sent to O stack 10, ADM=
When it is 1, bits 4 to 7 of CRI are included. After the address bits input to the circuit 22 are hashed, they enter the register 24 and read out the STO stack 1o. The read data (data stored in the area A-C at the address) enters the read register 16 and becomes one input of the match circuit 1B. As mentioned above, the 8th to 25th pins of the address are input to the other input of the match circuit, and the signal ADM indicating which of the 24/28 bit address modes the address belongs to is also input to the match circuit 1.
This is the other input of 8. When the human inputs on one side and the other side match, the match circuit 18 generates a signal S indicating this and sends it to the control circuit CTL. If there is a match output, it means that the data to be read is in the UP end or LO entry of the STO stack memory, and the CTL causes the data to be read. Also, at this time, the ID from the register 2o is loaded into the TLB. On the other hand, the fact that there is no matching output means that the target data is not in the STO stack memory, and the U
When neither the P entry nor the LO entry match, the old ID is removed and the contents of the register 12 and ADM are registered in the old entry. At this time, the old ID already registered in the TLB is partially purged.

Areas A and B of each address of the STO stack ■o.

As shown in FIG. 2, the contents of CRO and CR1 and a flag (ADM) are written in C when writing to the STO stack memory. (0) in this diagram is 1 of the STO stack
The addresses are shown, and each area A, B, and C is shown in the same figure (1).
It is divided into upper and lower as shown below. (1)
If both its upper UP and lower L○ are in 24-bit address mode, (2), f3); (4
) indicates that these are in 24/2B, 28/24.28/28 pinto address mode. As shown in the figure, whether the address mode is 24 bits or 28 bits, bits 8 to 25 of the CRI are stored in area B. However, in area A, bits 8 to 11 of CRO are stored in the 24-bit address mode, and bits 4 to 7 of the CRI are stored in the 28-bit address mode. That is, A
The contents of the area are 8 to 11 pins of CRO and CRI depending on whether the mode is 24-bit address mode or 28-bit address mode.
It is swapped with 4 to 7 bits of This process is performed by the selector 14 upon receiving the ADM signal. The data written to flag area C is 0.0 when the address mode is 24 bits.
It is 1 in 28-bit address mode.

The match circuit 18 compares the data in areas @A, B, and C read from the STO stack, the contents of the register 12 from which it was read, and ADM. 11 bits and 8 to 25 bits of CR1 and 0 (ADM), 4 to 7 of CR1 when ADM=1
BISO1-, CRI 8-25 bits and 1 (ADM). If these match, the output S of the match 1i818 will be 1 (match). By the way, if area C is not provided in the STO stack 10 (of course there is no ADM input to 18), bits 8 to 25 of the read CRI will be equal to that of the register 12, and the data of the read area A will be the same as that of the CRI. If there are 4 to 7 bits and this is equal to 8 to 11 bits of CRO of the register 12, the match circuit 18 will produce a match output even though they should not match. In this regard, if an area C is provided in the STO stack as in the present invention and the ADM bit is also compared, in the above case, the ADM of the read data from the STO stack is 1.
．． Since the ADM directly applied to the 77-chip circuit 18 is 0, the output S is 0, which can indicate a mismatch.In other words, as in the present invention, an area blc is provided and 24 bits
Setting a mode flag indicating which of the 28-bit address modes is in place will prevent accidental matching outputs, and will also allow different address modes to coexist, so that when the address mode changes, the barge TLB,
There is no need to perform a clear STO or the like.

In the 2-way method, when writing to the STO stack at a certain address, if it is the first one, the upper U
When writing to the P entry section and then rewriting at the same address, write to the lower LO entry section,
The address is now full. Then, when a request to write to the same address is issued again, a method is adopted in which the old one is removed and written there. Since the STO address (8 to 25 pins of CRI) is the upper bit of the atrus, it is natural that they can be the same access (read/write) address, and as a result, the above-mentioned erroneous match detection may occur.

Providing the area C increases the capacity of the STO stack 10, but the RAM constituting the stack has a fixed number of bits per word, and is generally used with some bits remaining. Therefore, area C may be configured using these remaining bits.

As described in detail, according to the present invention, purge T can be achieved by simple means.
This is extremely effective as it eliminates the need for LB, improves the performance of the STO stack, and makes it more effective.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, and Fig. 2 is a block diagram showing an embodiment of the present invention.
FIG. 3 is an explanatory diagram of the storage contents of the TO stack. In the drawing, 10 is the STO stack, C is the flag storage area,
18 is the Mabuchi circuit. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi 1 ill 2 2nd plan

Claims (1)

[Claims] Segment in multiple virtual memory system where different address modes exist!・Table In the origin stack control method, an area for storing a flag indicating the address mode is provided at each address of the stack, and the mode flag of the address is written to the address along with the segment chill pull start address, etc. Hypothetically, when a system accesses 9, the access address, read data of the stack read by the address, and a signal indicating the mode of the address are input to a match circuit, and a signal indicating a match or mismatch is generated. A method for controlling a segment table origin stack, characterized in that the segment table origin stack is obtained.