JPS60104988U - fritska circuit - Google Patents
fritska circuitInfo
- Publication number
- JPS60104988U JPS60104988U JP19541283U JP19541283U JPS60104988U JP S60104988 U JPS60104988 U JP S60104988U JP 19541283 U JP19541283 U JP 19541283U JP 19541283 U JP19541283 U JP 19541283U JP S60104988 U JPS60104988 U JP S60104988U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- capacitor
- series
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Audible And Visible Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の回路図、第２図は本考案の実施の１例
を示す回路図である。
１・・・乾電池、２・・・報知器、３・・・第１トラン
ジスタ、４・・・通電回路、５・・・第１抵抗、６・・
・第２抵抗、７・・・バイアス抵抗回路、８・・・第３
抵抗、９・・・第１コンデンサ、１０・・・時定数回路
、１１・・・第２トランジスタ、１２・・・第２コンデ
ンサ、１３・・・第３トランジスタ。FIG. 1 is a circuit diagram of a conventional example, and FIG. 2 is a circuit diagram showing an example of implementation of the present invention. DESCRIPTION OF SYMBOLS 1... Dry battery, 2... Alarm device, 3... First transistor, 4... Energizing circuit, 5... First resistor, 6...
・Second resistor, 7...bias resistance circuit, 8...third
Resistor, 9... First capacitor, 10... Time constant circuit, 11... Second transistor, 12... Second capacitor, 13... Third transistor.
Claims (1)
タ３を直列接続して成る報知器２の通電回路４と、第１
抵抗５に第２抵抗６を直列接続して成る第１トランジス
タ３のバイアス抵抗回路７と、第３抵抗８に第１コンデ
ンサ９を直列接続して成る時定数回路１０とを互いに並
列に接続し、第２抵抗６に、第１コンデンサ９の所定充
電電圧でＯＮする第２トランジスタ１１を並列接続し、
第１トランジスタ３に、第２コンデンサ１２を並列接続
し、第１コンデンサ９に、第２コンデンサ１２の所定充
電電圧でＯＮする第３トランジスタ１３を並列接続した
ことを特徴とするフリッカ回路。The energizing circuit 4 of the alarm 2 is formed by connecting the first transistor 3 to the alarm 2 in series to the dry cell 1 of 1.5 cm, and the first transistor 3 is connected in series to the alarm 2.
A bias resistance circuit 7 for the first transistor 3 formed by connecting a second resistance 6 to a resistance 5 in series, and a time constant circuit 10 formed by connecting a first capacitor 9 to a third resistance 8 in series are connected in parallel to each other. , a second transistor 11 that is turned on at a predetermined charging voltage of the first capacitor 9 is connected in parallel to the second resistor 6;
A flicker circuit characterized in that a second capacitor 12 is connected in parallel to the first transistor 3, and a third transistor 13 that is turned on at a predetermined charging voltage of the second capacitor 12 is connected in parallel to the first capacitor 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19541283U JPS60104988U (en) | 1983-12-21 | 1983-12-21 | fritska circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19541283U JPS60104988U (en) | 1983-12-21 | 1983-12-21 | fritska circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60104988U true JPS60104988U (en) | 1985-07-17 |
Family
ID=30752963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19541283U Pending JPS60104988U (en) | 1983-12-21 | 1983-12-21 | fritska circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60104988U (en) |
-
1983
- 1983-12-21 JP JP19541283U patent/JPS60104988U/en active Pending
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