JPS60104552U - electronic key device - Google Patents
electronic key deviceInfo
- Publication number
- JPS60104552U JPS60104552U JP1983197469U JP19746983U JPS60104552U JP S60104552 U JPS60104552 U JP S60104552U JP 1983197469 U JP1983197469 U JP 1983197469U JP 19746983 U JP19746983 U JP 19746983U JP S60104552 U JPS60104552 U JP S60104552U
- Authority
- JP
- Japan
- Prior art keywords
- key
- pulse
- setting
- encoded
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Lock And Its Accessories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示し、第1図及び第2図はキ
ーの夫々表状態及び層状態の側面図、第3図は電子キー
装置の電気的構成を示すブロック線図、第4図a7”7
至d及び第5図a乃至dは作用−説明用の透孔列及び各
部の波形図である。
図面中、1はキー、2及び3は第1及び第2の透孔列(
第1及び第2のパルス発生手段)、4及び6並びに5及
び7は第1及び第2の投光素子並−びに第1及び第2の
受光素子(第1及び第2の検知器)、9及び10は第1
及び第2のシフトレジ□スタ(第1及び第2の読取回路
)、11及び12は第1及び第2の記憶比較回路、16
はアンド回路(出力回路)、17は判定回路を示す。The drawings show one embodiment of the present invention; FIGS. 1 and 2 are side views of the key in the front and layer states, respectively; FIG. 3 is a block diagram showing the electrical configuration of the electronic key device; Figure a7”7
to d and FIGS. 5a to 5d are through hole rows and waveform diagrams of various parts for explanation of operation. In the drawing, 1 is a key, 2 and 3 are first and second through hole rows (
4 and 6 and 5 and 7 are first and second light projecting elements and first and second light receiving elements (first and second detectors); 9 and 10 are the first
and a second shift register □ register (first and second reading circuits), 11 and 12 are first and second storage comparison circuits, 16
1 represents an AND circuit (output circuit), and 17 represents a determination circuit.
Claims (1)
パルス発生手段及び符号化された第2のパルス列を前記
第1のパルス列のパルス発生タイミングとはずれて発生
させるための第2のパルス発生手段を有しキー穴に対し
て挿脱されるキーと、前記第1及び第2のパルス発生手
段に夫々対応して設けられ前記キーのキー穴に対する挿
脱によりパルス列を発生する第1及び第2の検知器と、
これらの第1及び第2の検知器からのパルス列を夫々読
取る第1及び第2の読取回路と、前記第41及び第2の
パルス列に夫々対応する第1及び第2の設定符号化信号
が夫々記憶されこれらの設定符号化信号の内の選択され
た設定符号化信号と前記第1及び第2の読取回路の読取
信号とを夫々比較して両者が一致した時に一致信号を出
力する第1及び第2の記憶比較回路と、これらの第1及
び第2の記憶比較回路がともに一致信号を出力した時に
出力信号を出力する中力回路と、前記第1及び第2の検
知器のいずれが最初にパルスを出力するかを検出して前
記キー穴に挿脱されるキーの表裏及び挿脱を判定し表と
判定した時には前記第1の記憶比較回路に第1の設定符
号化信号を選択させるとともに前記第2の記憶比較回路
に第、2の設定符号化信号を選択させ裏と判定した時に
は前記第1及び第2の記憶回路に前記哀詩とは逆の設定
符号化信号を選択させキーの抜脱と判定した時には前記
出力回路を無効化する判定回路とを具備してなる電子キ
ー装置。A first pulse generating means for generating an encoded first pulse train, and a second pulse for generating an encoded second pulse train at a timing different from the pulse generation timing of the first pulse train. A key having a generating means and inserted into and removed from the key hole, and first and second pulse generating means provided corresponding to the first and second pulse generating means, respectively, and generating a pulse train when the key is inserted into and removed from the key hole. a second detector;
first and second reading circuits that read the pulse trains from the first and second detectors, respectively, and first and second setting encoded signals corresponding to the forty-first and second pulse trains, respectively; first and second reading circuits that respectively compare a selected setting coded signal among the stored setting coded signals and read signals of the first and second reading circuits, and output a match signal when the two match; A second memory comparison circuit, a neutral power circuit that outputs an output signal when both the first and second memory comparison circuits output matching signals, and which of the first and second detectors is selected first. detecting whether the key is inserted into or removed from the keyhole, and determining whether the key is inserted or removed from the keyhole, and when it is determined that the key is inserted or removed from the keyhole, causing the first memory comparison circuit to select a first setting encoded signal. At the same time, the second memory comparison circuit selects a second setting encoded signal, and when it is determined that the tail is the tail, the first and second memory circuits select a setting encoded signal opposite to the elegy. an electronic key device comprising a determination circuit that disables the output circuit when it is determined that the electronic key has been removed.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983197469U JPS60104552U (en) | 1983-12-22 | 1983-12-22 | electronic key device |
US06/881,582 US4691201A (en) | 1983-12-07 | 1986-07-02 | Encoded signal device with self-contained clock generation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983197469U JPS60104552U (en) | 1983-12-22 | 1983-12-22 | electronic key device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60104552U true JPS60104552U (en) | 1985-07-17 |
JPH0139343Y2 JPH0139343Y2 (en) | 1989-11-24 |
Family
ID=30755782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983197469U Granted JPS60104552U (en) | 1983-12-07 | 1983-12-22 | electronic key device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60104552U (en) |
-
1983
- 1983-12-22 JP JP1983197469U patent/JPS60104552U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0139343Y2 (en) | 1989-11-24 |
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