JPH0139343Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electronic key device for generating a coded pulse train by a key to cause a predetermined operation such as an unlocking operation to be performed.

[Purpose of invention]

The present invention can reliably read the encoded signal and output the output signal even if the key is inserted into the keyhole with either the front or the back side. An object of the present invention is to provide an electronic key device that can prevent the output of the electronic key.

[Summary of the idea]

The present invention provides a first pulse generating means for generating an encoded first pulse train, and a first pulse generating means for generating an encoded second pulse train at a timing different from the pulse generation timing of the first pulse train. The pulse generator has two pulse generating means, and is provided corresponding to a key that is inserted into and removed from the key hole, and the first and second pulse generating means respectively, and generates a pulse train when the key is inserted into and removed from the key hole. first and second detectors, first and second reading circuits that respectively read pulse trains from the first and second detectors, and first and second reading circuits that respectively read pulse trains from the first and second detectors; and a second setting coded signal are respectively stored, and a selected setting coded signal from these setting coded signals is compared with the read signals of the first and second reading circuits to determine whether they match. first and second memory comparison circuits that output a match signal when the first and second memory comparison circuits output a match signal; and an output circuit that outputs an output signal when both the first and second memory comparison circuits output a match signal.
Detecting which of the first and second detectors outputs a pulse first and determining whether the key inserted into or removed from the keyhole is front or back, or inserted or removed, and when it is determined that the key is front or back, the first memory is stored. The comparison circuit selects the first setting coded signal, and the second storage comparison circuit selects the second setting coded signal. When it is determined that it is tails, the first and second storage comparison circuits select the first setting coded signal. The present invention is characterized in that it includes a determination circuit that selects a setting encoded signal that is opposite to the time and disables the output circuit when it is determined that the key has been removed.

〔Example〕

An embodiment in which the present invention is applied to an automobile unlocking device will be described below with reference to the drawings.

First, in FIG. 1, reference numeral 1 denotes a key, in which a first row of through holes 2 as a first pulse generating means are formed on the same straight line along the longitudinal direction, and this first through hole row 2 is formed along the longitudinal direction. The second hole is located below hole row 2.
A second row of through holes 3 serving as pulse generating means are formed on the same straight line. In this case, the key 1 is set with a plurality of pulse generation timing positions Ta ₁ , Ta _{2 , ...Ta 8 along the longitudinal direction, and the first through-hole row 2 is set with pulse generation timing positions Ta 1 , Ta 2} , ... Ta ₈ along the longitudinal direction. It consists of circular holes 2 ₁ , 2 3 , 2 ₄ , 2 _{5 , 2 7 and 2 8 corresponding to Ta 1 , Ta 3 , Ta 4 , Ta 5 , Ta 7 and Ta 8 , and also} has a hole in the key 1. are the pulse generation timing positions Ta ₁ , Ta ₂ ,... along the longitudinal direction.
For example, a plurality of pulse generation timing positions Tb ₁ , Tb ₂ , ...Tb _{8 are set at a plurality of locations, for example, eight locations, shifted by the radius dimension of the through holes of the through hole row 2 with respect to Ta 8 ,}
The second row of holes 3 includes, for example, circular holes 3 ₁ , 3 ₂ , 3 ₄ , ₃ 5 , corresponding to the pulse generation timing positions Tb ₁ , Tb ₂ , Tb ₄ , Tb ₅ , Tb ₆ and Tb ₈ . 3 ₆ and 3 ₈
Consisting of That is, the pulse generation timing position Ta ₁
and Tb ₁ , Ta ₂ and Tb ₂ , Ta ₃ and Tb ₃ , Tb ₄ and Tb ₄ ,
Ta ₅ and Tb ₅ , Ta ₆ and Tb ₆ , Ta ₇ and Tb ₇ and Ta ₈
The setting is such that one of the through holes of the through hole rows 2 and 3 is present in either of Tb ₈ . 4 and 5
are a first light projecting element and a first light receiving element, 6 and 7, which are first detectors corresponding to the first through hole row 2;
are a second light emitting element and a second light receiving element which are second detectors corresponding to the second through hole row 3, and these are disposed near a keyhole in an automobile door (not shown). In this case, the second light receiving element 7 is located below the first light emitting element 4, and the second light emitting element 6 is located below the first light receiving element 5. The light projecting directions of the first light projecting element 4 and the second light projecting element 6 are set to be opposite to each other. And key 1 is the first
When inserted into the keyhole of the door in the open state as shown in the figure, the first light-receiving element 5 receives the first pulse train Pa encoded based on the first through-hole array 2 (see Figure 4).
(b)), and the second light-receiving element 7 generates a second pulse train encoded based on the second through-hole array 3.
Pb (see Figure 4(c)) is generated.

Now, the electrical configuration of the electronic key device will be described with reference to FIG. That is, the output terminal of the first light receiving element 5 is connected to the first input terminal of the OR circuit 7, and is also connected to the input terminal I of the first shift register 9, which is the first reading circuit. ,
The output terminal of the second light receiving element 7 is connected to the second input terminal of the OR circuit 8, and also to the input terminal I of the second shift register 10, which is the second reading circuit. The output terminal of the circuit 8 is connected to each clock input terminal CK of the shift registers 9 and 10. Furthermore, the 8-bit output terminal O of the first shift register 9
The 8-bit output terminal O of the second shift register 10 is connected to the 8-bit input terminal I of the second storage comparison circuit 12. In this case, the first
In the second storage comparison circuits 11 and 12, both an 8-bit signal "10111011" which is the first setting encoded signal and an 8-bit signal "11011101" which is the second setting encoded signal are stored in advance.
Then, the first memory comparison circuit 11 always
When the setting encoded signal is selected and the output signal of the first shift register 9 matches the first setting encoded signal, a high level table match signal Sa ₁ is output from the output terminal Oa. It has become
Further, when a high level signal is applied to the selection terminal S, the second setting encoded signal is selected, and when the output signal of the first shift register 9 matches the second setting encoded signal, the output terminal A high-level back match signal Sb ₁ is output from Ob. Furthermore, the second memory comparison circuit 12 always selects the second setting encoded signal, and when the output signal of the second shift register 10 matches the second setting encoded signal, the output terminal is A high-level table match signal Sa ₂ is output from Oa, and when a high-level signal is given to the selection terminal S, the first setting encoded signal is selected and the second shift signal is output. When the output signal of the register 10 matches the first setting encoded signal, a high-level back match signal _Sb2 is output from the output terminal Ob. In these first and second memory comparison circuits 11 and 12, each output terminal Oa is connected to the first and second input terminals of the AND circuit 13, and each output terminal Ob is connected to the first input terminal of the AND circuit 14. and a second input terminal. Further, each output terminal of the AND circuits 13 and 14 is connected to the first and second input terminals of an OR circuit 15, and the output terminal of the OR circuit 15 is connected to the first input terminal of an AND circuit 16, which is an output circuit. has been done. 17 is a determination circuit that operates as described later, and its input terminal
Ia and Ib are connected to the output terminals of the light receiving elements 5 and 7, respectively, the output terminal Oa is connected to each selection terminal S of the first and second memory comparison circuits 11 and 12, and the output terminal Ob is connected to the AND circuit 16. is connected to the second input terminal of.

Next, the operation of this embodiment will be explained with reference to FIGS. 4 and 5.

When the key 1 is inserted into the keyhole of a car door with the key 1 facing up _as shown in FIG.
₃ , 2 ₄ , 2 ₅ , 2 ₇ and 2 ₈ , the pulses Pa ₁ , Pa ₃ , Pa ₄ , Pa ₅ , Pa ₇ and
The second light-receiving element 7 generates an encoded first pulse train Pa consisting of Pa ₈ , and the second light-receiving element 7 connects the through-holes 3 ₁ , 3 ₂ , 3 of the second through-hole array 3 as shown in FIG. 4a. ₄ , 3 ₅ , 3 ₆
and pulse as shown in Figure 4c based on ₃₈
A second encoded pulse train Pb consisting of Pb ₁ , Pb ₂ , Pb ₄ , Pb ₅ , Pb ₆ and Pb ₈ is generated. In this case, the first and second pulse generation timings of the first pulse train Pa and the second pulse train Pb are at pulse generation timing positions Ta ₁ , Ta ₂ , . . .
The pulse width is shifted by half of the pulse width based on Ta ₈ and Tb ₁ , Tb ₂ , and Tb ₈ , and a pulse is generated in one or both of the pulse trains Pa and Pb at each of the first and second pulse generation timings. It is something. Therefore, when these pulse trains Pa and Pb are applied to the OR circuit 8, the OR circuit 8 generates an OR signal corresponding to both the first and second pulse generation timings as shown in FIG. 4d. synchronization signals (synchronization pulses) Pc ₁ , Pc ₂ , ... Pc ₈ are generated, and these are used in shift registers 9 and 1.
0 to each clock input terminal CK. 1st
The shift register 9 receives synchronizing signals Pc ₁ , Pc ₂ ,...Pc ₈
The pulse train Pa given to the input terminal I based on
The presence or absence of pulses is sequentially written and stored as logic signals "1" and "0", and similarly, the second shift register 10 is supplied to the input terminal I based on synchronization signals Pc ₁ , Pc ₂ , ...Pc ₈ The presence or absence of pulses in the pulse train Pb is sequentially written and stored as logic signals "1" and "0", and as a result, the output signal, which is the stored content (read signal) of the first shift register 9, becomes an 8-bit signal "10111011". ”, and the output signal, which is the stored content (read signal) of the second shift register 10, becomes an 8-bit signal “11011101”. On the other hand, key 1
_is inserted into the keyhole in the open state shown in _FIG . , From this, the determination circuit 17 determines that the key 1 is the front, and sets the output signal of the output terminal Oa to a low level, and also determines that the key 1 is inserted, and sets the output signal of the output terminal Ob to a high level. shall be. Then, since the output signal of the output terminal Oa of this determination circuit 17 is at a low level, the first setting encoded signal is selected in the first storage comparison circuit 11,
The second storage comparison circuit 12 selects the second setting encoded signal. Further, since the output signals of the shift registers 9 and 10 are applied to the input terminals I of the memory comparison circuits 11 and 12, respectively, the first memory comparison circuit 11 receives the output signal of the second shift register 9 from the first setting. Since it matches the 8-bit signal "10111011" which is the encoded signal, the output terminal Oa
Since the output signal of the second shift register 10 matches the 8-bit signal "11011101" which is the second setting encoded signal, the second storage comparison circuit 12 outputs the table match signal Sa ₁ . Output terminal Oa
The table match signal Sa ₂ is now output. Since these table match signals Sa ₁ and Sa ₂ are given to the AND circuit 13, the AND circuit 13
will now output a high level output signal,
This high level output signal is applied to the first input terminal of the AND circuit 16 via the OR circuit 15. At this time, the second input terminal of the AND circuit 16 is supplied with the high-level output signal from the output terminal Oa of the determination circuit 17, so the AND circuit 16 receives the unlock signal, which is the high-level output signal. Sc is output and applied to an unlocking mechanism (not shown), which unlocks the door by energizing an electromagnetic solenoid that is the operating source. Thereafter, when the key 1 is removed from the keyhole of the door, the second light receiving element 7 first outputs a pulse Pb ₈ based on the through holes 3 ₈ of the second through hole row 3. From this, the judgment circuit 1
7 is the second light receiving element 7 when the key 1 is in the front state.
determines that the pulse Pb ₈ is first output when the key 1 is removed and removed, and sets the output signal of the output terminal Ob to a low level. Therefore, even if the temporary order memory comparison circuits 11 and 12 output table matching signals Sa ₁ and Sa ₂ when the key 1 is removed, the AND circuit 1
Since the second input terminal of 6 is at a low level, the AND circuit 16 is disabled and does not output the unlocking signal Sc.

Now, move key 1 up and down from the state shown in Figure 1.
In the case of the reverse side as shown in FIG. 2, which is reversed by 180 degrees, the first row of through holes 2 is on the lower side and the second row of through holes 3 is on the upper side. Therefore, when the key 1 is inserted into the keyhole of a car door in this reversed state, the second light receiving element 7 will be inserted into the through holes 2 ₁ , 2 ₃ , 2 of the first through hole row 2 as shown in FIG. 5a. Based on 2 ₄ , 2 ₅ , 2 ₇ and 2 ₈ , the pulses Pa ₁ , Pa ₃ , Pa ₄ , Pa ₅ ,
A coded first pulse train Pa consisting of Pa ₇ and Pa ₈ is generated, and the first light receiving element 5 is connected to the through holes 3 _{1 and} 3 of the second through hole array 3 as shown in FIG. 5a. _2,3
A coded second pulse train Pb consisting of pulses Pb ₁ , _{Pb 2} , Pb _{4 , Pb 5} , Pb ₆ and Pb ₈ as shown in FIG _. will occur. When these pulse trains Pa and Pb are applied to the OR circuit 8, the OR circuit 8 generates synchronization signals (synchronization pulses) Pc ₁ , Pc 2 , Pc 2 , Pc ₂ ,
. . . Pc ₈ is generated, and these are applied to each clock input terminal CK of shift registers 9 and 10. The first shift register 9 receives a synchronization signal
Based on Pc ₁ , Pc ₂ , ...Pc _{8 ,} the presence or absence of pulses in the pulse train Pb applied to the input terminal I is sequentially written and stored as logic signals "1" and "0", and similarly,
The second shift register 10 receives synchronization signals Pc ₁ , Pc ₂ ,
...Based on Pc ₈ , the presence or absence of pulses in the pulse train Pa applied to the input terminal I is sequentially written and stored as logic signals "1" and "0", and as a result, the memory content of the first shift register 9 becomes The output signal is an 8-bit signal "11011101", and the output signal which is the memory content of the second shift register 10 is 8 bits.
The bit signal becomes "10111011". On the other hand, when the key 1 is inserted into the keyhole in the reverse _position shown in FIG _. Therefore, the determination circuit 17 determines that the key 1 is on the back side and sets the output signal of the output terminal Oa to high level, and also determines that the key 1 is inserted and sets the output signal of the output terminal Ob to the high level. Set the output signal to high level. and,
Since the output signal of the output terminal Oa of the determination circuit 17 is at a high level, the second setting encoded signal is selected in the first memory comparison circuit 11, and the second setting encoded signal is selected.
In the storage comparison circuit 12, the first setting encoded signal is selected. Furthermore, the output signals of these shift registers 9 and 10 are sent to storage comparison circuits 11 and 12.
Since the output signal of the first shift register 9 matches the 8-bit signal "11011101" which is the second setting encoded signal, the first memory comparison circuit 11 outputs Terminal Ob
Since the output signal of the second shift register ₁₀ matches the 8-bit signal "10111011" which is the first setting encoded signal, the second memory comparison circuit 12 outputs the back matching signal Sb 1. Output terminal Ob
The back matching signal Sb ₂ is now output. These back match signals Sb ₁ and Sb ₂ are given to the AND circuit 13, so the AND circuit 13
will now output a high level output signal,
This high level output signal is applied to the first input terminal of the AND circuit 16 via the OR circuit 15. At this time, the second input terminal of the AND circuit 16 is given a high-level output signal from the output terminal Oa of the determination circuit 17, so the AND circuit 16 receives the unlocking signal, which is a high-level output signal.
Sc is output and applied to an unlocking mechanism (not shown), which unlocks the door by energizing an electromagnetic solenoid that is the operating source. Thereafter, when the key 1 is removed from the keyhole of the door, the first light receiving element 5 is first
The pulse Pb ₈ is now output based on the through hole 3 ₈ of the through hole row 3, and from this, the determination circuit 17
determines that the first light-receiving element 5 first outputs the pulse Pb ₈ when the key 1 is in the reverse position and the key 1 is removed, and sets the output signal of the output terminal Ob to a low level. Therefore, as the key 1 is removed and removed, the temporary memory comparison circuits 11 and 12 output the back matching signal.
Even if Sb ₁ and Sb ₂ are output, AND circuit 1
Since the second input terminal of 6 is at a low level, the AND circuit 16 is disabled and does not output the unlocking signal Sc.

According to this embodiment, the following effects can be obtained. That is, the radial dimension of the through-hole is determined based on the second through-hole sequence 3 for the encoded first pulse train Pa generated at the first pulse generation timing based on the first through-hole sequence 2 of the key 1. The encoded second pulse train Pb is generated at the second pulse generation timing shifted by a minute (half the pulse width), and the first pulse Pa 1 is the first pulse train Pb in the first pulse train Pa and the second pulse train _Pb. and Pb ₁ and the final pulses Pa ₈ and Pb ₈ are made sure to be generated, so that when the key 1 is inserted into the key hole, which of the first and second light receiving elements 5 and 7 is connected to the first through hole. It is possible to determine whether the key 1 is front or back depending on whether the pulse Pa ₁ is first generated based on the through hole 2 ₁ of the row 2, and the first light receiving element 5 generates the first pulse train Pa. In addition, when the second light receiving element 7 is in the front state of the key 1 in which the second pulse train Pb is generated, the determination circuit 17 causes the first memory comparison circuit 11 to select the first setting encoded signal, and the second light receiving element 7 generates the second pulse train Pb. The memory comparison circuit 12 selects the second setting encoded signal, the first light receiving element 5 generates the second pulse train Pb, and the second light receiving element 7 generates the first pulse train.
When the key 1 is in the reverse state generating Pa, the determination circuit 17 causes the first memory comparison circuit 11 to select the second setting encoded signal, and also causes the second memory comparison circuit 12 to select the first setting encoded signal. The signal can be selected, and therefore, even if the key 1 is inserted into the keyhole with either the front or back side, the encoded signal can be reliably read and the unlocking signal Sc, which is the output signal, can be output. . Furthermore, as mentioned above, the first
Since the final pulses Pa ₈ and Pb ₈ are always generated in the pulse train Pa and the second pulse train Pb, in addition to determining whether the key 1 is front or back, the first light receiving element 5 and the second light receiving element It is now possible to determine whether the key 1 is removed from the keyhole depending on which of the keys 7 generates the pulse Pa ₈ first, and when determining whether the key 1 is removed, the AND circuit 16 is disabled by the judgment circuit 17. As a result, even if the memory comparison circuits 11 and 12 output the coincidence signals Sa ₁ and Sa ₂ or Sb ₁ and Sb ₂ when the temporary key 1 is removed or removed, the unlock signal Sc is output by mistake. Therefore, the door unlocking mechanism is not operated unnecessarily. Also, the first pulse train
Since the synchronizing signals Pc ₁ , Pc ₂ , ... Pc ₈ can be obtained by the OR signal of Pa and the second pulse train Pb, there is no need to specially form a through hole row for generating the synchronizing signal in the key 1, for example. , which is advantageous in manufacturing the key 1. Moreover, since the light emitting directions of the first light emitting element 4 and the second light emitting element 6 are reversed, the light receiving elements 5 and 7 receive light only from the corresponding light emitting elements 4 and 6. The light receiving elements 5 and 7 will not malfunction since they will receive the projected light.

In the above embodiment, the key 1 is formed with the first and second through hole arrays 2 and 3 as the first and second pulse generating means, but instead, for example, the first and second magnetic force generating means are formed. In place of the light emitting elements 4, 6 and the light receiving elements 5, 7, first and second Hall elements or reed switches may be provided as first and second detectors.

In addition, the present invention is not limited to the embodiments described above and shown in the drawings, but can be modified as appropriate without departing from the gist, such as being applicable not only to automobile unlocking devices but also to electronic key devices in general. Of course, it can be implemented as follows.

[Effect of idea]

As explained above, the electronic key device of the present invention has the following features:
Even if the key is inserted into the keyhole with either the front or back side, the encoded signal from the first and second pulse generating means provided on the key can be reliably read and an output signal can be output. This has the practical effect of preventing erroneous output signals from being output when the key is removed from the key.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIGS. 1 and 2 are side views of the front and back states of the key, respectively. FIG. 3 is a block diagram showing the electrical configuration of the electronic key device, and FIG. Figures a to d and Figures 5 a to d are through hole rows and waveform diagrams of various parts for explaining the operation. In the drawing, 1 is a key, 2 and 3 are first and second through hole rows (first and second pulse generating means), 4 and 6, 5 and 7 are first and second light projecting elements, and First and second light receiving elements (first and second detectors), 9 and 10 are first and second shift registers (first and second reading circuits), 11 and 12
16 represents the first and second storage comparison circuits, 16 represents an AND circuit (output circuit), and 17 represents a determination circuit.

Claims (1)

[Scope of utility model registration request] A first pulse generating means for generating an encoded first pulse train, and a second pulse generating means for generating an encoded second pulse train at a timing different from the pulse generation timing of the first pulse train. a key that is inserted into and removed from the keyhole; and first and second pulse generation means that are provided corresponding to the first and second pulse generation means and generate a pulse train when the key is inserted into and removed from the keyhole. 2 detectors, first and second reading circuits that read pulse trains from the first and second detectors, respectively, and first and second reading circuits that respectively correspond to the first and second pulse trains. Setting coded signals are stored respectively, and a selected setting coded signal from these setting coded signals is compared with the read signals of the first and second reading circuits, and when the two match, a match signal is generated. an output circuit that outputs an output signal when both the first and second memory comparison circuits output a match signal;
and a second detector which outputs a pulse first and determines whether the key inserted into or removed from the keyhole is front or back, and if it is inserted or removed.When it is determined that the key is front or back, the first memory comparison circuit The first setting coded signal is selected, and the second storage comparison circuit selects the second setting coded signal, and when it is determined that it is tails, the first and second storage comparison circuits are instructed to select the second setting coded signal. An electronic key device comprising a determination circuit that selects a reverse setting encoded signal and disables the output circuit when it is determined that the key has been removed.