JPS60103632A - Method of separating performance problems of cmos lsi and vlsi having internal delay testing function - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to large scale integrated (LSI) circuit chips and very large scale integrated (VLSI) circuit chips, and more particularly to LSI and VLSI circuit chips using complementary metal oxide semiconductor (CMO8) logic circuits. related to.

More particularly, the present invention relates to CMO8LSI and VLSI circuit chips that include a particular set of composite test circuits, which, in addition to being used to functionally test the chips, also test integrated circuit packages. It is used to test the electrical delay of circuits on a chip before implementation.

Integrated circuit chips are formed on wafers. The wafer is a thin piece of pure silicon, typically ≠ inches in diameter for LSI and VLSI circuits, on which an array of chips is fabricated. The wafer is scribed along the unused channels between the chips and the chips are cut from the wafer. These chips are then mounted into integrated circuit packages for testing and, if successful, used.

The percentage of properly working chips on a wafer, or yield, is often very low.

In the manufacturing method of LSI and VLSI, the manufacturing process is complicated, so the yield is about 10%. Since chip packaging requires significant manufacturing costs, it is desirable to thoroughly test the chips before they are separated from the wafer to avoid packaging defective chips.

There are typically three types of tests required to adequately test an integrated circuit: (1) functional tests to show that all circuits operate as required; (2) parametric tests to show that the chip's input/output circuits have the correct electrical characteristics; and (3) tests to ensure that the circuits are running at the required speed. Delay test to show if it works.

The present invention provides a simple way to perform the third test when the CMO8LSI or VLSI chips are still part 7 of the wafer.

CMO8LSI or VLSI Chizzo chip testing has not been possible until now for the reasons described below.

However, a review of the development of delay testing as it relates to non-LSI or non-VLSI integrated circuit technology is useful in understanding the advantages of the present invention.

When the test chip is part 7 of a wafer, this requires a way to apply a signal to the input/output (factor/10) node of the chip and read the signal from it. Many probe mechanisms have been developed to meet this need. The probe is a mechanical arm that is electrically conductive and has a micropoint at its/end that makes electrical contact with the I10 pad, and the other end is wired to the tester's electronics. Probe systems have been manufactured that have the same number of probes as there are I-off heads of the chip under test. The contact end of the probe is arranged in the same pattern as the Ilo-9 so that when the tip is placed under the probe, the electrical signal from the tester lowers the Zolobe point and brings it into contact with the Ilo-9 hat.

When contact has been made with all Ilo nodes and test patterns can be applied to the input pads, clock signals are generated by the tester and sent to the appropriate input pads, as required. The response of the circuit on the chip to the input signal can then be read by the tester through a probe connected to the output pad. The tester can compare the output pattern read from the chip to the expected pattern based on the input pattern and determine whether the chip is functioning properly. Therefore, the probe system still satisfies the functional testing requirements of the test chip, which is part 7 of the wafer.

Probe systems are also used for delay measurements by using specific test chips. These test chips are placed at specific locations within the array of desired functional chips, thereby utilizing headspace on the wafer that could otherwise be used for additional functional chips. The test chip has a small number of I10 pads, and delay testing is performed using a probe mechanism that is different from the probe mechanism used for functional testing of other chips. Due to the small number of I-off nodes on the test chip, the probe arm on the delay tester can be made very small. Therefore, the inductance of the probe arm does not adversely affect the results of the delay experiment. Since each test chip replaces a potentially available functional chip, only a small number of test chips are used on each wafer.

Result of delay test on test chip (this result is 2 f l
) can be used to remove intact wafers. However, even if the delay test results do not exclude the wafer, all functional chips that pass the functional test must still be delayed tested after being separately implemented, as explained below. As it progresses,
The use of these test chips has become impractical.

In the early 7970s, the wafer diameter was typically 2 inches;
The line width (minimum dimension) on the chip was typically 7μ.

The size of the mask (a different mask is required for each step of the wafer fabrication process) is typically /:/, which was used to expose the resist on the wafer using a contact process. The original design was done using manual or automated methods and was much larger than the actual thickness, such as ioo:i to soo:i. This was reduced to a reticle with a typical size of 10:/ by a photo reduction method. This reticle was then applied to a step-and-beat camera that would reduce the size of /:/ by exposing its turns on a mask. The power mask position where the test chip pattern is given was skipped. When all of the chip pattern was exposed on the mask, the test chip reticle was placed into a step-and-heat camera, which exposed the test chip pattern in a blank position.

Until the mid-70's, wafers typically had a diameter of 3 inches and line widths on the chips were typically ≠ microns. A mask with a size of /:/ was made together with the test chip using an electron beam method, and was exposed onto a wafer using a projection adjustment method.

Until 2010, the diameter of the wafer was typically 1.5 inches, and the line width on the chip was typically J microns.

The projection adjustment method no longer satisfied the required accuracy. Due to the small dimensions used, the reticle was made using an electron beam method with a size of 10:/. No mask was used; rather, the reticle was exposed onto the wafer resist using a direct step-on-wafer (DSW) approach. Since the DSW method has extremely delicate tolerances during exposure, it is not possible to replace the chip reticle with a test chip reticle. Test chips were therefore no longer in practical use until the advent of VLSI technology.

Delay tests for normal chips in LSI and VLSI have not been practically used until now mainly for the following two reasons. That is, (1) the delay time of the circuit has been reduced. (2) As LSI and VLSI technology advances, the number of Ilo nodes has increased.

A reduction in circuit delay time means that the time between application of the input pulse and detection of the output pulse is smaller, and therefore the time measurements must be more accurate if the measurement results are to be meaningful. .

As the circuit density and number of chips increased, the size of the chip did not increase at the same rate. In fact, as the number of I10 pads on a chip increased, the pads had to become smaller and closer together.

The end face of the glove arm wired to the tester is thicker than the contact end face. Thus, the rows of globe arms along each side of the chip form a "fan" that is narrower at the Zolob end face and wider (9) at the end face wired to the tester. Chips with Ilo ze wood and globe arms along each side are usually square, so ■/Q
As the number of teds increases, the length of the probe arm must increase because the "fan" becomes wider at the tester end of the globe arm. This increase in probe length adds significant inductance to test circuits used in delay tests.

As discussed above, the reduction in circuit delay time inherent in LSI and VLSI technology requires more accurate measurements when performing delay testing. This means that the rise and fall times of the generated and measured signals must be small compared to the measured delay times. Furthermore, the switching point of the output signal relative to the input signal switching point must be measured more accurately. However, longer probe inductance distorts the signal used for delay testing or increases fast rise or fall times. Therefore, even if the delay time can be measured, the switching times (10) of the first input circuit and the last output circuit cannot be determined accurately enough to give satisfactory results. Therefore, although LSI and VLSI chips are functionally tested while still on the wafer, accurate delay testing must still be performed after the chips are mounted in an integrated circuit package.

The present invention seeks to solve the problem of how to delay test CMO8LSI and VLSI chips when they are still part 7 of a wafer. This avoids the problem of chip implementations that cannot meet delay requirements. The present invention attempts to solve the above-mentioned problems by utilizing the following advantages of the CMO8 technology.

Although CMO8LSI and VLSI circuit technologies have sufficient tolerance for manufacturing process variations, they inherently cannot provide sufficient tolerance for process defects. Due to the fine geometry, defects such as poor line resolution or masks with pinholes in the lenost usually result in significant damage. That is, circuits manufactured with defects do not perform their function and are detected by functional testing while the chip is still part of the wafer. Process variations in doping levels, temperatures, diffusion times, etc. typically result in circuits that function but are too slow to achieve satisfactory results.

Functional testing, which is a steady-state test, typically does not detect delayed defects caused by process variations.

Another characteristic of CMO8LSI and VLSI circuit technology is that if process variations degrade the delay characteristics of a circuit, the entire single chip on the wafer will also degrade, and all circuits will degrade in approximately the same way. Therefore, CMO8T,
If a single meaningful delay measurement can be made for an SI or VLS I chip while it is still part 7 of the wafer, a reliable determination of the delay of all circuits on that chip can be made. The present invention makes such delayed testing possible.

The current object of the present invention is to develop a CMO8LSI or VLSI which has an essential test circuit consisting of a shift register on the periphery of the chip.
This is achieved by using I integrated circuits.

The shift register has stages, or storage locations, that physically correspond to each of the I10 pads of the chip.

Shift registers are commonly used by testers to functionally test chips. This test method is 72g/year/
, Patent Application No. 33.2, dated February 27th. It is stated in 6.

Additional circuitry is used to invert and gate the signal from the tester to the shift register/times. All stages of the shift register are open, so the signal passes through the shift register,
Appears in the output. When a shift register is used in this way, it is called a ring oscillator. Each stage of the ring oscillator inverts the signal multiple times, so that because of the single inversion of the additional circuitry described above, the signal appearing at the output is an inversion of the one originally sent out by the tester. Additional circuitry darts this output signal into an inverter to circulate through the detection tester and again through the ring oscillator. The elapsed time of a signal through all stages of the ring oscillator provides a measure of the delay time of the circuit on the chip.

The present invention will be explained in detail below. The description is intended to explain the general principles of the invention, but is not intended to limit the invention. The invention is best defined by the appended claims.

As can be seen from FIG.
7 parts of an integrated circuit 70 including:

The integrated circuit of this example uses CMO8LSI and has a 1.2J-
, has 4 ■Okinogurado/4'. DI, A, B,
7 I/Q i4 labeled C, D, E and Do
, y/lI- are connected to the input/output control and clock control circuit/g of the tester. a shift register with a stage connected to each rad / one (with the exception of the f rad used for the test hood and ground and power connections mentioned above);
0 is formed around the chip 10. Shift registers are commonly used to functionally test chips as described in patent application Ser. However, in the present invention, the shift register is used as a ring oscillator when measuring delay time. All these operations are controlled by the input/output control and clock control circuits.

(/≠) Figures 2 and 3 show the shift register stages and 110 circuits for each i9 node, respectively. FIG. 2 shows the shift register stage as it relates to the input pad, and FIG. 3 shows the configuration as the shift register stage relates to the output pad. Each shift register stage has ≠ invert tags ≠−! It has 0 and 6 transfer ports T/~TB.

In this embodiment, the shift register is used as a ring oscillator. In this embodiment, the transfer gate T/
, T3 and TJ- are turned on by a control signal.

This allows a signal to be input to the first stage of the ring oscillator and transferred to the output of the final stage. Each stage has two inverters, so the output of the ring oscillator has the same polarity as the input. The signal undergoes five circuit delays at each stage of the ring oscillator. That is, each of the three transfer darts and two inverters suffers a circuit delay.

As shown in the figure, the clock signals A, B, C
.

The D and E input pads are each connected to an input buffer horn that protects and buffers the input signal and its complementary output signal. FIG. 5 shows seven circuits of the input buffer. Input protection is provided by resistor l4 and diodes jg and j. Complementary signals are provided by inverters j, 2 and 5'≠. The figure shows the input buffer used for signal A. Other truly high-order logic signals! An equivalent circuit is used for the signal. The input buffers used with the two true low signals and EK as the logic signals are equivalent except that the polarity of the output signal is reversed. Figure 4 shows NAND gate Otsu 0-71 and inverter 10-
A clock decoding circuit consisting of 10 circuits is shown. This circuit decodes complementary clock signals from input buffers AE and outputs signals AE, BE, CF.

Generate DE, R and their complements.

In the following description, an asterisk, *, is used to indicate a logic signal that is true when the voltage level is low. For example, signal R is true when high, and signal R* is true when low. The asterisk used has the same meaning as the par on the signal name in the circuit diagram.

Many signal names are combinations of individual signal names, so for example, signal AE! Since it is the result of the AND of signals A and E, it is marked in parentheses with an asterisk to avoid ambiguity. is sometimes used. Therefore, (
AE)” is a signal A that is true when both A and E are low.
E, while (A, ) AE means a signal that is true when A is low and E is high.

As shown in FIG. 7, the output buffer //B is the inverter //ll- and the AND-OR-INVERT gate //
It is driven by ke”-)//, 2 is DOI and D
Select one of the OEs as input. DOI is the data output signal from the internal shift register of chip 10 made as part 7 of internal circuit/2. DOE is the data output signal from external shift register 20. Transfer gates T3 and T+ and two inverters 70g and /10 are the final stage slave latch of the external shift register.

In this example, this is the output of the ring oscillator. When E is true, DOE is selected for the output buffer; when E is false, DOI is selected. AND-OR-INVE
The output of RT gate //,2, SO (shift out), is inverted by invert(/7) ri//≠ and goes to the output buffer and input selection circuit. AND-OR-INVERT) /
20 is used to select either ``(DI)'' or SO. (DI)* is the data input signal from the tester, and SO is the data output signal from the output selection circuit. K"-) T/and T2 and inverter/2. :2 and /λhiro are first-stage mask latches of the external shift register.

When the signal R is true, SO is selected as an input, and when R is false, (DI) is selected. The three-man NAND gate 7g and the inverter tag O shown in FIG. R is true whenever A, B, and C are true.

A timing diagram is shown in Fig. g. At time t/, the tester raises input signals A, B and E. The clock decoding circuit of FIG. 4 receives the signal A from the input buffer shown in FIG.
- decode E and their complements and three high-order signals AE
, BE and DE and generate a low signal CE. These j
The two signals shown in FIGS. 2 and 3 are transfer groups) T/, T
Turn on J and Tj (/J?) and turn off transfer darts T, 2 and T4/. This is AND-OR-IN~'ERT dirt/20
allows the signal at the output of (shown in FIG. 7) to pass through the ring oscillator. Since signal C is low level, 3
The human-powered NAND gate 7g (Figure 6) sets R* to a high level,
(DI)* is selected as the input to the ring oscillator.

AND-OR-INVERT RI-) / 20 The inverted signal (DI)* passes through the ring oscillator until it appears at the final stage as DOE. Since signal E is high, the output circuit shown in FIG. 7 passes DOE to the tester as signal SO. The tester raises signal C after detecting the arrival of SO. This is shown at time t2 in Figure g. Before time t/and after time t,2, the data input signal DI is shown in a cross-hatched pattern, indicating a state in which no attention is required for the signal.

When signal C goes high, the three-man NAND gate shown in Figure 4
7g makes the signal R high and R1+' low. The AND-OR-INVERT gate then selects the signal SO instead of (DI)* as the input to the ring oscillator. Signals AE, BE, CE and DE are unaffected by signal C going high, so transfer signals T/, Tj and Tj remain on and T2 and Tll remain off. SO is the inverse of (DI), so (AN
The ring oscillator produces a square wave when the output signal SO (inverted by D-OR-INVERT +"-t/, 20) is inverted before being applied to the input again. The period of the square wave is The tester detects each change in the signal SO through the output circuit shown in Figure 7b and calculates the average circuit delay time for all of the circuits included in the ring oscillator. Use the measured times to determine: The ring oscillator oscillates until the tester changes the timing signals A, B, C, and D.

A ring oscillator generates a square wave that the tester uses to measure its delay time. If the chip has 2J-6 Ilo/Grads, the ring oscillator and additional circuits are more than 7250 times the individual circuit delay times (2 inverters and 3 transfer boxes, each with 7250 shift registers) This means that each stage has a delay time of 7 circuits. As mentioned above, since process variations in CMO8 technology affect all circuits on the chip equally, the ring oscillator will increase the delay time difference between the circuits by a factor of 7.230 or more, thus making the measurements even more difficult. becomes easier. The rising and falling parts of the square wave output of the ring oscillator are degraded by the inductance of the probe, and therefore the square wave becomes trapezoidal due to the ringing superimposed thereon. However, since the waveform is repetitive, it is only necessary to trigger a counter at an arbitrary level in the rising and falling portions of the waveform to determine the time width of the waveform.

Since the signal is inverted when passed through the ring oscillator, the total delay time through the ring oscillator and additional circuitry is half the waveform period.

When CMO8LSI and VLSI chips are part of a wafer, a ring oscillator solves the problem of testing the delay of these chips. Since the CMO8 circuit consumes almost no power when using direct current, the ring oscillator does not dissipate power in the chip as long as the chip is used normally.

The ring oscillator can also be used at any package level, i.e. integrated circuit/package level, printed wiring board level,
Alternatively, it can also be used for delay testing at the system level. CMO8 circuits are very sensitive to increases in voltage and temperature. That is, as the supply voltage decreases or the ambient temperature increases, the circuit delay time of the CMO 8 increases. Ring oscillators can be used at the package level to detect bad wire bonds that result in increased chip temperature, or at the printed wiring board level to detect cold solder joints on power bins that bring the chip to low voltage. Ring oscillators can also be used at the system level to find hot spots caused by poor design or filters, or to check for low voltage occurrences caused by poor design, poor wiring, low supply power, etc. A record of the original delay time measured for the chip can be maintained, and changes in newly measured values can be used to isolate problems.

(22)

[Brief explanation of the drawing]

FIG. 1 is a schematic top plan view of a chip of the invention. FIG. 2 is a schematic diagram of providing complementary inputs to the input pads and associated latches. FIG. 5 is a schematic diagram of the input buffer circuit of FIG. FIG. 3 is a schematic diagram of a clock control circuit used to generate timing signals to control chip testing. FIG. 7 is a schematic diagram of the output and input circuitry of the test portion of the chip. FIG. g is a timing diagram showing various operations of the ring oscillator. 10... integrated circuit, /, 2... internal circuit, /4l-
-I10 Nogurado, / Otsu... I10 Driver) / I.
・・Tester input/output control and clock control circuit, 2o・
...Shift register, ≠o, 4+! -2. ≠G~SO,
Sノ, j≠. and θ~10 Otsu, 10g, /10, //≠, /ノ!
. 7.2≠...inverter, T/~T7...transfer port) AE, BE, DE...higher level signal, CF
...Low level signal, AE. BE, DE...Complementary signal of AE, BE, DE, A-E
... Clock signal, A-E... Signal complementary to A-E, j B... Resistor, j, 3-9... Diode, B. ~7g...NANDkey-) DOI-, DO
E...data output signal, //B...output buffer device)
77g...Input buffer, / / j, / j O
・A, ND-OR-INVERT r −). Name of agent: Kawahara 1) - Hari procedure - TC city official document (method) 3. Relationship with the case of the person making the amendment Name of patent applicant Name Storage Technology Partners 4
6. Agent 5. Date of amendment order. 6. Number of inventions increased by amendment.

Claims (1)

Claims: (1) Isolating the performance issues of an 0MO8LSI or VLSI integrated circuit chip at a desired packaging level, including the printed wiring board and system levels, said chip having a shift register circuit thereon; The shift register circuit is selectively connected in accordance with a control signal as a ring oscillator with an oscillation period approximately twice the transfer delay time of the signal passing through it, (,) before mounting the chip at a desired package level. (b) measuring and recording the oscillation period associated with the pre-ring oscillator on the hindlimb tip with the tip at the desired 24 cage level; (c) ) Stellar 7' measurement to separate meaningful differences between the two measurements in step (a) and step (b).
A method for separating 0MO8LSI and VLSILSI Tyranno problems with an internal delay test function, comprising the steps of: comparing measurements of and indicating the differences indicate performance problems of the system. (2) The difference between the two measurements in step (c) is used to isolate multiple problems, and the problems are: (1) Improper bonding increases chip temperature; (11) Improper electrical contact will reduce the voltage applied to the chip, such as cold contact with the power pins of the package in which the chip is housed, or with the power pins of the wiring board to which the package is attached. (iii) localized heating within the chip or in the system in which the chip is used where the localized heating is caused by improper design or improper wiring; Range 1
A method for isolating performance problems of 0MO8LSI and VLSI chips with internal delay test function as described in .