JPS60103560A - Digital signal recorder - Google Patents

Abstract

PURPOSE:To obtain a reproducing data with fidelity by writing an input digital signal to a buffer memory by an external clock signal synchronizing with the input signal, reading the result with a system clock signal, supplying the read signal to a recording processor, and recording its output to a recording medium. CONSTITUTION:The external clock CKW is fed to an A/D converter 1, a digital data is inputted from the A/D converter 1 to a buffer memory 2, the data is read from the buffer memory 2 by using a system clock CKS from a clock generating circuit 3 at the inside of a data recorder and fed to a redundancy code generating circuit 4. The output data of the redundancy code generaring circuit 4 is fed to an encoder 6, the channel encoding of recording data and insertion of a block synchronizing signal are performed and the recording data divided into four channels are extracted. The output of each channel of the encoder 6 is fed to rotary heads 8A-8D via recording amplifiers 7A-7D and a rotary transformer (not shown) and recorded on a magnetic tape 9.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a digital signal recording apparatus applicable, for example, to recording digital data on a magnetic tape using a rotary head.

"Background technology and its problems" A conventional analog data recorder has a configuration in which an analog input signal is )/M modulated and recorded on a magnetic tape by a magnetic head, and the signal reproduced from the magnetic tape is FM demodulated. I was in Togi-n. Therefore, due to uneven running speed of the magnetic tape.

■'T! The disadvantage was that the signal contained in the '2n signal contained a time axis fluctuation component.

In a digital tape recorder that records all digital audio signals or digital video signals, A/D conversion and necessary signal processing on the recording side are performed using an internal system clock, and on the playback side.

By writing the reproduced data into memory and reading the reproduced data using the system clock, time axis fluctuations are removed.
Furthermore, by the system clock.

Yes, it is configured to perform conversion. Mo1 like this
Although it is possible to eliminate time axis fluctuations due to unevenness in the running speed of the magnetic tape by using the Q configuration, there is a problem in that the influence of drift due to temperature of the system clock cannot be avoided. Furthermore, in the case of a data recorder, it is necessary to record digitized data at an arbitrary sampling frequency.

As mentioned above, a system configuration in which the sampling frequency is fixed to a specific value is not suitable for a data recorder.

``Purpose of the Invention'' Therefore, the purpose of this shadow generation is to avoid the influence of uneven tape running speed, as well as the influence of drift due to temperature and other factors such as system clock failure of the device, and to maintain the same quality as during recording. An object of the present invention is to provide a digital signal recording device that can reproduce faithfully reproduced data using a digital clock.

Another object of the present invention is to provide a digital signal recording device that can record digitized data using a sampling frequency that is completely freely determined within the range of the device's capabilities. be.

``Summary of the Invention'' This invention provides system clocking in which an input digital signal is multiplexed to a buffer memory using an external clock signal synchronized with the input digital signal, and the input digital signal is read out from the buffer memory and used as a system clock for a recording device. This digital signal recording apparatus is characterized in that an input digital signal from a buffer memory is supplied to a recording processor operated by clocking, and the output of the recording processor is recorded on a recording medium.

"Embodiment" An embodiment in which the present invention is applied to a digital data recorder will be described below. In FIG. 1 showing the overall configuration of this embodiment, 1 indicates the point where analog data is supplied.
In the OA7'v converter 1, which shows the VD'' converter,
Supplied by external clock CKW! Q, one sample is, for example, 8
The bit digital data is input from the converter 1 to the buffer memory 2 ". , A/D:In? The output data of the data recorder 1 is written to the buffer memory 2 using the external clock CKW, and is also written to the system clock CKS from the clock generation circuit 3 inside the data recorder.
Reads from the buffer memory 2 by IB. The external clock CK'W is of high precision and is well managed to avoid drift due to temperature. The digital data read out from the buffer memory 2 is supplied to the redundant code generation circuit 4. 2"L15.5 indicates an interface. Interface 5 is generated when recording a control word.

This control word is supplied to the redundant code generation circuit 4.
Do 1. Inside the interface 5, there is a buffer memory 2.
An address controller is provided to control the address of n.
ing. The interface 5 also serves as an intermediary for storing data from an external host computer, such as graphics data, in the buffer memory 2 regardless of the recording operation, and for pulling input digital data from the buffer memory 2 to the post computer.

The redundant code generation circuit 4 uses the unit of recording length n times one scan in one scan of the 9-rotation head.

Shuffling is performed to convert the data order to a different order from the original one, and the shuffling and one scan data is encoded with an error correction code. As an error correction code, 1, for example, a product code,
Its vertical and horizontal directions trs ku-r %-ir ik-%, I-1, 7II %-1: sory-T=
What did you use for the shield? Can be applied. The block address and identification data of the recording data are also formed by the redundant code generation circuit 4 and inserted into each block of recording data.

Output data of redundant code generation circuit 4 is supplied to encoder 6. The encoder 6 performs channel encoding of the recording data and inserts block synchronization number 13, and the output of the encoder 6 is as follows.

Recorded data divided into four channels is retrieved.

For channel encoding, for example, convert 1 sample 8 bits to 1 sample 9 bits (8-9)
Transformations can be used.

The output of each channel of the encoder 6 is sent to the recording amplifier 7A,
'7B, 7C, 7D and rotating heads 8A, 8B, f3C via a rotating transformer (not shown).

8D and recorded on the magnetic tape 9 21rL. Processing of digital data read from the buffer memory 2 or the memory of the interface 5 described above.

It is clocked by the system clock CKS.

FIG. 2 shows the recording/recording of the magnetic tape 9 in this embodiment.
shows a turn. Rotation ~nd 8A, 8B, 8 C, , 8
D scans the magnetic tape 9 wound around the tape guide drum diagonally from the bottom to the top, and scans four parallel tracks 10A, IDB, 10.D in one scan. C
,'l OD is formed.

Audio track 1 along the longitudinal direction of magnetic tape 9
1A, 11B, 11C and a control trunk 11D are provided. A sequence number as a trunk address is recorded in the audio track 11C.
Servo signals are recorded on the control track 11D.

Data processing is performed in units of data P of one scan. FIG. 3A shows the recorded data of the first scan output from the redundant code generation circuit 4.

One scan includes 512 blocks from 0th to 511th. s 1277:: Of the vines, 32 blocks are redundant codes, 2 blocks are control words, and 478 blocks are digital data. The control word is one block consisting of a sequence number, a data size signal indicating the number of long sword data in one Sugiyan period, and a user's code.
The same thing is recorded twice as two blocks. The recording data of this 51-length block is recorded on four tracks by the booter controller 1/4. As shown in Figure 3B, one block consists of a 4-byte CRC code (
It is a type of cyclic code and is 128 bytes including a redundant code for error detection. At the beginning of each block, the encoder 6 adds a 2-byte block synchronization signal 5YhTC and a 2-byte block address AD and identification signal as shown in the third tJc.

The signals reproduced from the magnetic tape 9 by the rotary heads 8A, 8B, and 80° 8D are transmitted to a rotary transformer (not shown) and reproduction amplifiers 12A, 12B, and 12C.

1 and 2 are supplied to the PLL circuit 13 via D, respectively.

The PLL circuit 13 extracts a clock from the reproduced data of each track. The output of the P'LL circuit 13 is supplied to a decoder 14. The decoder 14 is.

A circuit for extracting a block synchronization signal 1 includes a TBC for removing time axis fluctuations, a channel decoder, etc., and the output of the decoder 14 provides reproduced data that has not been returned to one channel. This reproduced data is supplied to the error correction circuit 15.

The error correction circuit 15 includes a deshuffling circuit that returns the data arrangement to its original order, and a correction circuit that performs vertical and horizontal error correction twice. At the output of the error correction circuit 15, reproduced digital data with a 1-bit error flag added to each sample is extracted from the output signal 21. Pamphlet memory 16 and interface 17
It will be supplied to The error flag indicates that an error has been detected.
J 21 If the sample data is missing or the error has been corrected, the level will be low, and the opposite sample data L'
The level is high when the sample data contains 3 errors. Among the reproduced data, error-free sample data, that is, valid sample data, are stored in the buffer memory 16 and the memory of the interface 17 first. Digital data is written into the buffer memory 16 (2t), and a control word is written into the memory of the interface 17 (n).

This writing is terminated by the system clock CK'S from the clock generation circuit 3. On the other hand, reading the memories of the buffer memory 16 and interface 17 is as follows:
This is done using an external clock CKH. The interface 17 is provided with an address controller that controls the address of the buffer memory 16. The reproduced digital data read out from the buffer memory 16 is supplied to the /A converter 18 20. External clock CK
H converts it into analog data and outputs it.

This external clock CKR is the same as the external clock CKW used during recording, and is a well-managed '20 and extremely stable lock signal.

In addition, the external clocks CKR and CKW are set so that overflow does not occur in the buffer memory 2 and the buffer memory 16 when processing one scan of data.
The system clock CKS is of low frequency.

The interface 17 takes in control data during +M playback, and also acts as an intermediary when the playback data whose sequence number matches the sequence number specified by the user is uploaded to the host computer. 19 indicates a 2t microprocessor installed in the above-mentioned processor that processes data on the recording side and the reproduction side,
A data and address bus 20 is provided between the microprocessor 19 and the interfaces 5 and 17.

21 is the system controller of this embodiment? , the system controller 21 and the microprocessor 19
A data and address bus 22 is provided between the system controller 21 and the host computer (n).
(not shown) and connection 20. System controller 2
1 includes a built-in microprocessor, a keyboard 23 . Memory 24 for data files. A CRT display 25 + printer 26 is provided. System controller 2
1 remotely controls a rotary head type recorder including one-rotation heads 8A to sD, sit tape 9, etc., and thereby controls various operations of the data recorder.
do. Further, by the user's operation of the keyboard 23, a user's code representing the year, month, day, hour, data type, etc. is generated.

"Application Example" This invention is applicable not only to digital data but also to recording still image data. The present invention is applicable not only to a single-rotation head type recording device but also to a recording device using a fixed head.

According to this invention, it is possible to eliminate not only unevenness in the running speed of the magnetic tape but also the influence of drift due to the temperature of the system clock, and it is possible to obtain faithful playback data regardless of the status of a single device. nru. According to the present invention, the sampling frequency can be completely set to 1, as long as it does not exceed the capability of the device determined by the capacity of the buffer memory, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of this invention; FIG. 2 is a recording pattern diagram of an embodiment of the invention; FIGS. 1 and 3 are data configurations of an embodiment of the invention. It is a route map showing. 1...;・A/D Konnokuri, 2.16...
...Nokurahua memory, 3...Clock generation circuit, 5.17...Interface, 9...
···Magnetic tape. 18...D/A''n'<-taO Agent Masa Tomo Sugiura

Claims (1)

[Claims] The input digital signal is written into the buffer memory using an external clock signal synchronized with the input digital signal, and the input digital signal is read from the buffer memory according to the system clock signal of the recording device, and the system operates according to the system clock signal. supplying the input digital signal from the buffer memory to a recording processor,
A digital signal recording device characterized in that the output of the recording processor is recorded on a recording medium.