JPS6010351U - Absolute value coefficient circuit - Google Patents
Absolute value coefficient circuitInfo
- Publication number
- JPS6010351U JPS6010351U JP9914683U JP9914683U JPS6010351U JP S6010351 U JPS6010351 U JP S6010351U JP 9914683 U JP9914683 U JP 9914683U JP 9914683 U JP9914683 U JP 9914683U JP S6010351 U JPS6010351 U JP S6010351U
- Authority
- JP
- Japan
- Prior art keywords
- output
- resistor
- inverting input
- absolute value
- value coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案の実施例を示し、第１図は回路図、第２図お
よび第３図は等節回路、第４図は入出力特性の例を示す
図である。
ＩＮ・・・・・・入力端子、ＯＵＴ・・・・・・出力端
子、Ｒ１−Ｒ４・・・・・・抵抗器、Ａ、、 Ａ２・・
・・・・差動増幅器、Ｄ、、 Ｄ２・・・・・・ダイオ
ード。The figures show an embodiment of the present invention, in which FIG. 1 is a circuit diagram, FIGS. 2 and 3 are isochoric circuits, and FIG. 4 is a diagram showing an example of input/output characteristics. IN...Input terminal, OUT...Output terminal, R1-R4...Resistor, A, A2...
...Differential amplifier, D,, D2...Diode.
Claims (1)
第１乃至第４の抵抗器と、該第１の抵抗器′と第２の抵
抗器との接続点へ反転入力が接続されかつ共通回路へ非
反転入力が接続されると共に前記第２の抵抗器と第３の
抵抗器との接続点へ出力が接続された第１の差動増幅器
と、該増幅器の出力が負極性のときオンになる方向とし
て該出力へ直列に挿入された第１のダイオードと、前記
第３の抵抗器と第４の抵抗器との接続点へ反転入力が接
続されかつ前記共通回路へ非反転入力が接続されると共
に前記出力端子へ出力が接続された第゛２の差動増幅器
と、該増幅器の出力が正極性のときオンになる方向とし
て該出力へ直列に挿入された第２のダイオードとからな
ることを特徴とする絶対値係数回路。first to fourth resistors inserted sequentially and in series between the input terminal and the output terminal, and an inverting input connected to the connection point between the first resistor' and the second resistor; a first differential amplifier having a non-inverting input connected to a common circuit and an output connected to a connection point between the second resistor and the third resistor, and when the output of the amplifier is of negative polarity; an inverting input is connected to a connection point between a first diode inserted in series to the output for turning on, the third resistor and a fourth resistor, and a non-inverting input is connected to the common circuit; a second differential amplifier whose output is connected to the output terminal; and a second diode inserted in series to the output so as to turn on when the output of the amplifier is of positive polarity. An absolute value coefficient circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9914683U JPS6010351U (en) | 1983-06-27 | 1983-06-27 | Absolute value coefficient circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9914683U JPS6010351U (en) | 1983-06-27 | 1983-06-27 | Absolute value coefficient circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010351U true JPS6010351U (en) | 1985-01-24 |
| JPS6142194Y2 JPS6142194Y2 (en) | 1986-12-01 |
Family
ID=30235087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9914683U Granted JPS6010351U (en) | 1983-06-27 | 1983-06-27 | Absolute value coefficient circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010351U (en) |
-
1983
- 1983-06-27 JP JP9914683U patent/JPS6010351U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6142194Y2 (en) | 1986-12-01 |
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