JPS58153460U - Temperature compensation bias circuit for PIN diode - Google Patents
Temperature compensation bias circuit for PIN diodeInfo
- Publication number
- JPS58153460U JPS58153460U JP4927882U JP4927882U JPS58153460U JP S58153460 U JPS58153460 U JP S58153460U JP 4927882 U JP4927882 U JP 4927882U JP 4927882 U JP4927882 U JP 4927882U JP S58153460 U JPS58153460 U JP S58153460U
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- terminal
- pin diode
- bias circuit
- temperature compensation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例によるＰＩＮダイオードのバイアス回路
図、第２図は本考案の実施例による同上回路図である。
６：電圧入力端子、８：ダイオード、９，１２゜１４：
演算増幅回路、１５：ＰＩＮダイオード、１６：負荷抵
抗。FIG. 1 is a bias circuit diagram of a PIN diode according to a conventional example, and FIG. 2 is a circuit diagram of the same according to an embodiment of the present invention. 6: Voltage input terminal, 8: Diode, 9, 12° 14:
Operational amplifier circuit, 15: PIN diode, 16: load resistance.
Claims (1)
が接続された第１の演算増幅器と、正端子がアースされ
、負端子と出力端子間に抵抗が接続された第２の演算増
幅器と、負端子と出力端子間にＰＩＮダイオードが接続
された第３の演算増幅器とを備え、電圧入力端子を抵抗
を介して前記第１の演算増幅器の負端子に接続し、この
第１の演算増幅器の出力端子を抵抗を介して前記第２の
演算増幅器の負端子に接続し、この第２の演算増幅器の
出力端子を前記第３の演算増幅器の正端子に接続し、こ
の第３の演算増幅器の負端子とアース間に負荷抵抗を接
続して構成したことを特徴とするＰＩＮダイオード用温
度補償バイアス回路。a first operational amplifier whose positive terminal is grounded and a diode connected between the negative terminal and the output terminal; a second operational amplifier whose positive terminal is grounded and a resistor connected between the negative terminal and the output terminal; a third operational amplifier having a PIN diode connected between the negative terminal and the output terminal; the voltage input terminal is connected to the negative terminal of the first operational amplifier via a resistor; The output terminal of the second operational amplifier is connected to the negative terminal of the second operational amplifier through a resistor, the output terminal of the second operational amplifier is connected to the positive terminal of the third operational amplifier, and the output terminal of the second operational amplifier is connected to the positive terminal of the third operational amplifier. A temperature compensation bias circuit for a PIN diode, characterized in that it is configured by connecting a load resistor between a negative terminal and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4927882U JPS58153460U (en) | 1982-04-07 | 1982-04-07 | Temperature compensation bias circuit for PIN diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4927882U JPS58153460U (en) | 1982-04-07 | 1982-04-07 | Temperature compensation bias circuit for PIN diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58153460U true JPS58153460U (en) | 1983-10-14 |
Family
ID=30060148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4927882U Pending JPS58153460U (en) | 1982-04-07 | 1982-04-07 | Temperature compensation bias circuit for PIN diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58153460U (en) |
-
1982
- 1982-04-07 JP JP4927882U patent/JPS58153460U/en active Pending
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