JPS60102073A - Video signal ciphering device - Google Patents

Video signal ciphering device

Info

Publication number
JPS60102073A
JPS60102073A JP58208930A JP20893083A JPS60102073A JP S60102073 A JPS60102073 A JP S60102073A JP 58208930 A JP58208930 A JP 58208930A JP 20893083 A JP20893083 A JP 20893083A JP S60102073 A JPS60102073 A JP S60102073A
Authority
JP
Japan
Prior art keywords
signal
video signal
switching
digital signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58208930A
Other languages
Japanese (ja)
Inventor
Tomoji Motoyoshi
本吉 知司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58208930A priority Critical patent/JPS60102073A/en
Publication of JPS60102073A publication Critical patent/JPS60102073A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain ciphering without changing the polarity of a video signal by converting an input video signal into a digital signal and conducted by switching a digital signal formed by delaying the former signal with prescribed clock's share of delay and a digital signal not delayed. CONSTITUTION:An input video signal SA fed from a television camera or a VTR is converted into a digital signal SD at an A/D converter 4. The digital signal SD is fed to a switching circuit 8 and also a delay circuit 10, where the input digital signal is delayed based on the clock from the pulse circuit 6 and the result is fed to the switching circuit 8. A digital signal SP not delayed and a delayed digital signal SD' are switched at each prescribed time at the switching circuit 8 by using a switching pulse P from a switching pulse generating circuit 12 and outputted while being ciphered.

Description

【発明の詳細な説明】 〔尾明の技術分野〕 1こ 本発明は有料テレビジョン放送等が使用される映摩信号
の暗号化装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Omei's Technical Field] 1. The present invention relates to an encryption device for video signals used in pay television broadcasting and the like.

〔発明の技術的背景上その問題点〕[Problems with the technical background of the invention]

従来、有料テレビジョン放送前に用いる映1象信号の暗
号化方式としては同期信号部分に関するものと1決像信
号部分に関するものが行われている。前者は同期信号の
一部除去及び極性反転等により、後者は映像信号の極性
反転等によっている。
Conventionally, as encryption methods for video signals used before pay television broadcasting, methods have been used for the synchronization signal portion and for the one-image signal portion. The former involves removing part of the synchronizing signal and inverting the polarity, and the latter involves inverting the polarity of the video signal.

一方、この暗号化方式として通常のテレビジョン放送波
と同様な信号形態で、しかも映像信号が暗号化されてい
る方式が請求されている。
On the other hand, as this encryption method, a method is being requested in which the signal format is similar to that of normal television broadcast waves, and in addition, the video signal is encrypted.

この暗号化方式では同期信号はそのままとし映像信号部
を極性反転させるものが採用されている・) しかし、この映像信号部の暗号化方式でFi組付せ数を
増力口させると復号器側の回路が1褪雑となり、又、粗
汁せ数を少くすうと比較的簡単に解読されるという欠点
を有していた。
In this encryption method, the polarity of the video signal section is inverted while leaving the synchronization signal as is.) However, if you increase the number of Fi assemblies in this video signal encryption method, the decoder side It has the disadvantage that the circuit becomes complicated and that it can be decoded relatively easily if the number of circuits is reduced.

〔発明の目的〕[Purpose of the invention]

本発明はかかる欠点を除去するもので映像信号部の秘匿
性が高く、かつ、通2にのテレビジョン放送波に適用し
得る映像信号暗号化装置を提供するものである○ 〔発明の概安〕 本漬間KJ−i−いては入力映像16号をディジタル1
d号に変換し、これを所定のクロック分遅延したディジ
タル信号と遅延しないディジタル信号とを切換えて導出
し、アナログ信号に変換して暗号化出力を得るものであ
るO 〔発明の実施例〕 以[、図面を参照して本発明の一実施例について説明す
る。
The present invention eliminates such drawbacks and provides a video signal encryption device that has a high degree of confidentiality in the video signal portion and can be applied to commonly used television broadcast waves. ] Honzuma KJ-i input video No. 16 is converted into digital 1
d code, which is then derived by switching between a digital signal delayed by a predetermined clock and a non-delayed digital signal, and converted into an analog signal to obtain an encrypted output. [, An embodiment of the present invention will be described with reference to the drawings.

r*< 1図は回路構成を示すものでテレビジョンカメ
ラ、VTR%から供給されるアナログ信号の第2図ta
)に示す人力映像信号(SA)は端子(2)からアナロ
グ−ディジタル変換器(以ト’A/D俊侠器と称す) 
+4) K導入され、ディジタル信号(SD)に震侯さ
れる0このA/I)変換器(4)にはパルス回路(6)
からクロック(Ct、)が供給され、このクロックに応
じて変換が行われる0第2図(a)においては−水平走
置期間lを示すもので、Tはこのクロック(CL)の1
クロック分を示し、A/D変換器(4)からは第2図(
1))に7廖すディジタル映像信号(SD )が導出さ
れる。
r*< Figure 1 shows the circuit configuration, and Figure 2 shows the analog signal supplied from the television camera and VTR%.
The human video signal (SA) shown in
+4) This A/I) converter (4) is equipped with a pulse circuit (6) which is injected into the digital signal (SD).
A clock (Ct, ) is supplied from the clock (Ct,), and conversion is performed according to this clock.
The clock minutes are shown in Fig. 2 from the A/D converter (4).
1)) A digital video signal (SD) is derived.

このA / I)変換器(4)からのディジタル映像信
号(SD)は切換回路(8)に供給されろとともに遅延
回路:10)に供給される。この遅延回路110)はゲ
イジタル遅延回路で構成され、パルス回路(6)からの
クロック(CL)を基にして、そのクロック分に応じて
入力ディジタル映像信号(SD)の遅延が行われる。そ
の遅延量は偶数のクロックの整数倍に選定されるもので
、図においては4クロック分の遅延を示し=A2図(Q
に示す遅延ディジタル映1象信号(S’D)が導出され
る0この遅延ディジタル映像信号(S / I) )は
切侠回1烙・8)にA / I)変換器(4)からの遅
延されないディジタル映1埃信号(SD)とともに供給
される。
The digital video signal (SD) from this A/I) converter (4) is supplied to a switching circuit (8) and a delay circuit (10). This delay circuit 110) is constituted by a gain digital delay circuit, and based on the clock (CL) from the pulse circuit (6), the input digital video signal (SD) is delayed in accordance with the clock. The amount of delay is selected as an integer multiple of an even number of clocks, and the figure shows a delay of 4 clocks = Figure A2 (Q
The delayed digital video signal (S'D) shown in is derived. This delayed digital video signal (S/I) is input from the A/I) converter (4) to the It is supplied with an undelayed digital video signal (SD).

切換回路+8+はディジタルスイッチング回路から成り
、切換パルス発生回路u21からの第2図td)に示す
切換パルス(1))によって遅延しないディジタル映像
信号(SD)と遅延したディジタル映1象信号(S/D
)とを所定期間毎に切換えて導出が行われる。切換パル
ス発生回路Uはノく107回路(6)からのクロック(
CL)によって動作され、このクロック(C、L )に
同期した切換・くルス(P)の鏑生が行われる。この切
換ノ(ルスtP)の切換周期は第2図+d)図示の如く
前記遅延量の1/2に選ホキれるもので2クロック分と
される。
The switching circuit +8+ is composed of a digital switching circuit, and is configured to output a digital video signal (SD) that is not delayed and a delayed digital video signal (S/ D
) at predetermined intervals. The switching pulse generation circuit U receives the clock from the 107 circuit (6) (
CL), and switching and generation of pulses (P) are performed in synchronization with this clock (C, L). The switching period of this switching node (tP) can be selected to be 1/2 of the delay amount, as shown in FIG. 2+d), and is two clocks.

切換パルス(P)によって切換回路(8)からは第2図
ie)に示すディジタル映像信号(S″D)が導出され
る。この信号(S // o )は図示の911<クロ
ック(CL)の2タロツク分(z’r)毎に遅延しない
ディジタル映1象倍号(SD)と遅延したディジタル映
像信号(S/D)が合成されている0このディジタル映
像信号(S// D )はディジタル−アナログ変換器
ll4)に供給され、;π2図(f)の如きアナログ信
号に変換されるOこのアナログ信号に変換された信号は
人力映像信号(8人)に対して暗号化出力として出力端
子(16)に導出される。
A digital video signal (S″D) shown in FIG. 2 ie) is derived from the switching circuit (8) by the switching pulse (P). This digital video signal (S//D) is composed of a non-delayed digital video signal (SD) and a delayed digital video signal (S/D) every 2 taroks (z'r). The signal is supplied to a digital-to-analog converter ll4) and converted into an analog signal as shown in Figure (f); π2. The signal converted to an analog signal is output as an encrypted output for the human input video signal (8 people). It is led out to the terminal (16).

なお、この暗号化された信号を復号するには上記遅延切
換と同じ+段を行って達成することができる。
Note that decoding of this encrypted signal can be achieved by performing the same + stage as the delay switching described above.

〔発明の効果〕〔Effect of the invention〕

以上、説明した様に本発明によれば、(:’l; 4止
及び切換によって暗号化を行うだめ、その1ljf= 
1通計、切換期間を変化させることにより多数の組εr
せで暗号化を行い得、その復号はt+Aj定のもののみ
によって口f能とすることができる0ま/ζ、ll′J
!−謬信号部の極性を変化させることなく暗号化するた
め通常のテレビジョン放送波としてそのまま利用するこ
とができる。
As explained above, according to the present invention, (:'l; 4) Since encryption cannot be performed by stopping and switching, 1ljf=
A large number of sets εr can be created by changing the switching period in one total.
0ma/ζ,ll′J
! - Since it is encrypted without changing the polarity of the error signal part, it can be used as is as a normal television broadcast wave.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による映像信号暗号化装置の一実画例を
示す回路構成図、第2図褥井≠叫は第1図の動作を説明
する各部の信号波彩図である0 4・・アナログ−ディジタル変JヤjWiy+8 ・・
切換回路、10・・・遅延回路、14・・グイジクル−
アナログ変換器。
FIG. 1 is a circuit configuration diagram showing an example of a video signal encryption device according to the present invention, and FIG. 2 is a signal wave diagram of each part explaining the operation of FIG. 1.・Analog-digital change JyajWiy+8...
Switching circuit, 10... Delay circuit, 14... Guidance
analog converter.

Claims (2)

【特許請求の範囲】[Claims] (1)人力映像信−号を所定クロックに応じてディジタ
ル信号に変換する手段と、このディジタル信号を前記ク
ロックの所定分遅延させる遅延手段と、この遅延ディジ
タル信号と遅延しない前記ディジタル信号とを所定期間
毎に切換え導出する切換手段と、この切換手段からのデ
ィジタル1g号をアナログ信号に変換する手段とを具備
する映像信号暗号化装置4゜
(1) means for converting a human video signal into a digital signal according to a predetermined clock; a delay means for delaying this digital signal by a predetermined amount of the clock; A video signal encrypting device 4゜ comprising a switching means for switching and deriving every period, and means for converting the digital 1g signal from the switching means into an analog signal.
(2)前記リノ侠手段はディジタル変換のクロックに同
期して切換えを行うことを特徴とする特許請求の範囲第
一項記載の映像信号暗号化装置0
(2) The video signal encrypting device 0 according to claim 1, characterized in that the renovating means performs switching in synchronization with a digital conversion clock.
JP58208930A 1983-11-09 1983-11-09 Video signal ciphering device Pending JPS60102073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58208930A JPS60102073A (en) 1983-11-09 1983-11-09 Video signal ciphering device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58208930A JPS60102073A (en) 1983-11-09 1983-11-09 Video signal ciphering device

Publications (1)

Publication Number Publication Date
JPS60102073A true JPS60102073A (en) 1985-06-06

Family

ID=16564476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58208930A Pending JPS60102073A (en) 1983-11-09 1983-11-09 Video signal ciphering device

Country Status (1)

Country Link
JP (1) JPS60102073A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02237238A (en) * 1988-06-07 1990-09-19 Macrovision Corp Method and device for coding and decoding time area signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02237238A (en) * 1988-06-07 1990-09-19 Macrovision Corp Method and device for coding and decoding time area signal

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