JPS60100670U - Inspection device for inner layer shield board of multilayer printed circuit board - Google Patents

Inspection device for inner layer shield board of multilayer printed circuit board

Info

Publication number
JPS60100670U
JPS60100670U JP19230183U JP19230183U JPS60100670U JP S60100670 U JPS60100670 U JP S60100670U JP 19230183 U JP19230183 U JP 19230183U JP 19230183 U JP19230183 U JP 19230183U JP S60100670 U JPS60100670 U JP S60100670U
Authority
JP
Japan
Prior art keywords
inner layer
printed circuit
multilayer printed
circuit board
layer shield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19230183U
Other languages
Japanese (ja)
Inventor
鴻上 修
耕治 和田
Original Assignee
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電工株式会社 filed Critical 松下電工株式会社
Priority to JP19230183U priority Critical patent/JPS60100670U/en
Publication of JPS60100670U publication Critical patent/JPS60100670U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は多層プリント基板内層シールド板の正面図、第
2図a、 b、 cは同上の不良発生説明図、第3図は
本考案の一実施例の回路構成図、第4図は同上のスイッ
チ部の切替スイッチの電気回路図、第5図は同上の使用
状態説明図、第6図a、 bは同上の不良検出の説明図
、第7図、第8図は同上の検査ピンの先部拡大図であり
、1はクリアランスホール、1aは孔、2はランド、9
は報知用ブザー、1layllbは外部接続端子、12
はスイッチ部、14は検査治具、15は検査ピン、15
 a、  15a’は凹所、SWは切替スイッチ、LE
Dは発光ダイオードである。 第6図 1 16  ’I       l。/ −第7図 −5゜・  −、−
Figure 1 is a front view of the inner layer shield plate of a multilayer printed circuit board, Figures 2 a, b, and c are diagrams explaining the occurrence of defects in the same as above, Figure 3 is a circuit configuration diagram of an embodiment of the present invention, and Figure 4 is in the same as above. Fig. 5 is an illustration of the state of use of the same as above, Fig. 6 a and b are illustrations of defect detection of the same as above, Fig. 7 and Fig. 8 are diagrams of the inspection pin of the same as above. This is an enlarged view of the tip, where 1 is a clearance hole, 1a is a hole, 2 is a land, and 9
is a notification buzzer, 1layllb is an external connection terminal, 12
14 is a switch part, 14 is an inspection jig, 15 is an inspection pin, 15
a, 15a' is the recess, SW is the changeover switch, LE
D is a light emitting diode. Figure 6 1 16 'I l. / -Figure 7-5゜・-,-

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] クリアランスホール、ランド部を所定の間隔で形成した
多層プリント基板内層シールド板上に上記間隔に対応し
て設けである複数の検査ピンを当接する検査治具と、各
検査ピンに1対1で設けた切替スイツtを設けであるス
イッチ部と、前記検査ピンに対して接続される対の電源
出力用の外部接続端子を備えて外部接続端子間が短絡さ
れると電源と外部接続端子との間に挿入されたブザーや
、発光素子のような表示手段によって表示を行なう短絡
検知手段とを有口前記切替スイッチによってクリアラン
スホール内の孔の開口に当接する検査ピンと、ランド部
に当接する検査ピンとに接続される電源極性を自在に選
択設定することを特徴とする多層プリント基板内層シー
ルド板の検査装置において、検査ピンの先部下面に凹所
を形成したことを特徴とする多層プリント基板内層シー
ルド板の検査装置。
An inspection jig that abuts a plurality of inspection pins provided corresponding to the above-mentioned intervals on the inner layer shield plate of a multilayer printed circuit board in which clearance holes and land portions are formed at predetermined intervals; A switch unit is provided with a switching switch t, and a pair of external connection terminals for power output are connected to the test pin, so that when the external connection terminals are short-circuited, the power supply and the A short-circuit detection means that displays an indication by a display means such as a buzzer or a light-emitting element inserted into the hole is connected to the test pin that contacts the opening of the hole in the clearance hole and the test pin that contacts the land portion using the apertured changeover switch. An inspection device for a multilayer printed circuit board inner layer shield board characterized by freely selecting and setting the polarity of a connected power source, the multilayer printed circuit board inner layer shield board having a recess formed on the lower surface of the tip of the test pin. inspection equipment.
JP19230183U 1983-12-14 1983-12-14 Inspection device for inner layer shield board of multilayer printed circuit board Pending JPS60100670U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19230183U JPS60100670U (en) 1983-12-14 1983-12-14 Inspection device for inner layer shield board of multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19230183U JPS60100670U (en) 1983-12-14 1983-12-14 Inspection device for inner layer shield board of multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS60100670U true JPS60100670U (en) 1985-07-09

Family

ID=30413886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19230183U Pending JPS60100670U (en) 1983-12-14 1983-12-14 Inspection device for inner layer shield board of multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS60100670U (en)

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