JPS60100464A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60100464A JPS60100464A JP58207425A JP20742583A JPS60100464A JP S60100464 A JPS60100464 A JP S60100464A JP 58207425 A JP58207425 A JP 58207425A JP 20742583 A JP20742583 A JP 20742583A JP S60100464 A JPS60100464 A JP S60100464A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- polycrystalline
- refractory metal
- barrier layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 239000003870 refractory metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910021332 silicide Inorganic materials 0.000 abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052718 tin Inorganic materials 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 229910004531 TaB Inorganic materials 0.000 abstract 1
- 229910010055 TiB Inorganic materials 0.000 abstract 1
- 229910052763 palladium Inorganic materials 0.000 abstract 1
- 229910052715 tantalum Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 230000015654 memory Effects 0.000 description 9
- 238000003491 array Methods 0.000 description 3
- 230000007774 longterm Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はＭＯ８−ＬＳＩに係シ、特に低抵抗で、かつ長
期信頼性に優れたゲートを持つＭＯ８−ＬＳＩに関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an MO8-LSI, and particularly to an MO8-LSI having a gate with low resistance and excellent long-term reliability.
従来広く用いられている多結晶ＳｉやＭＯシリサイド等
は、その抵抗が十分には低くないという゛欠点をもって
いる。たとえば厚さを３ＱＱＨｍとすると、多結晶Ｓｉ
とＭＯシリサイドはそれぞれシート抵抗が２０Ω／口、
４Ω／口程度である。Polycrystalline Si, MO silicide, etc., which have been widely used in the past, have the disadvantage that their resistance is not sufficiently low. For example, if the thickness is 3QQHm, polycrystalline Si
and MO silicide have a sheet resistance of 20Ω/mouth, respectively.
It is about 4Ω/mouth.
素子の機側化に伴なってＷやＭＯ等のリフラクトリ金属
を用いるとシート抵抗は１Ω／口以下にしうるが、ＭＯ
Ｓトランジスタのゲートをこれらの金属で形成するとｂ
わゆるしきい′電圧ＶＴの変化を引き起すホットエレク
トロン耐性が低下し、長期信頼度に劣るという欠点がめ
った。When devices are moved to the machine side, the sheet resistance can be reduced to 1 Ω/hole or less by using refractory metals such as W or MO.
When the gate of an S transistor is formed of these metals, b
The drawback is that the resistance to hot electrons that cause changes in the so-called threshold voltage VT is reduced, resulting in poor long-term reliability.
本発明の目的は多結晶８ｉゲート並の高信頼度と、リフ
ラクトリ金属ゲートの低抵抗性をもつゲートをもつＭＯ
Ｓトランジスタを提供することにある。The purpose of the present invention is to provide an MO gate with high reliability comparable to that of a polycrystalline 8i gate and low resistance of a refractory metal gate.
An object of the present invention is to provide an S transistor.
本発明の骨子は、薄いゲート酸化膜上は多結晶Ｓｉゲー
トで構成し、この上部にり７ラクトリ金属とＳｔの反応
を阻止するバリヤ層を設け、さらにこの上部にす７２ク
トリ金属を形成するものでるる。す７ラクトリ金属と、
バリヤ層、多結晶Ｓｉは同一のパターンで一括してバタ
ーニングする。こねによってマスク合せなしに従来と同
寸法でゲートが形成できる。The gist of the present invention is that a polycrystalline Si gate is formed on a thin gate oxide film, a barrier layer is provided on top of this to prevent the reaction between the 7-tri-metal and St, and a 72-tri-metal is further formed on top of this. It comes out. 7 Lactoli metals and
The barrier layer and polycrystalline Si are patterned all at once in the same pattern. By kneading, a gate can be formed with the same dimensions as before without the need for mask alignment.
以下、本発明の一実施列を第１図により説明する。Ｓｌ
基板１上によく知られたＬＯＣＯ８（ＬｏｃａｌＱｘｉ
ｃｌａｒｉｏｎ ｏｆ ５ｉｌｉｃｏｎ ）法で０．５
〜１μｍ厚のフィールド酸化膜２を形成する。フィール
ド酸化膜２の形成されない部分の一部にゲート酸化膜３
全２〜ｉＱＱＨｍ厚に形成する。この後リンやＡＳを添
刀ｎした多結晶Ｓｉ４を被着し、Ｐｔやｐｄのシリサイ
ドやＴｉＮ、９るいは’ｌ’ｉ１３． ＴａＢ等のパリ
ャノｗｉ５を被着し、さらにＷ、Ｍｏ、あるいはＴａな
どのり７ラクトリ金属６を被着しこの三層のゲートを一
括して同一パターンによってエツチングしてＭＯＳ ）
ランジスタのゲートを形成する。Hereinafter, one embodiment of the present invention will be explained with reference to FIG. Sl
The well-known LOCO8 (LocalQxi
clarion of 5ilicon) method 0.5
A field oxide film 2 with a thickness of ~1 μm is formed. A gate oxide film 3 is formed on a part of the area where the field oxide film 2 is not formed.
It is formed to a total thickness of 2 to iQQHm. After that, polycrystalline Si4 coated with phosphorus or AS is deposited, Pt or PD silicide, TiN, 9 or 'l'i13. MOS (MOS) is formed by depositing Palyano Wi5 such as TaB, and then depositing glue 7 and lamination metal 6 such as W, Mo, or Ta, and etching these three layers of gates in the same pattern at once.
Forms the transistor gate.
第１図はトランジスタのチャネル幅方向の断面を示すが
、第２図（・よチャネル長方向の断面図を示す。領域７
はトランジスタのソース・ドレインである。本発明では
り７ラクトリ金属６は多結晶Ｓｉ４と反応して混シ合わ
ないので多結晶Ｓｉ。Figure 1 shows a cross-section of the transistor in the channel width direction, while Figure 2 shows a cross-section of the transistor in the channel length direction.
are the source and drain of the transistor. In the present invention, the laminated metal 6 reacts with polycrystalline Si4 and does not mix with polycrystalline Si4.
高信頼性とりフラクトリ金属の低抵抗性を兼ね備えるこ
とができる。It can combine high reliability with the low resistance of frac-trimetal metals.
第３図に本発明の他のズ施例を示す。第１〜第２図で述
べた実施例は、バリヤ層５が導電層であシ、す７ラクト
リ金楓６はいずれの部分でも多結晶Ｓｉ４に電気的に接
ｄされている。第３図に示す実施例は、このバリヤ層５
が、絶縁）摸である場合であシ、部分的にバリヤ層５に
接続孔８を形成し、この接続孔８を通じて多結晶Ｓｉ４
とす７ラクトリ金属８を′電気的に候＋涜する。この場
合、バリヤ層５としては、多結晶３ｉ４自身の熱酸化膜
。FIG. 3 shows another embodiment of the invention. In the embodiment described in FIGS. 1 and 2, the barrier layer 5 is a conductive layer, and the transparent gold maple 6 is electrically connected to the polycrystalline Si 4 at any part thereof. The embodiment shown in FIG.
In this case, a contact hole 8 is partially formed in the barrier layer 5, and the polycrystalline Si4
Then, the metal 7 and the metal 8 are electrically depleted. In this case, the barrier layer 5 is a thermal oxide film of the polycrystalline 3i4 itself.
窒化膜、ろるいはＣＶＤ法による５ｉ０２．ＰＳＧ（Ｐ
ｈｏｓｐｈｏ ５ｉｌｉｃａｔｅ Ｑｌａｓｓ ）、５
ｊｓＮ４膜等を用いることができる。これらの絶縁膜は
ｓｉのＬＳＩで広く用いられているもので、安定性。Nitride film, 5i02. by CVD method. PSG(P
5 ilicate Qlass ), 5
jsN4 film or the like can be used. These insulating films are widely used in Si LSIs and are stable.
信頼性の上で申し分のないものであシ、す７ラクトリ金
属６との反応も極めて少なく安定である。It is satisfactory in terms of reliability, and is stable with very little reaction with tri-metal 6.
この発明の実施例はり７ラクトリ金属６が直接多結晶８
ｉ４に接しているので、約１０００１：’以上の長時間
の熱処理では反応して空洞が発生し、電気的な接続が破
壊される場合があるので、第４図に他の実施例を示すよ
うにＴｉＮ単層やＴｉ／ＰＬＳｉ２二層等で代表される
接続バリヤ層９を接続孔部８に自己整合等で形成すれば
、１０００ｃ以上の熱処理にも耐えることができる。Embodiment of this invention Beam 7 Lactrimetal 6 is directly polycrystalline 8
Since it is in contact with i4, long-term heat treatment over about 10001:' may react and create cavities, destroying the electrical connection. Therefore, another example is shown in Fig. 4. If a connection barrier layer 9 typified by a TiN single layer or a Ti/PLSi2 double layer is formed in the connection hole 8 by self-alignment, it can withstand heat treatment of 1000C or more.
第５図に本発明の他の実施例を示す。本例は、メモリセ
ルが規則正しくアレー状に配列されているダイナミック
メモリセルアレーの例であシ、厚いフィールド酸化膜の
ない活性領域１ｏに、ゲートを兼ねたワード線１２と、
ソース・ドレイン接続孔１１を介してソース・ドレイン
領域に接続されたピント線１３がアレー状に形成される
。（本発明の説明には直接関与しないのでキャパシタ電
極たるプレートは図中に示さない。）特にこの例のよう
に、折シ返しビットａ型ではワード線１２はメモリセル
１つに対し２本分形成されており、一般にワード線１２
は単一層で形成されることが多い。本発明では、Ｍ１図
に示しｆｃ夾施例を用いることができ、かつ第３図と第
４図に示した実施例を用いることができる。この場合、
接続孔８はメモリセル個々に形成する必決はなく、第５
図に示したようにメモリセルアレーの特定の部分のみに
接続孔８を形成し、最下階の多結晶Ｓｉ４と上層のリフ
ラフ） ＩＪ輩属６を接続すればよい。第５図の説明で
は接続孔８はワード線１２幅よシ小さいが、大きくして
もよい。そうすれば、特に接続孔８とワード線１２のマ
スク合せに留意する必要がなく高集積に向いている。FIG. 5 shows another embodiment of the invention. This example is an example of a dynamic memory cell array in which memory cells are regularly arranged in an array. In an active region 1o without a thick field oxide film, a word line 12 which also serves as a gate is provided.
Pinto lines 13 connected to the source/drain regions via the source/drain connection holes 11 are formed in an array. (The plate serving as the capacitor electrode is not shown in the figure because it is not directly related to the explanation of the present invention.) In particular, in the folded bit a type as in this example, the word line 12 is two for one memory cell. generally word line 12
is often formed in a single layer. In the present invention, the fc-containing embodiment shown in FIG. M1 can be used, and the embodiments shown in FIGS. 3 and 4 can be used. in this case,
It is not necessary to form the connection hole 8 in each memory cell, but in the fifth hole.
As shown in the figure, connection holes 8 are formed only in specific portions of the memory cell array, and the polycrystalline Si 4 on the lowest floor and the riffraff (IJ) layer 6 on the upper layer are connected. In the explanation of FIG. 5, the connection hole 8 is smaller than the width of the word line 12, but it may be made larger. In this case, there is no need to pay particular attention to the mask alignment between the connection hole 8 and the word line 12, and the device is suitable for high integration.
接続孔８の配列ピッチＰは第６図に示すように形成する
。すなわちトランジスタ１４のゲート部１５に対して、
リフラクトリ金属６がら接続部の抵抗１７を介して多結
晶ｓｉ４の抵抗１８に接続される。この抵抗１８の末端
にトランジスタ１４のゲート１５が接続されておシ、ワ
ード線たるリフラクトリ金属６に印加する信号に対し許
容しうるだけの時間遅れを見込んでピッチＰを定めれば
よい。The arrangement pitch P of the connection holes 8 is formed as shown in FIG. That is, for the gate portion 15 of the transistor 14,
The refractory metal 6 is connected to a resistor 18 made of polycrystalline silicon 4 via a resistor 17 at a connection portion. The gate 15 of the transistor 14 is connected to the terminal of this resistor 18, and the pitch P may be determined by allowing for an allowable time delay with respect to the signal applied to the refractory metal 6, which is a word line.
この実施例はダイナミックメモリの例で示したが、スタ
チックメモリや、不揮発性メモリ、ゲートアレーなと細
くて長いリフラクトリ金属を必要とするすべてのＬＳＩ
に適用することができるのは明白である。Although this embodiment was shown as an example of a dynamic memory, it can also be applied to static memory, non-volatile memory, gate arrays, and all other LSIs that require thin and long refractory metal.
It is obvious that it can be applied to
本発明によｎは実績のある信頼性の高い多結晶Ｓｉゲー
トと耐熱性が高くかつ低抵抗す７ラクトリ金属の両者の
長所を合せもつゲートが形成でき、特にこのゲートを細
く長く配線する場合に適する。According to the present invention, it is possible to form a gate that combines the advantages of both the proven and reliable polycrystalline Si gate and the highly heat-resistant and low-resistance metal, especially when wiring this gate long and thin. suitable for
これによって大きなアレーをもつメモリや、ゲートアレ
ーを高速化することができる。This makes it possible to speed up memories with large arrays and gate arrays.
第１図〜第４図は本発明の実施例になる半導体装置の断
面図、第５図は平面図、第６図は模式図である。
１・・・Ｓｉ基板、２・・・フィールド酸化膜、３・・
・ゲート酸化膜、４・・・多結晶５Ｉｘ５・・・バリヤ
層、６・・・す７ラクトリ金属、７・・・ソース・ドレ
イン領域、８・・・接続孔、９・・・接続バリヤ層、１
０・・・活性帆域、１１・・・ソース・ドレイン接続孔
、１２・・・ワード線、１３・・・ビット線、１４・・
・トランジスタ、１５・・・ゲート部、１６・・・リフ
ラクトリ金属抵抗、１７・・・接第１図
第２図
第 ４− 図
第 ５ 図1 to 4 are sectional views of a semiconductor device according to an embodiment of the present invention, FIG. 5 is a plan view, and FIG. 6 is a schematic diagram. 1...Si substrate, 2...field oxide film, 3...
・Gate oxide film, 4... Polycrystalline 5Ix5... Barrier layer, 6... S7 lacquer metal, 7... Source/drain region, 8... Connection hole, 9... Connection barrier layer ,1
0...Active area, 11...Source/drain connection hole, 12...Word line, 13...Bit line, 14...
・Transistor, 15...Gate part, 16...Refractory metal resistor, 17...Connection Fig. 1 Fig. 2 Fig. 4- Fig. 5
Claims (1)
に形成したり７ラフトリ金属層の三層からｇかつ同一パ
ターンで形成されるゲート電極・配線を設けたことを特
徴とする半導体装置。 ２、上記第１項記載の半導体装置において上記バリヤ層
は導電層であることを％徴とする半導体装置。 ３、第１項記載の半導体装置において、上記バリヤ層は
絶縁膜であシ、かつ所定の部分で上記多結晶Ｓｉと上記
リフラクトリ金属が電気的に接続していることを特徴と
する半導体装置。 ４、第３項記載の半導体装置において上記接続部の上記
多結晶Ｓｉと上記リフラフ）ＩＪ金属間にバリヤ層を設
けたことを特徴とする半導体装置。[Claims] 1. A barrier formed on polycrystalline Si, and gate electrodes/wirings formed on the barrier layer and three layers of a rough metal layer and in the same pattern. Characteristic semiconductor devices. 2. The semiconductor device according to item 1 above, wherein the barrier layer is a conductive layer. 3. The semiconductor device according to item 1, wherein the barrier layer is an insulating film, and the polycrystalline Si and the refractory metal are electrically connected at a predetermined portion. 4. The semiconductor device according to item 3, further comprising a barrier layer provided between the polycrystalline Si of the connection portion and the riffraff IJ metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58207425A JPS60100464A (en) | 1983-11-07 | 1983-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58207425A JPS60100464A (en) | 1983-11-07 | 1983-11-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60100464A true JPS60100464A (en) | 1985-06-04 |
Family
ID=16539540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58207425A Pending JPS60100464A (en) | 1983-11-07 | 1983-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60100464A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4888297A (en) * | 1982-09-20 | 1989-12-19 | International Business Machines Corporation | Process for making a contact structure including polysilicon and metal alloys |
| US5438023A (en) * | 1994-03-11 | 1995-08-01 | Ramtron International Corporation | Passivation method and structure for a ferroelectric integrated circuit using hard ceramic materials or the like |
| US5523595A (en) * | 1990-08-21 | 1996-06-04 | Ramtron International Corporation | Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film |
| US5902131A (en) * | 1997-05-09 | 1999-05-11 | Ramtron International Corporation | Dual-level metalization method for integrated circuit ferroelectric devices |
| JP2007262766A (en) * | 2006-03-29 | 2007-10-11 | Shimizu Corp | Recharge method and underground water recharge system used for the same |
-
1983
- 1983-11-07 JP JP58207425A patent/JPS60100464A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4888297A (en) * | 1982-09-20 | 1989-12-19 | International Business Machines Corporation | Process for making a contact structure including polysilicon and metal alloys |
| US5523595A (en) * | 1990-08-21 | 1996-06-04 | Ramtron International Corporation | Semiconductor device having a transistor, a ferroelectric capacitor and a hydrogen barrier film |
| US5438023A (en) * | 1994-03-11 | 1995-08-01 | Ramtron International Corporation | Passivation method and structure for a ferroelectric integrated circuit using hard ceramic materials or the like |
| US5578867A (en) * | 1994-03-11 | 1996-11-26 | Ramtron International Corporation | Passivation method and structure using hard ceramic materials or the like |
| US5902131A (en) * | 1997-05-09 | 1999-05-11 | Ramtron International Corporation | Dual-level metalization method for integrated circuit ferroelectric devices |
| JP2007262766A (en) * | 2006-03-29 | 2007-10-11 | Shimizu Corp | Recharge method and underground water recharge system used for the same |
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