JPS60100451A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection and shortcircuit of wirings by removing by dry etching and flattening the unnecessary first wiring layer on an organic film when forming a multilayer wiring structure, thereby obtaining the flat surface of an insulating film in good reproducibility. CONSTITUTION:A PSG film 32 is formed as an insulating film by a CVD method on a semiconductor substrate 31, and with a photoresist film 33 as a patterned organic film as a mask the film 32 is selectively etched. Then, an aluminum film 34 is formed as a wiring layer having substantially the same thickness as the film 32 is formed on the overall surface. Then, a photoresist film 35 is, for example, spin-coated on the overall surface in such a manner to be thick on a recess and thin on the other portion. Subsequently, the films 35, 34 are etched until the unnecessary film 34 is eliminated. The remaining photoresist film 33' and 35' are removed by O2 plasma etching, a PSG film 36 is then formed by a CVD method on the entire surface, thereby obtaining a flat surface state.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device in which an unnecessary Al film on an organic insulating layer is removed by dry etching in a lift-off method.

(Prior Art) As the density of semiconductor devices increases, it becomes necessary to adopt a multilayer wiring structure. Multilayer wiring refers to forming a first wiring on a semiconductor substrate, depositing an insulating film on top of it, and then forming a second wiring, and the insulating film between the wirings must be as flat as possible. is desirable.

FIG. 1 is a cross-sectional view of a multilayer wiring structure formed by a conventional semiconductor device manufacturing method. This is a step 5 on the semiconductor substrate 1.
1st A7 of 000 to 1oooo people! Form wiring 2,
A PSG film having approximately the same thickness as the first AI wiring 2 is deposited as the insulating film 3, and a second A wiring 4 is formed on the entire surface thereof.

If the insulating film 3 is not particularly planarized, the first AA wiring 2
At that point, there is a courier step (when K is a concave indentation).
can be seen. Therefore, the M2Aj' wiring 4 formed thereon also has a significant step difference, similar to the insulating film 3. In this stepped portion 5, there is a risk that the second AJ wiring 4 may become disconnected or short-circuited.

As a method to solve this problem, there is a planarization method called lift-off method. FIG. 2 shows a process diagram of the beam 7-toff method. First of all, as shown in FIG.
ooo A is formed, and the first insulating film 12 is selectively etched using the photosensitive organic film 13 patterned thereon as a mask.

Next, as shown in FIG. 2(b), after forming the Vc first Al wiring 14 on the entire surface, the photosensitive organic film 13 is removed, and the first AJ wiring 14 on the photosensitive organic film 3 is removed. As a result, a flat surface can be obtained as shown in FIG. 2(c).

Therefore, the first insulating film 15 to be formed next is as shown in FIG.
), resulting in a flat film with no steps.

However, in this method, by removing the photosensitive organic coating 13, the first AA wiring 1 on the photosensitive organic coating is removed.
In order to remove 4 and 9, excess material of the first Aj' wiring 14 remains in the removal solution for the photosensitive organic film 13.

For this reason, the etching solution for the photosensitive organic film 13 is contaminated, resulting in a drawback that the etching is not suitable for mass processing.

Further, as another conventional planarization method, there is a planarization method using an etch bag method as shown in FIG.

FIG. 3(a) shows that after forming the first A7 wiring 22 on the semiconductor substrate 21 and forming the PSG film as the first insulating film 23 on the entire surface, the organic material is [2
4 was spin-coated.

Next, dry etching was performed under conditions such that the organic film 24 and the psci had approximately the same etching rate, and as shown in FIG.
) as shown in I) until the S G film appears on the entire surface, and the surface shape of the organic film 24 is
There is a method of transcribing to GM23'.

This method has the disadvantage that etching is stopped midway through the PSG film, making it difficult to detect the end point, and that the thickness of the insulating film changes due to variations in the etching speed within the wafer.

Furthermore, it is difficult to obtain stable planarization due to fluctuations in the etching rate ratio between PSG and the organic film 24, and the surface shape of the organic film 24 depending on the underlying pattern.

(Objective of the Invention) The present invention was made to eliminate the above-mentioned conventional drawbacks, and it is possible to obtain a flat surface of an insulating film with good reproducibility, prevent wiring disconnections and short circuits, and prevent LS'I An object of the present invention is to provide a method for manufacturing a semiconductor device that can achieve high integration, high speed, and high reliability.

(Summary of the Invention) The gist of the present invention is that when forming a multilayer wiring structure, an unnecessary first wiring layer on an organic film is removed by dry etching and flattened.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings.

FIGS. 4(a) to 4(f) are cross-sectional views showing the first embodiment of the present invention in the order of steps. First, as shown in FIG. 4(a), CVD (Chemical
A PSG film 32 of approximately 1M is formed as an insulating film by the calVapor Deposition method, and the PSG #'32 is selectively etched using the patterned organic film 33 as a mask.

Next, as shown in FIG. 4(b), the photorenost film 3
An AI film 34 is formed as a wiring layer with approximately the same thickness as the PSG film 32 on the entire surface, leaving the PSG film 32.

Next, as shown in FIG. 4(c), an organic film, such as a photorenost film 35, is spin-coated over the entire surface so that it is thicker in the recesses and thinner in other parts.

Next, as shown in FIG. 4(d), the photorenost film 35 and the AJ film type 4 are etched until unnecessary AJ film types 4 on the photorenost film 33 are removed. This etching is performed by dry etching.

An appropriate etch rate ratio between the photorenost 35 and the AJ film type 4 is 1:1 to 4. To give an example of an etching method, a parallel plate type device is used, and the etching gas is BG*.
3: CF4 + 5ch Q2 = 4: When carried out at a pressure of about 20 pa with a mixed gas of 1, the etch rate ratio is photorenost: AA! A membrane ratio of approximately 1:3 is suitable for this embodiment.

The end point of this etching is when unnecessary Al film species are no longer present, so the end point can be detected by detecting a decrease in the Al emission intensity at a wavelength of 396-.

After removing the unnecessary AJ film 34, the remaining photoresist films 33' and 35' are removed by 02 plasma etching as shown in FIG. 4(e), and then P is etched by CVD.
By forming the SG film 36 on the entire surface, as shown in FIG.
A flat surface shape as shown in is obtained.

As explained above, in the first embodiment, unlike the conventional lift-off method, unnecessary Al! Since the membrane is left as a solid by tri-etching, there is no problem of contaminating the solution, and there is an advantage that large-scale processing is possible.

In addition, it is not only possible to detect the end point of etching to remove unnecessary AI films, but also because there is an unnecessary photoresist film 33' under the removed AI film.
Even if some overetching is performed, there is no change in flatness, and flattening is achieved with good reproducibility.

Furthermore, according to the above embodiment, the photoresist film coated on the surface of the flat insulating film can be obtained as a uniform film thickness with no unevenness, so this can be applied as a technical means to obtain a mask pattern with uniform thickness. It is possible to do so.

The first example is the AI! shown in FIG. 4(b). In the case where the film 34 is formed completely by the photoresist film 33 with a component force of 1#, the AI film may adhere to the side wall of the resist film 33 depending on the shape of the photoresist film 33 or the method of forming the AII film 34. You may end up doing this. .

In this case, most of the unnecessary Al film 34' can be removed by dry etching, but some may remain on the shoulder of the AJ wiring. This AI is shown in Figure 4(e)
It can be removed by performing a little isotropic etch (wet etch) during the process.

At this time, as shown in FIG.
A groove portion 46 is formed between the J film 43 and the PSG film 4. To fill this space, the insulating film 3 in the first embodiment
Instead of using only the PSG film formed by the CVD method in 6, fill the grooves with a silica film formed by spin coating.
Next, by forming the insulating film 45 in two steps, such as forming PSG #44 by the CVD method, the fifth
A perfectly flat surface can be obtained as shown in the figure.

This method has the advantage that it has almost no effect on the shape of the photoresist film 33 or the state of separation between the wiring portion and the unnecessary portion of the A-no film 34, and that a surface shape with excellent flatness can be obtained.

(Effects of the Invention) As described above, according to the method of manufacturing a semiconductor device of the present invention, when manufacturing a multilayer wiring structure, an insulating film on a semiconductor substrate is patterned using a finely turned organic film, and a semiconductor A first layer wiring layer with the same thickness as this insulating film is embedded on the substrate, and a first layer wiring layer is formed on the organic film, and this layer is dry-etched until unnecessary first layer wiring on the organic film is removed. Since the organic film and the first groove wiring thereon are removed, this unnecessary first layer wiring does not remain as a solid substance, making it easy to process.

In addition, with dry etching, since there is an organic film underlying the first layer wiring to be removed, there is plenty of room for over-etching, and it is possible to flatten the insulating film without the need for particularly technically difficult etching. surface can be obtained with good reproducibility.

As a result, the second layer wiring may be disconnected, and the first layer wiring may
This method not only solves the problem of short circuits in layer wiring, but also has a wide range of utility as a method for forming multilayer wiring in semiconductor devices and as a method for creating highly accurate mask patterns. .

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a multilayer wiring structure according to a conventional method for manufacturing a semiconductor device, FIG. 2 (a) to FIG. (a) and FIG. 3(b) are process explanatory diagrams of another example of the conventional method for manufacturing a semiconductor device, and FIG. 4(a) to FIG. 4(f) are respectively
5 is a process explanatory diagram of one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 5 is a sectional view for explaining another embodiment of the method for manufacturing a semiconductor device according to the present invention. 31.41...Semiconductor substrate, 32,42,44°45
... Insulating film, 33, 33', 35'... Photorenost film, 34.43... AI film. Patent Applicant Oki Electric Industry Co., Ltd. Procedural Amendment June-7, 1980 Kazuo Wakasugi, Commissioner of the Patent Office 1, Indication of Case 1981 Patent Application No. 2075562, Name of Invention Method for Manufacturing Semiconductor Device 3, Amendment Relationship with the case of the person who made the patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order 1925, Month, Day (self-motivated) 6, Detailed description of the invention of BAa shoes subject to amendment Column 7, Contents of amendment 1) ``Exclude 'ft'' on page 3, line 12 of the specification is corrected to ``remove.'' 2) On page 6, line 4, rMJ is corrected to "μ". 3) On page 10, line 4, "1st groove" is corrected to "1st layer."

Claims (1)

[Claims] a step of applying a patterned first photosensitive organic film on the first insulating film formed on the semiconductor substrate and selectively etching the first insulating film using the first photosensitive organic film as a mask; , a step of forming a first wiring layer on the entire surface after this etching, a step of forming a second organic film so as to be thicker in the recessed part and thinner in other parts after the formation of the first wiring layer; a second organic coating and the first organic coating;
After removing the first wiring film on the photosensitive organic film by dry etching, and removing the first Jw-containing organic film and the second organic film, a second wiring film is applied to the entire surface. 1. A method for manufacturing a semiconductor device, comprising the step of forming an insulating film.