JPS60100246A - Address changeover device - Google Patents

Abstract

PURPOSE:To expand a cover area combined with an address by optionally joining/selecting address data by independently shifting input address data in the opposite direction in correspondence to each dimensional group of address data of plural dimensional structure. CONSTITUTION:An address changeover device selects X and Y addresses of each 12 bits from a pattern generator (not shown in a figure) and X and Y addresses from a CPU (not shown in the figure) by multiplexers 10 and 11, shifts said addresses to the upper bit side by a setting signal X shift of an I/O structure at an X address data shifter 12. The device inputs 10 bits of the Y address into a 16 bit Y address data shifter 13, shifts said bit to the upper bit side of the X address, and selects and outputs six bits of overlapped shift of the X and Y addresses by a six bit multiplexer 14 by combination of X and Y address order, thereby expanding the number of combined bits to 24 bits.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is used in IC testing equipment and the like to detect addresses in a multi-dimensional configuration such as X and Y generated from a pattern generator according to the mantle configuration of various devices under test. The present invention relates to an address recombination device that can arbitrarily rearrange addresses into a desired number of addresses.

[Background of the invention]

FIG. 1 is a block diagram of an example of a conventional address recombination device. This address recombination device inputs test) addresses X and Y inputted from a pattern generator into seven address registers 100 and 101, and uses a multiplexer to cope with the capacities and output node configurations of various types of memory under test. 1
02, the above test address X according to the number of used addresses.

Y is rearranged and the defective storage device] - 0 (3 is given as a defective address. 1, the address data on the Y side is other than the one (11] bits used in the multiplexer 102 along with the address on the X side) Remaining address (+
1 bit. In FIG. 1, 1 + 1 = 12 degrees) is used as the selection signal C8 for the memory configuration block of the defective storage device 106, so the shift device 103 adds 7 notes to the multizorexed portion of the Y-side address. Therefore, the remaining address on the Y side is output to the shift device 103, and after being decoded as j by the decoder 104, the AND circuit 105 and stored in the defective storage device 106.

FIG. 2 shows a block diagram of main parts of the address recombination device shown in FIG. 1. X6 to X + 1 of 1 x 6 bits of X side address,
)′ side address]・can 6 bisoto Yo −Ys can be arbitrarily combined, multiplexer] 02A,.

6-bit address data a6 to a-th are output from B and C. The output contents are shown in the explanatory diagram of operation truth values in FIG. As shown in the figure, seven selection output contents P+~])7 are sent out. This covers the range from the input side having the lower 6 bits and the )' side having a total of 12 bits, to the Y side having a total of 12 bits and the Y side having 6 bits at the first position.

- As explained above, the conventional one-address recombination device
As shown in the explanatory diagram of the address recombination principle in Figure 4, the recombination is performed by multiplexing some of the other 6 bits so that at least 6 bits of each test address X and Y remain. It was a way of doing things. According to this method, each j2 on the X and Y sides input from the pattern generator
The bit addresses can be rearranged in seven ways for the gold side 18 pins 1-, which partially overlap the x and Y addresses.

This method has poor expandability in address recombination width, and if the X and Y addresses of the device under test are outside the above seven coverage ranges (hereinafter expressed as 6X/12Y to 12X/6Y), In other words, in the case of IOX/IOY where the total number of bits of the X and Y address is 18 or more, or when using an address of 6X or less or 6Y or less, there are cases where the recombination device cannot deal with it. .

The minimum number of addresses used by IC test equipment is usually:
A device of 6X or more than 6X is sufficient; if a device smaller than 6X is required, an address on one side of the X or Y side can be used instead.

Therefore, in practical use, there was no particular problem as long as a combination of 6XX or 6X or more was possible.

However, as memory capacity increases, the gold side
It is necessary to recombine addresses exceeding 8 bits, and even though the pattern generator can generate 24 bits (maximum 12X/12Y), the recombination device has a low recombination function (for example, 18 bits), so IC test equipment is not suitable. It has become impossible to fully demonstrate its performance.

Therefore, in order to improve the multiplexing function on the l+II long line of the conventional method, for example, the method shown in Figure 4 can be extended to widen the recombination address pixel width and increase the number of bits to be multiplexed in the X and Y addresses. must be reduced. That is, to rearrange the 20-bit address on the gold side, the address to be multiplexed is reduced to 4 bits for both X and Y, and the minimum bit width after switching is BX-? lkoha8
It becomes Y. Furthermore, to obtain a total width of 24 bits, the multiplex address for X and Y is eliminated and direct addresses must be used, so 12
It becomes impossible to rearrange addresses smaller than the address of Y. Therefore, in order to satisfy the minimum 6-bit width recombination and obtain the maximum address (at least 22 pins 1- of 12X10Y) of 12X-12Y, the methods shown in Figure 2 and Figure 4 have limitations. .

[Purpose of the invention]

An object of the present invention is to provide an address recombination device that eliminates the above-mentioned drawbacks of the prior art and can greatly expand the power and range of combinations of multi-dimensional addresses and recombine them into a desired number of addresses. It is in.

[Summary of the invention]

The address recombination device according to the present invention is an address recombination device that recombines address data into a desired number of addresses according to the target object and outputs the address recombination device. An address data mutter that independently shifts the input address data in the opposite direction within the range of the bit width, and arbitrarily combines the output address data from the set of address data of each dimension according to the number of bits used. The system is equipped with a multiplexer for selecting the selected one.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of an embodiment of the address recombination device according to the present invention, FIG. 6 is an explanatory diagram of its operational truth value, and FIG.
8 is an explanatory diagram of the address recombination principle of another embodiment of the address recombination device according to the present invention. FIG. FIG. 3 is an explanatory diagram of the principle of address recombination.

Here, 10.11 is a multiplexer, 12.degree. 13 is an X, X address data 7 lid, 14 is a 6-bit multiplexer, and 15 is an address data buffer.

In FIG. 5, multiplexers 10 and 11 each receive 12 bits from a pattern generator (hereinafter abbreviated as PO).
(Pinto) and the X,
) and CPU mode (CPU). Normally, during a test, the TEST address from the PG is first input and the test result is memorized, then the CP
A CPU address is input which is generated by U or another /...-ware address generator for analysis.

The TEST address signal input from the PG is determined by the capacitance of the device under test (mantle configuration inside the element) and the focus width configuration of its output data, and the number of addresses for each X and Y is up to 121) it ( The memory capacity of the device under test that can be handled is up to 16 Mb (day).

These address data are rearranged to the required number of X and Y addresses depending on the device conditions at the time of testing.
After being rearranged into a series of addresses, the data is transferred from the address data buffer 15 to the defective storage device.

Address data shifters 12, 13 and 6-bit multiplexer 14U: Automatically rearrange these addresses.

The total number of device addresses required for IC test equipment is at least the minimum IQ bit (6X, 4Y; X address is 6 bits, To deal with memory beyond IMbit, IOX/I
It is necessary to switch the 20bth address or higher of OY. The embodiment shown in Fig. 5 and the embodiment shown in Fig. 8 have a minimum of 6X and 4Y.
It is also possible to use up to 22 bits.

Isolation of the defective storage device into the configuration memory is performed by manually inputting the lower side b1t of the X address and using a decoder. At this time, the I10 configuration of the device under test (lbit, 4
If it is a dI10 device, use the lower 4b port of the X address, or if it is a 4i10 configuration, use the 2 bits of the
(1'IJ-fk H11, i + b i d + 1lI-
) input l −+ fZ Then, the X address data is I
The upper blt side of the X address is shifted by the setting signal Xah+tt of the 10 configuration. That is, when 1■10, the shift amount of X is X61. When t is 0.2■10, it is X, h I I is 21.4I10, it is X, bl (
(: When 2.8I10, the x and h-th values are also =3.

Next, the address shift amount ymh1tr on the Y side is the number of X addresses used by the device and the above /ft amount X5hlfL.
Therefore, it can be determined by the following formula.

Yshth t = 12 (Xshift +x)...
・(1) However, X is the number to be tested) ・Represents the number of used addresses of the device's X address, and X≦12.

The address input on the Y side is as shown in FIG.
It inputs 771• to the upper bit side of the X address. (The address shift amount y+h on the Y side of the 1-in formula gives the X, 10Y total 22b1t
t becomes possible. However, Figure 5:
The X address data shifter 13 in the figure is 161)it and 8
Since I am using a shifter, 10X/12'Y
To output 22 bl, the input address of Y is 10 bits.
It is only possible to input by t, so reclassification is not possible. This can be done by constructing the Y address data buffer J3 with a 16-bit input by a longer (at least 2-bit) shifter. However, in a normal case, since the cape structure of the device is large on the X side, it is sufficient to obtain 221+it by rearranging one side. The 6 bits in the overlapping part of the X address shift l- (maximum 6 bits) direction and the X address shift (maximum 31+it) are processed by the 6-bint multiplexer 14 shown in FIG. 5 in the 7 ways shown in FIG. 6! (X like a logical value.

Selective output is performed based on the combination of the order of the X addresses.

The embodiment of FIG. 8 uses the X used in FIG.

This configuration uses the X address shifters 12 and 13 as they are, and allows selection of IOX and 12Y with 22 bat outputs. In other words, the input data 12 of the X address
Similar performance can be achieved by simply using all of the bits and inputting them in the reverse order of the X address in FIG. The address input method in the X direction and the shift amount Xh hth t are completely the same. Soft amount yl in Y direction
The hth is expressed by the following formula % formula % () However, Y represents the number of used addresses of the X address of the device, and Y≦12.

The maximum of the above shift amount ys h I f L is 6X・1
When 2Y, X5hllt"0 is 4 shifts]・sun.

Next, FIG. 9 shows the input bits of the X and X addresses in FIG.
Although the number and the arrangement of the same data are the same, by reducing the number of bits for multiplexing the output data of the XIY address data muffler 12.13 to 4 bits,
The total number of outputs after address rearrangement is 24 bits. Hardware 2: By simply replacing the 6-bit multiplexer 14 in FIG. 5 with a 4-bit multiplexer, the number of addresses to be handled becomes 24b. In this case, y, l,...
l is given by the following equation.

yshlfL == 24 (X+++ index l−X+Y
)'...(3) However, in this configuration, the maximum address that can be rearranged is 24 bits of 12X/12Y, but the minimum address is 8X. However, in this case as well, 6
In order to be able to perform recombination from
bit).

Note that the bit length of the X address data thick 12 is a minimum of 15 bits (X address 121+it+Xgbtft
The maximum number of bits may be 3 bits).

As described above, the total number of combined bits of X and Y addresses, which was conventionally up to 1 sbit, can be expanded to a maximum of 24 b1, resulting in a significant performance improvement.

Although the above embodiment has been described with one address data having a two-dimensional structure of X and Y, the same applies to a multi-dimensional structure of three or more dimensions, and this does not preclude application of the present invention.

〔Effect of the invention〕

Since the coverage range of the combination of X and X addresses can be greatly expanded and rearranged to the desired number of addresses,
Significant effects can be obtained in improving the performance, flexibility, and efficiency of testing equipment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional address recombination device, FIG. 2 is a configuration diagram of its main parts, FIG. 3 is an explanatory diagram of the truth value of the same operation, and FIG. 4 is a diagram of the same operation. An explanatory diagram of the principle, FIG. 5 is a block diagram of an embodiment of the address recombination device according to the present invention, FIG. 6 is an explanatory diagram of its operation truth value, and FIG.
8 is an explanatory diagram of the address recombination principle of another embodiment of the address recombination device according to the present invention, and FIG. 9 is an explanatory diagram of the address recombination principle of another embodiment of the address recombination device according to the present invention. It is an explanatory diagram of the principle. 10.11...Multiplexer, 12...X address data 7 lid, 13...X address data shifter, 1
4...6-bit multiplexer, 15. Address data buffer. Mine 1 圀obscene J [! ] General hAft Fig. 7 0 iR to Xs 7 t = tZ- (Xs #Lrft sentence X) rft to Shachi S

Claims (1)

[Claims] 1. An address recombination device that rearranges and outputs address data into a desired number of addresses according to the phantom object,
Corresponding to each dimension set of multidimensional address data,
An address data shifter that independently shifts the input address data in the opposite direction within the range of the bit width, and an address data shifter that arbitrarily combines the output address data from the set of address data of each dimension according to the number of bits used. An address recombination device characterized in that it is configured to include a multiplexer for selecting. 2. An address recombination device according to claim 1, in which the dimensions of address data are two sets, and the bits of the input address data to each address data shifter are arranged in opposite directions.