JPS5999538U - switch discrimination circuit - Google Patents
switch discrimination circuitInfo
- Publication number
- JPS5999538U JPS5999538U JP19291682U JP19291682U JPS5999538U JP S5999538 U JPS5999538 U JP S5999538U JP 19291682 U JP19291682 U JP 19291682U JP 19291682 U JP19291682 U JP 19291682U JP S5999538 U JPS5999538 U JP S5999538U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- circuit
- discrimination circuit
- switch discrimination
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のスイッチ弁別回路図、第２図は本考案の
スイッチ弁別回路の実施例のブロック図、第３図は第２
図の回路詳細図である。
１・・・スイッチ（又はリレー接点）、２・・・スイッ
チ（又はリレー接点）、３・・・サージ吸収回路、４・
・・波形整形回路、５．１４・・・フリップフロップ回
路、６．１３・・・マルチプレクサ回路、７・・・カウ
ンタ回路、８・・・カウンタ出力信号、９．１０・・・
スイッチ弁別信号。FIG. 1 is a conventional switch discrimination circuit diagram, FIG. 2 is a block diagram of an embodiment of the switch discrimination circuit of the present invention, and FIG.
FIG. 3 is a detailed diagram of the circuit shown in FIG. 1... Switch (or relay contact), 2... Switch (or relay contact), 3... Surge absorption circuit, 4...
... Waveform shaping circuit, 5.14... Flip-flop circuit, 6.13... Multiplexer circuit, 7... Counter circuit, 8... Counter output signal, 9.10...
Switch discrimination signal.
Claims (1)
すスイッチ弁別回路に於いて、入力信号線に誘導される
外乱ノイズ、及びスイッチのチャタリングを防止する為
に、サージ吸収回路、波形整形回路、フリップフロップ
回路を設け、更に、人間の操作ミスに依る、誤信号と正
規の信号を判別するマルチプレクサ回路を前記の後段に
設けたことを特徴とするスイッチ弁別回路。In a switch discrimination circuit that extracts only a single input from multiple switch input signals, surge absorption circuits, waveform shaping circuits, and flip-flops are used to prevent disturbance noise induced in the input signal line and switch chattering. 1. A switch discrimination circuit, further comprising a multiplexer circuit disposed at a subsequent stage of the circuit for discriminating between an erroneous signal caused by a human operation error and a normal signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19291682U JPS5999538U (en) | 1982-12-22 | 1982-12-22 | switch discrimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19291682U JPS5999538U (en) | 1982-12-22 | 1982-12-22 | switch discrimination circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999538U true JPS5999538U (en) | 1984-07-05 |
Family
ID=30415043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19291682U Pending JPS5999538U (en) | 1982-12-22 | 1982-12-22 | switch discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999538U (en) |
-
1982
- 1982-12-22 JP JP19291682U patent/JPS5999538U/en active Pending
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