JPS599935A - Manufacture of probe card - Google Patents

Manufacture of probe card

Info

Publication number
JPS599935A
JPS599935A JP11893982A JP11893982A JPS599935A JP S599935 A JPS599935 A JP S599935A JP 11893982 A JP11893982 A JP 11893982A JP 11893982 A JP11893982 A JP 11893982A JP S599935 A JPS599935 A JP S599935A
Authority
JP
Japan
Prior art keywords
contactors
elastic body
wafer
contact
sections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11893982A
Other languages
Japanese (ja)
Other versions
JPS6159530B2 (en
Inventor
Masao Okubo
昌男 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Electronic Materials Corp
Original Assignee
Japan Electronic Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Electronic Materials Corp filed Critical Japan Electronic Materials Corp
Priority to JP11893982A priority Critical patent/JPS599935A/en
Publication of JPS599935A publication Critical patent/JPS599935A/en
Publication of JPS6159530B2 publication Critical patent/JPS6159530B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To prevent the generation of displacement among contactors by forming the contactors at wafer terminals, connecting lead wires to the contactors, molding the contactors with an elastic body, and fixing the elastic body to a board. CONSTITUTION:A photo-resist 2 is applied to a copper substrate 1, the terminal patterns 3 of a wafer to be treated are baked, and developed, and the photo- resist of the terminal pattern sections is removed. Gold is attached to the sections of the pattern sections 3 and the contactors 4 to wafer terminals are formed, the resist 2 remaining in sections except the pattern sections 3 is removed, and the lead wires 5 are welded to the contactors 4. A frame 6 is assembled around the contactors 4, the contactors 4 are molded with the elastic body 7, a reinforcing plate 8 is formed onto the elastic body, and the frame 6 is removed. The reinforcing plate 8 is fixed to a glass epoxy resin board 9. According to said manufacture, the contactors 4 are obtained through a predetermined photographic baking process, and displacement is not generated among the contactors 4.

Description

【発明の詳細な説明】 本発明は半導体ウェファ−のテストに用いるプローブカ
ードの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a probe card used for testing semiconductor wafers.

中心部に顕微鏡による観察のための穴を有する絶縁基板
に、その穴を取り囲んで放射状に探針を配設した従来形
式のプローブカードは、その製造ニ当りって、上記の穴
から、その下に置かれたテストすべき半導体ウェファ−
の端子、または、端子の配列位置を画いた図形を観察し
ながら、探針の先端がウェファ−の端子の配列位置に一
致するよう、各探針の位Wa整を行う必要がある。この
作業は、特に最近、ウェファ−の端子数が増大するにお
よんで、まずます長時間を要する複雑な作業となりつつ
あるだけでなく、このような方法で製造されたプローブ
カードは、取り扱い上の僅かな不注意により探針の位置
が変わり、探針位置の再調整を要するなどの欠点がある
Conventional probe cards have an insulating substrate with a hole in the center for microscopic observation, and probes are arranged radially around the hole. Semiconductor wafer to be tested placed on
It is necessary to adjust the position of each probe so that the tip of the probe coincides with the arrangement position of the terminals on the wafer while observing a diagram depicting the terminals or the arrangement position of the terminals. Not only is this process becoming increasingly time-consuming and complex, especially as the number of terminals on wafers increases, but probe cards manufactured using this method are also difficult to handle. There is a drawback that the position of the probe changes due to slight carelessness, requiring readjustment of the probe position.

本発明は、以上のような欠点を取り除き、ウェファ−の
端子数や、端子配列パターンの複雑性に関係なく一定の
作業工程で、ウェファ一端子への接触片間の相対的位置
関係がずれることのない、しかも、端子がハンプ型であ
っても接触子に滑りを生じない、プローブカードの製造
方法を提供することを目的としている。
The present invention eliminates the above-mentioned drawbacks, and eliminates the possibility that the relative positional relationship between the contact pieces for one wafer terminal deviates during a certain work process, regardless of the number of terminals on the wafer or the complexity of the terminal arrangement pattern. It is an object of the present invention to provide a method for manufacturing a probe card that does not cause slippage of the contacts even if the terminals are hump-shaped.

以上の目的のために本発明は、フォトレジストを塗布し
た基板上にテストすべき半導体ウェファ−の端子パター
ンを焼き付けた後、端子パターン部のフォトレジストを
除去してそこに所定の厚さに金属を付着させてウェファ
一端子への接触子を形成する工程と、接触子にリード線
を電気接続する工程と、上記リード線を外部に引き出し
た状態で上記接触子を弾性体でモールドする工程と、弾
性体による接触子のモールド後、上記基板を除去する工
程と、上記接触子をモールドした上記弾性体を所定の強
度を有する板に固着する工程とから成っている。
For the above purpose, the present invention involves baking a terminal pattern of a semiconductor wafer to be tested on a substrate coated with photoresist, then removing the photoresist in the terminal pattern area and applying metal to the predetermined thickness. a step of forming a contact to one terminal of the wafer by attaching it to the wafer, a step of electrically connecting a lead wire to the contact, and a step of molding the contact with an elastic body with the lead wire pulled out to the outside. , after molding the contact with the elastic body, the method comprises the steps of removing the substrate, and fixing the elastic body on which the contact has been molded to a plate having a predetermined strength.

以下に本発明の実施例を図面に基づいて説明する。Embodiments of the present invention will be described below based on the drawings.

まず、第1図に示すように、厚さ0.2闘の銅の基板1
、感光した部分が現像液に熔解するフォトレジスト2と
して例えばコダソク社のマイクロレジスト752を塗り
、それにテストすべき半導体ウェファ−の端子パターン
3を焼付けた後、現像して端子パターン部のフォトレジ
ストを除去する。
First, as shown in Figure 1, a copper substrate 1 with a thickness of 0.2
For example, Microresist 752 manufactured by Kodasoku Co., Ltd. is applied as the photoresist 2 whose exposed areas dissolve in a developing solution, and after the terminal pattern 3 of the semiconductor wafer to be tested is printed on it, it is developed to remove the photoresist in the terminal pattern area. Remove.

この場合の焼付けは、端子パターン以外の部分を感光さ
せるように行う。第2図はこの段階における銅基板上の
フォトレジストの付着状態を、第1図のラインLに沿っ
た断面について示している。
In this case, the baking is performed in such a way that parts other than the terminal pattern are exposed to light. FIG. 2 shows the state of adhesion of the photoresist on the copper substrate at this stage in a cross section taken along line L in FIG.

次に、端子バクーンを有する側から銅基板1に金の電気
メンキをほどこし、第3図に示すように、端子パターン
部3の所に金4を0.01〜0.005mの厚さに付着
させてウェファ一端子への接触子4を形成した後、第4
図に示すように端子パターン部以外の部分に残留するフ
ォトレジスト2を溶剤、例えばコダソク社のマイクロレ
ジスト除去液を用いて熔解除去し、接触子4にリード線
5を爆接する。その後、接触子4のまわりに枠6を組み
立て、リード線5を外部に引き出した状態で枠6の中へ
ゴムを流し込んで固化させ、接触子を弾性体7でモール
ドし、続いてその上にエポキシ樹脂を流し込んで補強板
8を固化形成し、その後で枠6を取りはずす(第6図)
。次に接触子の接触面が充分に露出する程度に、四塩化
炭素に弾性体をエツチングする。これを第7図に示すよ
うにガラスエポキシ樹脂板9に固着して、本発明の製造
方法によるプローブカードが得られる。
Next, apply gold electroplating to the copper substrate 1 from the side with the terminal backing, and as shown in FIG. After forming the contact 4 to the wafer one terminal, the fourth
As shown in the figure, the photoresist 2 remaining in the area other than the terminal pattern portion is melted and removed using a solvent, for example, a microresist removal solution manufactured by Kodasoku Co., Ltd., and the lead wire 5 is explosively connected to the contact 4. Thereafter, a frame 6 is assembled around the contact 4, and with the lead wire 5 pulled out, rubber is poured into the frame 6 and solidified, the contact is molded with an elastic body 7, and then Pour epoxy resin and solidify the reinforcing plate 8, then remove the frame 6 (Figure 6)
. Next, the elastic body is etched in carbon tetrachloride to the extent that the contact surface of the contact is sufficiently exposed. This is fixed to a glass epoxy resin plate 9 as shown in FIG. 7 to obtain a probe card according to the manufacturing method of the present invention.

以上のように、本発明によれば、テストすべきウェファ
−の端子への接触子が、端子の数や配列パターンの複雑
性に関係なく、一定の写真焼付工程を通して得られ、接
触子相互間にずれを生ずることもない。また、本発明に
基づく方法で製造されたプローブカードを用いれば、ウ
ェファ−のテストに当たっての、接触子とシェフ1一端
子との間の位置整合に際しても、ウェファ−とプローブ
カードの2次元的位置関係を一度決定しておけばよく、
従来のプローブカードの場合のように、顕微鏡により探
針とウェファ一端子間の接触を、各探針毎に監視、調整
する必要がない。
As described above, according to the present invention, the contacts to the terminals of the wafer to be tested can be obtained through a certain photoprinting process regardless of the number of terminals or the complexity of the arrangement pattern, and the contacts between the contacts can be No deviation occurs. Furthermore, if the probe card manufactured by the method based on the present invention is used, the two-dimensional position of the wafer and the probe card can be adjusted even when positioning the contacts and the terminals of the chef 1 during wafer testing. All you have to do is decide on the relationship once,
There is no need to monitor and adjust the contact between the probe and the wafer terminal for each probe using a microscope, as is the case with conventional probe cards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例において、半導体ウェファ−の端
子の配列を銅基板上のフォトレジストに焼き付けた状態
を示す図である。第2図は第1図に示した基板上のフォ
トレジストに現像を行った状態を示す断面図、第3図は
第2図に示す現像された端子パターンに、ウェファ一端
子への接触子となる金属を付着させた状態を示す図、第
4図は接触子にリード線を接続すると共に、銅基板上の
残留フォトレジストを除去した状態を示す図である。第
5図は接触子を弾性体でモールドし補強板を設ける過程
を説明するための図である。第6図は弾性体でモールド
され、補強板が設けられた接触子のユニットの断面を示
す。第7Fgは本実施例により製造されたプローブカー
ドの断面を示す図である。 ■・・・銅基板、     2・・・フォトレジスト、
3・・・端子パターン、 4・・・接触子、5・・・リ
ード線、    6・・・枠、7・・・弾性体、   
 8・・・補強板、9・・・ガラスエポキシ樹脂。 特許出願人  日本電子材料株式会社 代 理 人  弁理士  西1) 新 手続補正書 (yi却 昭和57年 特許願  第118939号2、発明の名
称 プローブカードの製造方法 代表者 大久保昌男 4、代理人 住所  大阪市北区兎我野町15番13号5、補正命令
の日付 昭和57年10月26日 (発送日)159−
FIG. 1 is a diagram showing a state in which the terminal arrangement of a semiconductor wafer is printed onto a photoresist on a copper substrate in an embodiment of the present invention. Figure 2 is a cross-sectional view showing the developed state of the photoresist on the substrate shown in Figure 1, and Figure 3 is a cross-sectional view showing the developed terminal pattern shown in Figure 2 with a contact for one terminal on the wafer. FIG. 4 shows a state in which lead wires are connected to the contacts and the remaining photoresist on the copper substrate is removed. FIG. 5 is a diagram for explaining the process of molding the contact with an elastic body and providing a reinforcing plate. FIG. 6 shows a cross section of a contact unit molded with an elastic body and provided with a reinforcing plate. 7Fg is a diagram showing a cross section of the probe card manufactured according to this example. ■...Copper substrate, 2...Photoresist,
3...Terminal pattern, 4...Contact, 5...Lead wire, 6...Frame, 7...Elastic body,
8... Reinforcement plate, 9... Glass epoxy resin. Patent applicant: Nippon Electronic Materials Co., Ltd. Agent: Patent attorney: Nishi 1) New procedural amendment (Yi dismissed in 1982 Patent Application No. 118939 2, Name of invention: Probe card manufacturing method Representative: Masao Okubo 4, Agent address: 15-13-5 Usagano-cho, Kita-ku, Osaka City, Date of amendment order: October 26, 1981 (Shipping date) 159-

Claims (1)

【特許請求の範囲】[Claims] フォトレジストを塗布した基板上にテストすべき半導体
ウェファ−の端子パターンを写真焼付した後、上記端子
パターンのフォトレジストを除去してその部分に上記基
板の表面を露出させ、そこへ所定の厚さに金属を何着さ
せて上記半導体ウェファ−の端子への接触子を形成し、
上記接触子にリード線を電気接続した上、上記リード線
を外部に引き出した状態で上記接触子を弾性体でモール
ドすると共に上記基板を除去し、上記接触子をモールド
した上記弾性体を所定の強度を有する板に固着させるこ
とによりプローブカードを形成するプローブカードの製
造方法。
After photo-printing a terminal pattern of a semiconductor wafer to be tested on a substrate coated with photoresist, the photoresist of the terminal pattern is removed to expose the surface of the substrate in that area, and a predetermined thickness is applied thereto. How many metals are applied to the semiconductor wafer to form contacts to the terminals of the semiconductor wafer?
After a lead wire is electrically connected to the contact, the contact is molded with an elastic body with the lead wire pulled out, and the substrate is removed. A method for manufacturing a probe card, in which the probe card is formed by fixing it to a plate having strength.
JP11893982A 1982-07-07 1982-07-07 Manufacture of probe card Granted JPS599935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11893982A JPS599935A (en) 1982-07-07 1982-07-07 Manufacture of probe card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11893982A JPS599935A (en) 1982-07-07 1982-07-07 Manufacture of probe card

Publications (2)

Publication Number Publication Date
JPS599935A true JPS599935A (en) 1984-01-19
JPS6159530B2 JPS6159530B2 (en) 1986-12-17

Family

ID=14748965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11893982A Granted JPS599935A (en) 1982-07-07 1982-07-07 Manufacture of probe card

Country Status (1)

Country Link
JP (1) JPS599935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0921401A1 (en) * 1996-06-28 1999-06-09 Shin-Etsu Polymer Co., Ltd. Probe and method for inspection of electronic circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0921401A1 (en) * 1996-06-28 1999-06-09 Shin-Etsu Polymer Co., Ltd. Probe and method for inspection of electronic circuit board

Also Published As

Publication number Publication date
JPS6159530B2 (en) 1986-12-17

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