JPS5998364A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To write a program by a read-out exclusive memory (P-ROM) write device, and to hold its contents by writing a program by the P-ROM write device, and also providing a backup power source. CONSTITUTION:The first and the second changeover switches 9, 11 are switched to a program side, and are installed to a socket of a P-ROM write device. Subsequently, when a signal is applied to the socket 1, a signal of an ''L'', level is applied to <=CE2 of an RAM2. Also, an output of the first invertor 7 is provided to R/W of the RAM2. Also, an output of the second AND gate 10 becomes ''L'', and an output of the third AND gate 14 also becomes ''L''. Accordingly, a data can be written in the RAM2. In this state, even if a memory device is removed from the P-ROM write device, the contents of the RAM2 are held by a backup power source 5. In this way, it is possible to write a program and to hold its contents.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that can be written under the same conditions as a read-only memory (P-ROM).

[Technical background of the invention]

Conventionally, when developing a program using, for example, a microcomputer, the following steps (1) to (6) are sequentially performed.

(1) Creating a flowchart (2) Coding in assembler language (3) Translating assembler language into machine word (4) Loading the developed machine word program into the memory of the target tossle microcomputer (5) Executing the program (6) )-1' program debugging, and then steps (5) and (6>) are repeated alternately to complete the program.

[Problems with background technology]

By the way, in steps (4), (5), and (6) above, the method of executing the program in the memory of the target microcomputer is as follows: - Write the mother program to the P-ROM and then execute the program in the target microcomputer's memory. There is a method that is implemented in the P-ROM and is executed on the read/write memory (RAM) after transferring the contents of the P-ROM to the RAM. However, in such a device, when modifying the contents of the P-ROM, it is necessary to perform erasing with an eraser and then rewrite, which is extremely troublesome.

Furthermore, it is necessary to provide the P-ROM and RAM in duplicate, which requires a duplicate memory area, which is not rational.

In addition, as a method that does not use P-ROM, the target microcomputer's RA can be accessed via an appropriate interface.
There is also one that transfers 7″ quadrature directly to M from the outside.

After depacking the program in RAM,
The completed program is written to P-ROM and implemented.

However, such a device requires an interface for transferring data from the outside to the target microcomputer, resulting in high cost.

Furthermore, it is also possible to use an emirator as another method. If such an emitter is used, the extra R
AM is not required and there is no need for an interface, but
The disadvantage is that the emulator device itself is expensive.

[Purpose of the invention]

The present invention has been made in view of the above circumstances.
It is an object of the present invention to provide a semiconductor memory device in which a program can be arbitrarily written using a writer and the contents can be retained.

[Summary of the invention]

That is, the present invention has mechanically and electrically equal connections to the P-ROM and a P-ROM writer (P-ROM).
It is characterized in that a program can be written in using the same method as a P-ROM using a P-ROM (M writer), and that it has a pack power supply for retaining the contents.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the circuit diagram shown in FIG. Note that in this embodiment, P-ROMTM
M323 D (model name, Tokyo Shibaura Electric Co., Ltd.) 0M
The replacement with O8 type RAM TC5s 16 (model name, Tokyo Shibaura Electric Co., Ltd.) will be explained.

In FIG. 1, a socket 1 has a structure mechanically equivalent to each pin of the P-ROM. And 2 is 0M above
It is an O8 type RAM. Each data pin DATA o to DATA of the socket is connected to each data bin DATA o NDATA 7 of the RAM 2 . Also, each address pin of socket 1 ADD oNADD
1. Each address pin ADD of RAM 2.

~ Connected to ADD1o. and Vc of socket 1
Connect the c pin (No. 24) to RA through diode 3 in the forward direction.
It is connected to vDD of M2, and a backup power source 5 is connected to this vDD via a diode 4 in the forward direction. The CS pin (No. 20) of the socket 1 is connected to one input of the first AND dart 6, the first inverter 7, and one input of the EX-OR dart 8, respectively. -The VP pin (No. 21) of the socket 1 is connected to the read-side fixed contact of the first read/program selector switch 9. The output of the first inverter 7 is connected to the program side fixed contact of the changeover switch 9. Then, move the movable contact of this changeover switch 9 to R.
It is connected to R,'v (No. 21) of AM 2. Then, the PRG bin (No. 18) of pin 1 is applied to the other input of EX-ORB and one input of the second AND dart 10. And the second series - program changeover switch 11
The program side fixed contact of is connected to the reference potential, the read side fixed contact is connected to vDD of RAM 2, and the movable contact is connected to Ml through the resistor 12, and the second AND dart 6.10
and one input of the third AND r − ) J 4 via the second inverter 13 .

Then, the VCA pin (No. 24) of the socket 1 is applied to one input of the first OR gate 16 via the third inverter 15, and the output of the first melon dart 6 is applied to the other input of this OR gate 16. give.

Then, the output of this first OR gate 16 is stored in the C of RAM2.
Give to E2. In addition, vDD and CE of RAM 2,? A resistor 17 is inserted between the two. and the second ANDr
- The output of the gate 10 is applied to one input of the second 0Rr-gate 1B. Then, the output of EX-OR gate 8 is sent to the third AN
This third palm dart 1 is given to the other input of the D dart 14.
The output of 4 is applied to the other input of the second 0RP-to-1B.

Then, the output of the second 0R) f-to 1B is transferred to the C of RAM2.
I try to give it to EJ (No. 18).

FIG. 2 is a perspective view showing the assembled state of the circuit shown in FIG. 1, in which the pins of the socket 1 are extended and attached to a board 19, and this board 19 has a RAM 2, a backup power source 5, a changeover switch 9, 11. Integrated circuit elements 20 constituting each dirt circuit and inverter circuit are installed.

With such a configuration, each signal is applied as shown in FIG. 3 when writing to the P-ROM.

In other words, after address data Add is given, CS goes to "H" and PGM goes to "H" for a certain period of time.
25V is applied to pp.

Then, the data D1N given while the PGM is at the ``H'' level is written.

On the other hand, FIG. 4 shows each signal during writing to C-MOS RAM. After address data Add is applied, R2
〆Specify writing by setting W to L'. Then, while CE2 is held at "L", data DIN for the period when CEI becomes 6L" is written.

Therefore, if command writing is to be performed, the first and second changeover switches 9 and 1 of the semiconductor memory device shown in FIG.
1 to the program side and insert it into the socket of the P-ROM writer. and the third to socket 1 of the memory device.
When a signal as shown in the figure is given, during the period when PGM is "H", the surface input of the first AND dart becomes "L#" and the first
The OR dart surface input is also “L- and #) CE of RAM2
The input of the first inverter 7 is 'H' and its output 'L# is applied to the first inverter 2.
The data is applied to the R/W of the RAM 2 via the changeover switch 9. Furthermore, the input of the second AND dart 10 is 'L#''H
At ``'', the output becomes ``L''. Also, the surface input of the EX-OR dart 8 is "H#" and the multiple output is I L'.Therefore, the input of the third ΔDr-to 14 is IH#"'L"
Therefore, the output is 'L'.The surface input of the second OR dart 18 is L#, so the output 'L' is stored in the RAM.
Give to CEI of 2. In other words, RAM 2's CE2 becomes 1L", R/W becomes L", and cEl becomes @L", so data DIN can be written to RAM 2. In this state, the memory device is removed from the P-ROM writer. Even if the pRAM z is removed, the contents of the pRAM z are retained by the backup power supply 5.

Then, this memory device is attached to the ROM socket of the target microcomputer. and selector switch 9
, 11 to the read side, RAM 2 (7)
CE x He is L”, 87w is JP.

'L1 is given to each CEI so that programmed contents can be read out. Therefore, by programming with the P-ROM writer and then executing with the target microcomputer, and repeating this process alternately, the shiveback operation can be performed efficiently in a short time. After completing the real-time depacking using the memory device, it is loaded into the P-ROM writer again and the contents are read.
A P-ROM may be installed here and a program written therein.

That is, the connector 1, which is the connection end to the outside, has a mechanism mechanically equivalent to a P-ROM, and the connector 1
The logic circuit inserted between the RAM 2 and the 0MO8W RAM 2 makes it electrically equivalent to a P-ROM.

〔Effect of the invention〕

As described above, according to the present invention, since the 0MO8 type RAM is mechanically and electrically equivalent to the P-ROM, it is possible to provide a semiconductor memory device that can efficiently debug programs in a short time. .

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a perspective view showing the external appearance of the above embodiment, Fig. 3 is a time chart showing the write timing of P-ROM, and Fig. 4 is 0M.
3 is a time chart showing read timing of an O8 type RAM. 1... Connector, 2... 0MO8 type RAM,
5...Backup power supply, 6,10.14...
AND dart, 16, 18...OR dart, 8...
EX-OR Dart, 7, 13.15...Inverter. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Vpp 21pin 25V, Dc Figure 4

Claims (1)

[Claims] A connector mechanically equivalent to a read-only memory, a 0MO8 type read/write memory connected to this connector,
By using a logic circuit inserted between the connector and the 0MO8 type read/write memory and switching to the program side, the 0MO8 type read/write memory is electrically equivalent to a read-only memory during writing at the connector. a read/program changeover switch for controlling the logic circuit so as to electrically equivalently switch the 0MO8 type read/write memory into a read-only memory at the time of reading at the connector by switching and switching to the read side; A semiconductor memory device comprising a backup power supply that supplies power to memory.