JPS5996768A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to satisfy three parameters for speed-up at the same time by providing a source-drain region of a semiconductor substrate with three or more different diffusion depths. CONSTITUTION:After forming an isolation oxide film 12 and a thermal oxide film 13 on the p type Si substrate 11, a gate oxide film 14 and a gate poly Si 15 of an MOS transistor are formed thereon, and the n-source-drain region 16 are formed over the entire surface of the p type Si substrate 11 after forming the gate poly Si 15. Next, a resist film is left only at a region to be desired to form the n-source-drain region, and As is implanted, thus forming the n<+> source- drain region 17 of deeper diffusion depth than that those of the n-source-drain region 16 are formed. The thermal oxide film 13 on the p type Si substrate 11 is locally removed, and a CVD oxide film 18 doped with phosphorus is adhered thereon. At this time, the phosphorus is diffused into the p type Si substrate 11 much more than at the part wherefrom the thermal oxide film 13 is removed, and thus an n<++> region 19 is formed. Then, contact holes are bored through the CVD oxide film 18, and a diffused region 20 of deep xj by diffusing phosphorus through the bored holes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device used in an MO8 type integrated circuit.

[Prior art]

In recent years, the technological development of MO8 type memory has made great progress.
Currently, research and development is progressing on the dynamic MO8RAM for the 256 and the static MO8RAM for the 64.

Although the technological development of such large-capacity memory is extremely effective due to miniaturization of waveforms, device technology is also extremely important. In particular, in order to realize a high-speed dynamic MO8RAM, the development of device technology is essential, and various studies are being carried out.

Generally, in order to realize a high-speed dynamic MO8RAM, there are three important parameters shown below. That is, (1) Prevention of signal delay due to parasitic resistance between the source/drain region and a part of the cross-under of the signal line.

(2) Improved conductance by shortening the gate length.

(3) Gate capacitance, stray capacitance by reducing the overlapping capacitance between the gate and source/drain.

Reduced mirror capacity.

There is. In order to realize a high-speed MOS dynamic RAM, devices are required to reduce and improve these three parameters. That is, the above (
Item 1) is a problem in which a large parasitic CR time constant appears when contacts cannot be provided in the source/drain region and shunting cannot be achieved with At wiring. Dynamic M is a big problem when you need to drive current.
This causes margin failure in O8RAM. Also,
As is well known, the above item (2) is based on improving the performance of MOS transistors, and the premise is to shorten the channel length of the gate. However, short channel MOS
A transistor has a breakdown voltage between source and drain.

Since this causes a decrease in skirt current and threshold voltage, improvement thereof is also required. In addition, since dynamic 11/[O8RAM uses a gate strap circuit, an electric field higher than the power supply voltage is applied, and a drop in base current and threshold voltage to dynamically hold memory cells and peripheral circuits is fatal. Since this is a drawback, a device that does not cause short channel effects and can achieve high conductance is required. Furthermore, the above item (3) is a reduction in the load capacitance of the basic circuit and a reduction in Miller capacitance. When analyzing the capacity of a dynamic MO8RAM, approximately 54 times the capacity is the gate capacity.

That is, it is approximately 1/2 of the total capacity. If this capacitance can be reduced, the load capacitance can be reduced and it is advantageous for speeding up.

In addition, the large amount of overlapping capacitance between the gate and the source/drain acts as a mirror capacitance, which is a major hindrance to speeding up, and it is necessary to reduce this capacitance in order to speed up.

FIGS. 1A and 1B are cross-sectional views of a conventional MOS transistor section and a part of its cross under. The process claw of the MOS transistor constructed in this way is as shown below. That is, 1 (a) An isolation oxide film (2) is placed on a p-type silicon substrate (1).
), a thermal oxide film (3) is formed on the silicon substrate (1) and a gate oxide film (4) and a gate polysilicon (MOS) are formed on the silicon substrate (1).
5) to form.

(e) After forming gate polysilicon (5), n+ source/drain regions (6) are formed on p-type silicon substrate (1).
form. This region (6) becomes a parasitic resistance of the source/drain, so it is necessary to reduce the resistance.

(d) A C1VD oxide film (7) is formed on the isolation oxide film (2) and the gate oxide film (4), and a contact is made to connect the n+ source/drain region (6) to the At wiring described later. A hole is drilled and P (phosphorus) is diffused through the hole to form a deep diffusion region (8) with a diffusion depth xj.

(e) CVD oxide film (Att wiring (9) is performed on the sumo wrestler to perform internal wiring on the chip.

Also, although Figure (b) shows a part of the cross under, this manufacturing process is the same as that shown in Figure (,).
``N+ source/drain regions (6) are provided below the signal lines (9a) and (9b) to short-circuit the At lines (9).

However, in the conventional MOS transistor having the above structure, it is extremely difficult to satisfy the three parameters for increasing speed. That is, in order to lower the diffusion resistance of the n+ source/drain region (6), the amount of As ions implanted to form the n+ region by increasing the diffusion depth xj of the n+ source/drain region (6) is increased. need to do more. For example, if 6×105/c4 is implanted, a sheet resistance of about 25Ω/hole can be obtained, but xj
If it is 0.45 μm, there is a large amount of overlapping capacitance between the gate and the source/drain, which impedes speeding up and also increases the gate capacitance itself, which is not desirable for speeding up.

However, the cross-under resistance of the n+ diffusion layer of the peripheral circuit can be made to be about 250/unit, which lowers the wiring resistance, but it is not sufficient for increasing the speed. On the other hand, the gate capacitance, Ge′
If a method is adopted in which the overlapping capacitance between the gate and the source/drain is reduced, it is necessary to make Xj of the n-diffusion layer shallow, which increases the parasitic resistance, and is therefore not suitable for increasing speed. As described above, in the conventional structure, there is a contradiction in satisfying the three parameters for increasing speed, and therefore, it is impossible to satisfy these three parameters at the same time.

[Summary of the invention]

Therefore, the present invention was made with the aim of improving the above-mentioned drawbacks, and by providing at least three different diffusion depths in the source/drain regions of a semiconductor substrate, three parameters for increasing speed can be simultaneously satisfied. The objective is to provide a semiconductor device that can

[Embodiments of the invention]

FIG. 2 is a diagram showing an actual example of a semiconductor device according to the present invention, and FIG. 2(a) is a cross-sectional view of a MOS transistor part;
FIG. 5B is a cross-sectional view of a part of the cross under. In these figures, MOS transistors are formed by the following process. That is, (a) the isolation oxide films α and the thermal oxide film (13) are formed on the p-type silicon substrate aII.

(b) A gate oxide film α4) and a gate polysilicon 0ω of a MOS transistor are formed on a PW silicon substrate aυ.

(c) After forming the gate polysilicon layer 9, an n-tooth drain region (161) is formed on the entire surface of the p-type silicon substrate aυ. In this case, this region (16) is the gate capacitance, and It is possible to reduce large volumes.

(d) Leave the resist film only in the regions where you want to form the n source/drain regions, and implant As into the n source/drain regions.
An n+ source/drain region (17) having a deeper diffusion depth than the drain region (L6) is formed.

In this case, this region (l'O) reduces the source/drain parasitic resistance and also reduces the cross-under resistance.

(e) Thermal oxide film (131
is locally removed and P (phosphorus) is doped thereon.
Wave-deposit VD oxide film. At this time, a thermal oxide film (13
) is diffused into the p-type silicon substrate av from the removed portion to form an n,100 region. In this case, the cross-under resistance is reduced in the nth region a9.

(f) In order to connect the n10 region α9 with the At wiring described later, a contact hole is formed in the CvD oxide film α~, and P (phosphorus) is diffused through this hole to form a deep diffusion region of Xj. form. And At wiring CI! 1)
, (21m), and (21b) are performed to wire the inside of the chip. In this case 1. The XJ of this diffusion region (a) is approximately 1.3 μm.

The MOS transistor configured in this manner can satisfy all three important parameters for speeding up described above. That is, the n source/drain region←Q formed by shallow diffusion can reduce the overlapping large capacitance between the gate and the source/drain, and when obtaining the same Lef f, the gate capacitance can also be made smaller than in the conventional case. However, care must be taken because the sheet resistance of this shallow diffusion layer in the n source/drain region becomes high. In other words, this n source
When the resistance of the drain region Q6) increases, the conductance of the MOS transistor decreases. Therefore, the resistance of the diffusion layer is less than 1000/unit, that is, about 1X
If the amount of As implanted is 1015/, -d, this decrease in conductance will not be a problem. At this time, XJ is approximately 0
．． It is 2 μm. In addition, the n+ source/drain region (l
Since η is infinite considering the depth of Xj, it is possible to achieve a sufficiently low resistance. For example, a 6.times.10@15/- As implant provides a sheet resistance of about 25 .OMEGA./hole. However, the amount of As to be implanted must be selected with due care to junction leakage, etc. On the other hand, the n++ region dispersion layer used only in a part of the cross-under uses Pln as a diffusion source. When xi and xi = about 2.3 μm, the sheet resistance can be set to 15 to 20 Ω/port, and the parasitic resistance of the signal line can be sufficiently reduced, making it easy to increase the speed.

According to such a configuration, all three important parameters required for high speed can be fully satisfied, so it is possible to realize a MO8I-transistor suitable for high speed dynamic.

In the above-mentioned embodiments, the case where the present invention is applied to an N-channel MOS transistor has been described, but it goes without saying that the same effect can be obtained when applied to a P-channel MOS transistor. In addition, the n+
Although the case where the tensile region 9) is formed of P (phosphorus) has been described, it is of course possible to implant this region with As or to further reduce the resistance.

As described above, the present invention is characterized in that three or more diffusion regions with different diffusion depths are formed in one semiconductor device, and the structure has a large number of overlapping capacitances between the gate and the source/drain. An n diffusion layer that reduces gate capacitance, an n raw mineralization layer that reduces parasitic resistance and cross-under resistance in the source/drain regions of MOS transistors, and an n + 10-odd layer that prevents At wiring from punching through. Scattered layer, cross under
It is provided with an n+10' diffusion layer having a deep Xj that can reduce the resistance, and can be used in common with the n+10+10 diffusion layer. Therefore, 3 for speedup
It is a feature of this invention that the diffusion depth is greater than or equal to 1, and all variations within this range belong to this invention. Furthermore, it goes without saying that if the cross-under resistance can be reduced by n raw mineral scattering layers, the three important parameters for speeding up can be satisfied without using n+10 scattering layers. In this case as well, there are three or more diffusion depths.

〔Effect of the invention〕

As explained above, according to the present invention, by providing at least three different diffusion depths in the source/drain regions of the semiconductor substrate, a high-speed dynamic MO8 semiconductor device that simultaneously satisfies three parameters for speeding up is achieved. Extremely excellent effects can be achieved.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are cross-sectional views showing a conventional MOS transistor part and a part of its cross under, and FIG.
, ) and (b) are cross-sectional views of a MOS transistor part and a part of its cross under, showing an embodiment of the semiconductor device according to the present invention. αυ...P-type semiconductor substrate, αri...Isolation oxide film, C131...Thermal oxide film, Qcar...Gate oxide film, 05)...Gate polysilicon, (te...
...n source/drain region, aη...n+ source/drain region, a~...CVD oxide film, (19a
e * * n + ten area (2o+ ----diffusion area, (21), (2b). (21b) ... At wiring. Agent Shin Kuzuno - Figure 1 (q) Figure 2 ( a) (b) Procedural amendment (spontaneous) 58316 Showa year, month, day 2, name of the invention: semiconductor device 3, person making the amendment Representative: Hitoshi Katayama Department 4, agent: 5, details of the invention in the specification to be amended Explanation Column 6 Change “Gate Strap Circuit” on page 3, line 7 of the Specification of Contents of Amendment to “
"Pootstrap circuit" is corrected. that's all

Claims (1)

[Claims] 1. A MO8 type semiconductor device, characterized in that at least three different diffusion depths are provided in source/drain regions of the same semiconductor substrate.