JPS5996768A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5996768A JPS5996768A JP57207076A JP20707682A JPS5996768A JP S5996768 A JPS5996768 A JP S5996768A JP 57207076 A JP57207076 A JP 57207076A JP 20707682 A JP20707682 A JP 20707682A JP S5996768 A JPS5996768 A JP S5996768A
- Authority
- JP
- Japan
- Prior art keywords
- source
- oxide film
- region
- drain region
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 239000011574 phosphorus Substances 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000033558 biomineral tissue development Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はMO8型集積回路に用いられる半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device used in an MO8 type integrated circuit.
近年、MO8型メモリの技術開発は長足の進歩を果し、
現在では256にダイナミックMO8RAM、 64に
スタティックMO8RAMの研究、開発が進んでいる。In recent years, the technological development of MO8 type memory has made great progress.
Currently, research and development is progressing on the dynamic MO8RAM for the 256 and the static MO8RAM for the 64.
このような大容量メモリの技術開発は、微細化波曲によ
る効果が極めて大きいが、装置の技術も極めて重要であ
る。特に高速ダイナミックMO8RAMを実現するには
装置技術の開発は必須であシ、種々の検討がなされてい
る。Although the technological development of such large-capacity memory is extremely effective due to miniaturization of waveforms, device technology is also extremely important. In particular, in order to realize a high-speed dynamic MO8RAM, the development of device technology is essential, and various studies are being carried out.
一般に高速ダイナミックMO8RAMを実現するために
は、下記に示す3つの重要なパラメータがある。すなわ
ち、
(1)、ソース・ドレイン領域と信号線のクロスアンダ
一部との寄生抵抗による信号遅延の防止。Generally, in order to realize a high-speed dynamic MO8RAM, there are three important parameters shown below. That is, (1) Prevention of signal delay due to parasitic resistance between the source/drain region and a part of the cross-under of the signal line.
(2)、ゲート長を短かくすることによるコンダクタン
スの向上。(2) Improved conductance by shortening the gate length.
(3)、ゲート容量、ゲートとソース・ドレインの重な
シ容量を低減することによる浮遊容量。(3) Gate capacitance, stray capacitance by reducing the overlapping capacitance between the gate and source/drain.
ミラー容量の低減。Reduced mirror capacity.
がある。そして、これら3つのパラメータを低減し、向
上させることが高速MOSダイナミックRAMを実現す
るために装置には必要とされている。すなわち、前記(
1)項は、ソース・ドレイン領域ではコンタクトを設け
ることができず、At配線でシャントできない場合に大
きな寄生CR時定数が表われる問題である0また、クロ
スアンダ一部での信号遅延は、大きな電流をドライブす
る必要のある場合に大きな問題となシ、ダイナミックM
O8RAMのマージン不良を起こす原因となる。また、
゛前記(2)項は良く知られているようにMOS )ラ
ンジスタの性能向上でアシ、その前提はゲート長の短チ
ャンネル化である。しかしながら、短チヤンネルMOS
トランジスタは、ソース・ドレイン間の耐圧。There is. In order to realize a high-speed MOS dynamic RAM, devices are required to reduce and improve these three parameters. That is, the above (
Item 1) is a problem in which a large parasitic CR time constant appears when contacts cannot be provided in the source/drain region and shunting cannot be achieved with At wiring. Dynamic M is a big problem when you need to drive current.
This causes margin failure in O8RAM. Also,
As is well known, the above item (2) is based on improving the performance of MOS transistors, and the premise is to shorten the channel length of the gate. However, short channel MOS
A transistor has a breakdown voltage between source and drain.
すそ電流および閾値電圧の低下を起すので、その改善も
必要である。また、ダイナミック11/[O8RAMで
はゲートストラップ回路を用いるので、電源電圧以上の
電界が印加されることおよびダイナミックにメモリセル
、周辺回路を保持するためにすそ電流や閾値電圧の低下
は、致命的な欠点となるので、短チャンネル効果を起こ
さず、高コンダクタンスが実現できる装置が必要となる
。さらに前記(3)項は基本回路の負荷容量の低減とミ
ラー容量の低減である。ダイナミックMO8RAMの容
量分析を行なうと、その約54係がゲート容量である。Since this causes a decrease in skirt current and threshold voltage, improvement thereof is also required. In addition, since dynamic 11/[O8RAM uses a gate strap circuit, an electric field higher than the power supply voltage is applied, and a drop in base current and threshold voltage to dynamically hold memory cells and peripheral circuits is fatal. Since this is a drawback, a device that does not cause short channel effects and can achieve high conductance is required. Furthermore, the above item (3) is a reduction in the load capacitance of the basic circuit and a reduction in Miller capacitance. When analyzing the capacity of a dynamic MO8RAM, approximately 54 times the capacity is the gate capacity.
すなわち、全容量の約1/2である。この容量を低減で
きれば、負荷容量が低減でき高速化に有利である。That is, it is approximately 1/2 of the total capacity. If this capacitance can be reduced, the load capacitance can be reduced and it is advantageous for speeding up.
また、ゲートとソース・ドレイ/間の重な多容量は、ミ
ラー容量として作用するので、高速化の大きな妨げとな
シ、高速化にはこの容量の低減が必要である。In addition, the large amount of overlapping capacitance between the gate and the source/drain acts as a mirror capacitance, which is a major hindrance to speeding up, and it is necessary to reduce this capacitance in order to speed up.
第1図(a)および(b)は従来のMOS)ランジスタ
部およびそのクロスアンダ一部の断面図を示したもので
ある。このように構成されるMOS)ランジスタのプロ
セスクローは次に示すようになる。すなわち1
(a) p型シリコン基板(1)上に分離用酸化膜(2
)、熱酸化膜(3)を形成する0
(b) p W シ’Jコン基板(1)上にMOS)ラ
ンシスタノゲート酸化膜(4)とゲートポリシリコン(
5)とを形成する。FIGS. 1A and 1B are cross-sectional views of a conventional MOS transistor section and a part of its cross under. The process claw of the MOS transistor constructed in this way is as shown below. That is, 1 (a) An isolation oxide film (2) is placed on a p-type silicon substrate (1).
), a thermal oxide film (3) is formed on the silicon substrate (1) and a gate oxide film (4) and a gate polysilicon (MOS) are formed on the silicon substrate (1).
5) to form.
(e)ゲートポリシリコン(5)を形成した後、p型シ
リコン基板(1)上にn+ソース・ドレイン領域(6)
を形成する。この領域(6)はソース・ドレインの寄生
抵抗となるので、低抵抗化が必要である。(e) After forming gate polysilicon (5), n+ source/drain regions (6) are formed on p-type silicon substrate (1).
form. This region (6) becomes a parasitic resistance of the source/drain, so it is necessary to reduce the resistance.
(d)分離用酸化膜(2)およびゲート酸化膜(4)上
にC1VD酸化膜(7)を形成し、n+ソース・ドレイ
ン領域(6)と後述するAt配線との接続を行なうため
のコンタクトホールを穿設し、この穿孔を通してP(リ
ン)を拡散して拡散深□さxjの深い拡散域(8)を形
成する。(d) A C1VD oxide film (7) is formed on the isolation oxide film (2) and the gate oxide film (4), and a contact is made to connect the n+ source/drain region (6) to the At wiring described later. A hole is drilled and P (phosphorus) is diffused through the hole to form a deep diffusion region (8) with a diffusion depth xj.
(e) CVD酸化膜(力士にAt配線(9)を行なっ
てチップ内配線をする。(e) CVD oxide film (Att wiring (9) is performed on the sumo wrestler to perform internal wiring on the chip.
また、同図(b)はクロスアンダ一部を示したものであ
るが、この製造工程は同図(、)で示した通シでありz
”信号配線(9a) 、 (9b)下にn+ソース・ド
レイン領域(6)を設けてAt配線(9)を短絡してい
る。Also, although Figure (b) shows a part of the cross under, this manufacturing process is the same as that shown in Figure (,).
``N+ source/drain regions (6) are provided below the signal lines (9a) and (9b) to short-circuit the At lines (9).
しかしながら、前記構成による従来のMOS )ランジ
スタにおいては、高速化のための3つのノくラメータを
満足することは極めて困難であった。すなわち、n+ソ
ース・ドレイン領域(6)の拡散抵抗を下げるためには
n+ソース・ドレイン領域(6)の拡散の深さxjを深
くしてn十領域を形成するためのAsイオンの注入量を
多くする必要がある。例えば6×105/c4の注入を
行なえば、シート抵抗約25Ω/口が得られるが、xj
が0.45μmとなシ、ゲートとソース・ドレインの重
な多容量が多くなシ、高速化の妨げとなるとともに、ゲ
ート容量自体も大きくなり、高速化には好ましくない。However, in the conventional MOS transistor having the above structure, it is extremely difficult to satisfy the three parameters for increasing speed. That is, in order to lower the diffusion resistance of the n+ source/drain region (6), the amount of As ions implanted to form the n+ region by increasing the diffusion depth xj of the n+ source/drain region (6) is increased. need to do more. For example, if 6×105/c4 is implanted, a sheet resistance of about 25Ω/hole can be obtained, but xj
If it is 0.45 μm, there is a large amount of overlapping capacitance between the gate and the source/drain, which impedes speeding up and also increases the gate capacitance itself, which is not desirable for speeding up.
壕だ、周辺回路のn+拡散層のクロスアンダ−抵抗は約
250/口にできるので、配線抵抗の低抵抗化となるが
、高速化には不十分となる。一方、ゲート容量、ゲ ′
−トとソース・ドレインとの重なり容量を低減する方式
を採ると、n十拡散層のXjを浅くする必要があシ、シ
たがって寄生抵抗が大きくなるので、高速化には適さな
い。このように従来構造では3つの高速化のためのパラ
メータを満足させるには矛盾を生じ、したがって、これ
ら3つのノくラメータを同時に満足させることは不可能
であった。However, the cross-under resistance of the n+ diffusion layer of the peripheral circuit can be made to be about 250/unit, which lowers the wiring resistance, but it is not sufficient for increasing the speed. On the other hand, the gate capacitance, Ge′
If a method is adopted in which the overlapping capacitance between the gate and the source/drain is reduced, it is necessary to make Xj of the n-diffusion layer shallow, which increases the parasitic resistance, and is therefore not suitable for increasing speed. As described above, in the conventional structure, there is a contradiction in satisfying the three parameters for increasing speed, and therefore, it is impossible to satisfy these three parameters at the same time.
したがってこの発明は、前述した欠点を改善する目的で
なされたもので、半導体基板のソース・ドレイン領域に
、少なくとも異なる3つの拡散深さを設けることによっ
て、3つの高速化のためのパラメータを同時に満足でき
る半導体装置を提供することにある。Therefore, the present invention was made with the aim of improving the above-mentioned drawbacks, and by providing at least three different diffusion depths in the source/drain regions of a semiconductor substrate, three parameters for increasing speed can be simultaneously satisfied. The objective is to provide a semiconductor device that can
第2図はこの発明による半導体装置の一実差例を示す図
であシ、同図(a)はMOS)ランジスタ部の断面図、
同図(b)はクロスアンダ一部の断面図である。これら
の図において、MOSトランジスタは次に示すようなプ
ロセスによって形成される。すなわち、
(a) p型シリコン基板aII上に分離用酸化膜α々
、熱酸化膜(13)を形成する。FIG. 2 is a diagram showing an actual example of a semiconductor device according to the present invention, and FIG. 2(a) is a cross-sectional view of a MOS transistor part;
FIG. 5B is a cross-sectional view of a part of the cross under. In these figures, MOS transistors are formed by the following process. That is, (a) the isolation oxide films α and the thermal oxide film (13) are formed on the p-type silicon substrate aII.
(b) P Wシリコン基板aυ上にMOS)ランジス
タのゲート酸化膜α4)とゲートポリシリコン0ωとを
形成する。(b) A gate oxide film α4) and a gate polysilicon 0ω of a MOS transistor are formed on a PW silicon substrate aυ.
(c)ゲートポリシリコンミ9形成後、p型シリコン基
板aυの全面にnツース・ドレイン領域(161を形成
する。この場合、この領域(16)がゲート容量、、ゲ
ートとソース・ドレイン間の重な多容量を低減できる。(c) After forming the gate polysilicon layer 9, an n-tooth drain region (161) is formed on the entire surface of the p-type silicon substrate aυ. In this case, this region (16) is the gate capacitance, and It is possible to reduce large volumes.
(d) nソース・ドレイン領域を形成したい領域にの
み、レジスト膜を残し、Asを注入し、前記nソース・
ドレイン領域(L6)よりも拡散深さの深いn+ソース
・ドレイン領域(17)を形成する。(d) Leave the resist film only in the regions where you want to form the n source/drain regions, and implant As into the n source/drain regions.
An n+ source/drain region (17) having a deeper diffusion depth than the drain region (L6) is formed.
この場合、この領域(l′Oがソース・ドレインの寄生
抵抗を低減し、クロスアンダ−抵抗をも低減させる。In this case, this region (l'O) reduces the source/drain parasitic resistance and also reduces the cross-under resistance.
(e) p型シ5リコン基板αυ上の熱酸化膜(131
を局部的に除去し、その上にP(リン)をドープしたC
VD酸化酸化膜波着させる。このとき、熱酸化膜(13
)を除去した部分よl(’、lン)がp型シリコン基板
avに拡散され、n、千十領域時を形成する。この場合
、とのn千生領域a9でクロスアンダ−抵抗を低減する
。(e) Thermal oxide film (131
is locally removed and P (phosphorus) is doped thereon.
Wave-deposit VD oxide film. At this time, a thermal oxide film (13
) is diffused into the p-type silicon substrate av from the removed portion to form an n,100 region. In this case, the cross-under resistance is reduced in the nth region a9.
(f)n十十領域α9と後述するAt配線との接続を行
なうため、CvD酸化膜α〜にコンタクトホールを穿設
し、この穿孔を通してP(リン)を拡散してXjの深い
拡散領域噛を形成する。そして、At配線CI!1)
、 (21m) 、 (21b)を行なってチップ内配
線をする。この場合1.この拡散領域(イ)のXJは約
1.3μm程度である。(f) In order to connect the n10 region α9 with the At wiring described later, a contact hole is formed in the CvD oxide film α~, and P (phosphorus) is diffused through this hole to form a deep diffusion region of Xj. form. And At wiring CI! 1)
, (21m), and (21b) are performed to wire the inside of the chip. In this case 1. The XJ of this diffusion region (a) is approximately 1.3 μm.
このようにして構成されたMOS)ランジスタは、前述
した高速化の3つの重要なパラメータを全て満足するこ
とができる。すなわち、浅い拡散によるnソース・ドレ
イン領域←Qはゲートとソース・ドレイン間の重な多容
量を小さくでき、しかも同一のLef fを得るときに
は従来に比べてゲート容量も小さくできる。しかし、こ
の浅いnソース・ドレイン領域−の拡散層はシート抵抗
が高くなるので注意を要する。つまり、このnソース・
ドレイン領域Q6)の抵抗が高くなると、MOSトラン
ジスタのコンダクタンスを低下させてしまう。したがっ
て、拡散層の抵抗が1000/口以下、すなわち約lX
1015/、−dのAs注入量であればこのコンダクタ
ンスの低下が問題にはならない。このときのXJは約0
.2μmである。また、n+ソース・ドレイン領域(l
ηはXjの深さを考慮するととがないので、十分な低抵
抗化が可能となる。例えば、6X1015/−のAs注
入によシ約25Ω/口のシート抵抗が得られる。しかし
、とのAs注入量は”ジャンクションリーク等を十分に
注意して選択されなシればならない。一方、クロスアン
ダ一部のみに用いるn++領域領域波散層はPlン)を
拡散源にしておシ、xi =2.3μm程度で、シート
抵抗は15〜20Ω/口とでき、信号線の寄生抵抗を十
分に小さくできるので、高速化が容易にできる。The MOS transistor configured in this manner can satisfy all three important parameters for speeding up described above. That is, the n source/drain region←Q formed by shallow diffusion can reduce the overlapping large capacitance between the gate and the source/drain, and when obtaining the same Lef f, the gate capacitance can also be made smaller than in the conventional case. However, care must be taken because the sheet resistance of this shallow diffusion layer in the n source/drain region becomes high. In other words, this n source
When the resistance of the drain region Q6) increases, the conductance of the MOS transistor decreases. Therefore, the resistance of the diffusion layer is less than 1000/unit, that is, about 1X
If the amount of As implanted is 1015/, -d, this decrease in conductance will not be a problem. At this time, XJ is approximately 0
.. It is 2 μm. In addition, the n+ source/drain region (l
Since η is infinite considering the depth of Xj, it is possible to achieve a sufficiently low resistance. For example, a 6.times.10@15/- As implant provides a sheet resistance of about 25 .OMEGA./hole. However, the amount of As to be implanted must be selected with due care to junction leakage, etc. On the other hand, the n++ region dispersion layer used only in a part of the cross-under uses Pln as a diffusion source. When xi and xi = about 2.3 μm, the sheet resistance can be set to 15 to 20 Ω/port, and the parasitic resistance of the signal line can be sufficiently reduced, making it easy to increase the speed.
このような構成によれば、高速化に必要な3つの重要な
パラメータを全て十分に満足できるので、高速ダイナミ
ックに適したMO8I−ランジスタを実現可能となる。According to such a configuration, all three important parameters required for high speed can be fully satisfied, so it is possible to realize a MO8I-transistor suitable for high speed dynamic.
なお、前述した実施例では、NチャンネルMOSトラン
ジスタに適用した場合について説明したが、Pチャンネ
ルMO8)ランジスタに適用しても全く同様に同一の効
果が発揮できることはいうまでもない。また、前記n+
十領領域9)をP(リン)で形成した場合について説明
したが、この領域をAsの注入で行なっても、さらに低
抵抗化しても良いことは勿論である。In the above-mentioned embodiments, the case where the present invention is applied to an N-channel MOS transistor has been described, but it goes without saying that the same effect can be obtained when applied to a P-channel MOS transistor. In addition, the n+
Although the case where the tensile region 9) is formed of P (phosphorus) has been described, it is of course possible to implant this region with As or to further reduce the resistance.
このようにこの発明は、1つの半導体装置の中に3つ以
上の拡散深さの異なる拡散領域を形成したことに特徴を
有し、その構成はゲートとソース・ドレイン間の重な多
容量とゲート容量を低減させるn拡散層と、MOSトラ
ンジスタのソース・ドレイン領域の寄生抵抗とクロスア
ンダ−抵抗とを低減させるn生鉱散層と、At配線のつ
き抜は防止するためのn+十十数散層、クロスアンダ−
抵抗を低減できる深いXjを有するn+十′拡散層とを
設けたものであシ、前記n+十十数散層 +十/拡散層
とは共用も可能である。したがって、高速化のための3
つ以上の拡散深さを有することがこの発明の特徴であシ
、この範囲内での変化は全てこの発明に帰属するもので
ある。また、クロスアンダ−抵抗をn生鉱散層で低減で
きる場合には、n+十十数散層用いなくとも、高速化の
3つの重要なパラメータを満足できることは言うまでも
ない。この場合も3つ以上の拡散深さを有している。As described above, the present invention is characterized in that three or more diffusion regions with different diffusion depths are formed in one semiconductor device, and the structure has a large number of overlapping capacitances between the gate and the source/drain. An n diffusion layer that reduces gate capacitance, an n raw mineralization layer that reduces parasitic resistance and cross-under resistance in the source/drain regions of MOS transistors, and an n + 10-odd layer that prevents At wiring from punching through. Scattered layer, cross under
It is provided with an n+10' diffusion layer having a deep Xj that can reduce the resistance, and can be used in common with the n+10+10 diffusion layer. Therefore, 3 for speedup
It is a feature of this invention that the diffusion depth is greater than or equal to 1, and all variations within this range belong to this invention. Furthermore, it goes without saying that if the cross-under resistance can be reduced by n raw mineral scattering layers, the three important parameters for speeding up can be satisfied without using n+10 scattering layers. In this case as well, there are three or more diffusion depths.
以上説明したようにこの発明によれば、半導体基板のソ
ース・ドレイン領域に少なくとも3つの異なる拡散深さ
を設けたことによって、3つの高速化のだめのパラメー
タを同時に満足した高速度ダイナミックMO8半導体装
置が実現可能となる極めて優れた効果が得られる。As explained above, according to the present invention, by providing at least three different diffusion depths in the source/drain regions of the semiconductor substrate, a high-speed dynamic MO8 semiconductor device that simultaneously satisfies three parameters for speeding up is achieved. Extremely excellent effects can be achieved.
第1図(a)および(b)は従来のMOS)ランジスタ
部およびそのクロスアンダ一部を示す断面図、第2図(
、)および(b)はこの発明による半導体装置の一実施
例を示すMOS )ランジスタ部およびそのクロスアン
ダ一部の断面図である。
αυ・・・・p型半導体基板、αり・・・・分離用酸化
膜、C131・・・・熱酸化膜、Qカ・・・・ゲート酸
化膜、05)・・・・ゲートポリシリコン、(te・・
・・nソース・ドレイン領域、aη・・・・n+ソース
・ドレイン領域、a〜・・・・CVD酸化膜、(19a
e * * n+十領領域(2o+ −−−−拡散領
域、(21) 、 (2b) 。
(21b) ・〜・・At配線。
代理人 葛 野 信 −
第1図
(q)
第2図
(a)
(b)
手続補正書(自発)
58316
昭和 年 月 日
2、発明の名称
半導体装置
3、補正をする者
代表者片山仁へ部
4、代理人
5、補正の対象
明細書の発明の詳細な説明の欄
6 補正の内容
明細書第3頁第7行目の「ゲートストラップ回路」を「
プートストラップ回路」と補正する。
以 上FIGS. 1(a) and 1(b) are cross-sectional views showing a conventional MOS transistor part and a part of its cross under, and FIG.
, ) and (b) are cross-sectional views of a MOS transistor part and a part of its cross under, showing an embodiment of the semiconductor device according to the present invention. αυ...P-type semiconductor substrate, αri...Isolation oxide film, C131...Thermal oxide film, Qcar...Gate oxide film, 05)...Gate polysilicon, (te...
...n source/drain region, aη...n+ source/drain region, a~...CVD oxide film, (19a
e * * n + ten area (2o+ ----diffusion area, (21), (2b). (21b) ... At wiring. Agent Shin Kuzuno - Figure 1 (q) Figure 2 ( a) (b) Procedural amendment (spontaneous) 58316 Showa year, month, day 2, name of the invention: semiconductor device 3, person making the amendment Representative: Hitoshi Katayama Department 4, agent: 5, details of the invention in the specification to be amended Explanation Column 6 Change “Gate Strap Circuit” on page 3, line 7 of the Specification of Contents of Amendment to “
"Pootstrap circuit" is corrected. that's all
Claims (1)
・ドレイン領域に少なくとも異なる3つの拡散深さを設
けたことを特徴とする半導体装置。1. A MO8 type semiconductor device, characterized in that at least three different diffusion depths are provided in source/drain regions of the same semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57207076A JPS5996768A (en) | 1982-11-24 | 1982-11-24 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57207076A JPS5996768A (en) | 1982-11-24 | 1982-11-24 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5996768A true JPS5996768A (en) | 1984-06-04 |
JPH05872B2 JPH05872B2 (en) | 1993-01-06 |
Family
ID=16533799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57207076A Granted JPS5996768A (en) | 1982-11-24 | 1982-11-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5996768A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5061649A (en) * | 1986-03-31 | 1991-10-29 | Kabushiki Kaisha Toshiba | Field effect transistor with lightly doped drain structure and method for manufacturing the same |
US5101262A (en) * | 1985-08-13 | 1992-03-31 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing it |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5271974A (en) * | 1975-12-11 | 1977-06-15 | Nec Corp | Production of semiconductor device |
-
1982
- 1982-11-24 JP JP57207076A patent/JPS5996768A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5271974A (en) * | 1975-12-11 | 1977-06-15 | Nec Corp | Production of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5101262A (en) * | 1985-08-13 | 1992-03-31 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of manufacturing it |
US5061649A (en) * | 1986-03-31 | 1991-10-29 | Kabushiki Kaisha Toshiba | Field effect transistor with lightly doped drain structure and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH05872B2 (en) | 1993-01-06 |
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