JPS5996758A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS5996758A JPS5996758A JP57206624A JP20662482A JPS5996758A JP S5996758 A JPS5996758 A JP S5996758A JP 57206624 A JP57206624 A JP 57206624A JP 20662482 A JP20662482 A JP 20662482A JP S5996758 A JPS5996758 A JP S5996758A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- hole
- partition
- lead
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明はＩＣ、ＬＳ Ｉ等の半導体装置を外囲器内に組
み立てる際に使用されるリードフレームの改良に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in lead frames used when assembling semiconductor devices such as ICs and LSIs into envelopes.
第１図に示すように、ＩＣやＬＳＩ等の半導体チップｌ
はリードフレームＵを用いて外囲器にパッケージングさ
れる。同図において、１１ 、１１’はリードフレーム
の外枠で、平行に配役されている。薇外枠１１ 、 Ｉ
Ｚ’は所定の間隔をおいて仕切枠１２で連結されてお
り、この仕切枠１２には喝その全長に亘って透孔１３が
穿設されている。そして、１を切砕１２および外枠Ｉ
Ｚ 、 １２’で囲まれた領域には所定のノくターンが
形成されている。壕ず、その・令甲火に（は半導体チッ
プｌをマウントするためのベッド部１４が自己役され、
該ベッド部は支干守り一ド１５によって外枠Ｉ Ｚ 、
Ｊ １’に連結支持されている。As shown in Figure 1, semiconductor chips such as IC and LSI
is packaged into an envelope using a lead frame U. In the figure, 11 and 11' are outer frames of lead frames, which are arranged in parallel. Outer frame 11, I
Z' are connected by a partition frame 12 at a predetermined interval, and a through hole 13 is bored in the partition frame 12 over its entire length. Then, cut 1 into pieces 12 and outer frame I.
A predetermined notch is formed in the area surrounded by Z and 12'. The bed section 14 for mounting the semiconductor chip is self-contained, without a trench.
The bed part has an outer frame IZ,
It is connected and supported by J1'.
このベッド部１４の周囲にはこれに離間して多数のイン
ナーリード１６・・・が目己役されている。A large number of inner leads 16 are provided around the bed portion 14 at a distance therebetween.
これらのインナーリード１６・・・はその先端がベッド
部１４を取シ囲むように１己役され、他端部は外部リー
ド１７・・・とじて延設されて仕゛切枠１２に運７附さ
れている。また、同じ方間に延設てれるインナーリード
１６・・・は外部リード１７・・・との境界においてブ
リッジ部１８を介して相互に連結され、更に外枠１７
、 Ｚ １’に運、１店支持されている。The tips of these inner leads 16 are used to surround the bed part 14, and the other ends are extended as external leads 17 and carried to the cutting frame 12. It is attached. Further, the inner leads 16 extending in the same direction are connected to each other via the bridge portion 18 at the boundary with the outer leads 17, and furthermore, the outer leads 17
, Z 1' is lucky and supported by 1 store.
上記のリードフレームを用いて半へ９体チップ１を外ｌ
ｉ５器にパッケージングする際には、１ず図示のように
半導体チップ１をベッド部１４上にマウントする（ダイ
ボンディング）。続いて半４にチップｌの内部端子とイ
ンナーリード１６・・・の先端部間をＡｕ あるいはＡ
Ｉ！巻のボンディングワイヤ２で接続する（ワイヤボン
ディング）。その後、飼えば樹脂封止パッケージの場合
には、半導体チップ１、ベッド部１４、インナーリード
１６・・・およびポンディングワイヤ２の部分を樹脂モ
ールド層で気酪封止する（樹脂封止工程）。次いで、支
持リード１５を外枠Ｚ Ｚ 、 Ｚ Ｚ’から切断する
と共に外部リード１７・・・を仕切枠１２から切断し、
同時にブリッジ部１８を切除する。これてよって個々の
半導体装置がフレームから分離され、また個々の独立し
たリードが形成される（リードフォーミング工程）。Remove the 9-piece chip 1 into half using the above lead frame.
When packaging into an i5 device, the semiconductor chip 1 is first mounted on the bed portion 14 as shown in the figure (die bonding). Next, on half 4, connect Au or A between the internal terminal of chip l and the tip of inner lead 16...
I! Connect with the 2-volume bonding wire (wire bonding). After that, in the case of a resin-sealed package, the semiconductor chip 1, bed portion 14, inner leads 16, and bonding wires 2 are air-sealed with a resin mold layer (resin sealing step). . Next, the support leads 15 are cut from the outer frames ZZ, ZZ', and the outer leads 17... are cut from the partition frame 12,
At the same time, the bridge portion 18 is removed. As a result, individual semiconductor devices are separated from the frame, and individual independent leads are formed (lead forming step).
ところで、インナーリード１６・・・の先端部には一般
にへグ メッキが施されており、前記ワイヤボンディン
グエ梶においては、インナーリード１６・・・を２５０
〜３５０℃にヒートアップした状態でボイディングワイ
ヤ２を圧脇する。仕切枠１２の略全長に亘って穿設され
た透孔１３は、このワイヤボンディング時の加熱によっ
て生じる歪を緩和し、リードフレーム１０に反りが発生
するのを防止する作用を果たすものである。By the way, the tips of the inner leads 16 are generally coated with a metal plate, and in the wire bonding machine, the inner leads 16 are coated with 250 ml of metal.
The voiding wire 2 is pressed while heated to ~350°C. The through holes 13 formed along substantially the entire length of the partition frame 12 serve to alleviate the distortion caused by heating during wire bonding and to prevent the lead frame 10 from warping.
しかしながら、上記従来のリードフレームは、フラット
パッケージ用リードフレームのように板厚が０．２〜０
．１５ ｍｍと薄い場合には熱歪に対する調性が小さい
ため、仕切枠１２に設けた透孔１３だけではこの歪を防
止できず、反りの発生を回避できないという問題があっ
た。また長尺フレームの場合にも、ワイヤボンディング
時の熱膨張が外枠１１． Ｉ Ｊ’を介して７賭がるた
めに透孔１３だけではこれを緩和できず、反りの発生を
防止できないという間通があった。However, the conventional lead frame mentioned above has a plate thickness of 0.2 to 0.
．． When the thickness is as thin as 15 mm, the tonality with respect to thermal distortion is small, so that the through holes 13 provided in the partition frame 12 alone cannot prevent this distortion, and there is a problem that warping cannot be avoided. Also, in the case of a long frame, the thermal expansion during wire bonding will cause the outer frame 11. 7 through IJ', the through hole 13 alone could not alleviate this problem and could not prevent the occurrence of warpage.
本発明は上記事情に鑑みてなされたもので、板厚の薄い
フラットパッケージ用リードフレ°−ムあるいは長尺の
リードフレームの場合にも、ワイヤボンディング時の熱
歪を緩和して反りの発生を防止することが７できるリー
ドフレームを提供しようとするものである。The present invention was made in view of the above circumstances, and even in the case of thin lead frames for flat packages or long lead frames, thermal distortion during wire bonding is alleviated and warpage is prevented. The purpose of the present invention is to provide a lead frame that can
〔発明の概要Ｊ
本発明によるリードフレームは、従来のリードフレーム
における外枠の仕切枠との連結位置に、仕切枠に穿設さ
れだ透孔と連通する新たな透孔を穿設したことを特徴と
するものである。[Summary of the Invention J The lead frame according to the present invention has a new through hole that communicates with the through hole drilled in the partition frame at the connection position of the outer frame and the partition frame in the conventional lead frame. This is a characteristic feature.
上記本発明のリードフレームでは外枠に新たに設けた透
孔により、ワイヤボンディング時に外枠を介して長手方
向に継がる熱歪を緩和することができる。In the lead frame of the present invention, the through holes newly provided in the outer frame can alleviate thermal strain that continues in the longitudinal direction through the outer frame during wire bonding.
実施例
第２図は本発明の一笑加例になるリードフレームを示す
平面１図である。同図において、１１゜ｌｉ’ｊは外枠
、１２は仕切枠、１４はベッド、Ｎ１５、ｚ５ｔｊ、支
持リード、１６はインナーリード、１７は外部リード、
１８はブリッジ部であシ、これらは総て第１図の従来の
リードフレームと同ｂｊ＜に形成されている。他方、こ
の実施トリでは仕切枠１２Ｖこ、従来の透孔１３と違っ
て外枠１２ 、１１’に種で延設された透孔１３’が穿
設されている。そして、外枠Ｉ Ｚ 、 １１’には仕
切枠１２との遅１．活位、ｉｌ ｖで前記透孔１３Ｖ？
ｌ連通する新たな透孔１９が長手方向（てτａって形成
されている。Embodiment FIG. 2 is a plan view showing a lead frame which is an additional example of the present invention. In the same figure, 11゜li'j is an outer frame, 12 is a partition frame, 14 is a bed, N15, z5tj is a support lead, 16 is an inner lead, 17 is an outer lead,
Reference numeral 18 denotes a bridge portion, all of which are formed at the same bj< as in the conventional lead frame shown in FIG. On the other hand, in this embodiment, the partition frame 12V is different from the conventional through hole 13 in that the outer frame 12, 11' is provided with a through hole 13' extending with a seed. The outer frame I Z , 11' has a lag 1. The active position, the through hole 13V at il v?
A new through hole 19 that communicates with each other is formed in the longitudinal direction (τa).
上記実’；”Ａ （！１１ｊのリードフレームによれば
、ワイヤボンディング時の刀口熱による歪は二つの透孔
１３’ ＋ １９’によってｌ丙オロされる。待に、新
たに設けられた透孔１９によって、従来は全く吸収され
なかった外枠１１ 、１１’を介して長手方向に′ｉ社
がる歪を犬ｔｌｌ昌に緩和することができる。従つて、
上に実Ｍｔｉ ｅ’ｌｌ」のリードフレームによれば、
長尺あるいは薄手のリードフレームの揚台にもワイヤボ
ンディング時の反１）’Ａ生を直重することができる。According to the lead frame of the above-mentioned actual ';'A (!11j), the distortion caused by the knife edge heat during wire bonding is reduced by the two through holes 13' + 19'. Due to the holes 19, the strain exerted in the longitudinal direction through the outer frames 11 and 11', which was not absorbed at all in the past, can be completely alleviated.
According to the lead frame,
It is also possible to directly load the raw material during wire bonding on the platform of a long or thin lead frame.
以上説明したよう（で、本発明によればワイヤボンディ
ング＋１３：の年ζ歪を太：ｉ昌に緩オ日し、フラット
パッケージ用のリードフレームあるいは長尺のリードフ
レームの場合にも反りの発生を直重することができるり
−、ドフレームを提供でさるものである。As explained above, according to the present invention, the distortion of wire bonding +13:0. It can be hung vertically or provided with a frame.
第１図は従来のリードフレームに半４体チップをマウン
トし、史Ｑζフイヤボンデイング？行なった状態ｃシ示
す平面図、第２図は本発明の一実施例になるリードフレ
ームの平面図である。
１１ 、１１’・・・外枠、１２・・・仕切枠、１３′
・・・透孔、１４・・・ベッド部、１５・・・支持リー
ド、１６・・・インナーリード、１７・・・外部リード
、１８・・・ブリッジ部、１９・・・透孔。Figure 1 shows a half-quad chip mounted on a conventional lead frame and subjected to history Qζ wire bonding. FIG. 2 is a plan view of a lead frame according to an embodiment of the present invention. 11, 11'...outer frame, 12...partition frame, 13'
...Through hole, 14...Bed part, 15...Support lead, 16...Inner lead, 17...Outer lead, 18...Bridge part, 19...Through hole.
Claims (1)
を所定間隔で連結する複数の仕切枠と、該仕切枠および
前記外枠で囲まれた領域の略中央に配設され、外枠また
は仕切枠に連結支持されたベッド部と、該ベッド部の周
囲にこれと離間して配設された複数のインナーリードと
、該インナーリードを延設して形成され、ＡｉＪ記仕切
枠に連結支持された外部リードと、前記仕切枠の略全長
に亘って穿設された第１０透孔と、前記外枠における仕
切枠との連結位置に前記第１の透孔に連辿して穿設され
た嬉２のＩ力孔とを具備したことを４似とするリードフ
レーム。Two outer frames arranged in parallel in the longitudinal direction, a plurality of partition frames connecting these outer frames at predetermined intervals, and arranged approximately in the center of the area surrounded by the partition frames and the outer frame. AiJ memory is formed by extending the inner leads, including a bed portion connected and supported by an outer frame or a partition frame, a plurality of inner leads arranged around the bed portion at a distance from the bed portion, and the inner leads extending from the bed portion. An external lead connected and supported by the partition frame, a tenth through hole drilled over substantially the entire length of the partition frame, and a connecting position of the outer frame with the partition frame are connected to the first through hole. A lead frame similar to 4 in that it is equipped with a 2-hole I force hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57206624A JPS5996758A (en) | 1982-11-25 | 1982-11-25 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57206624A JPS5996758A (en) | 1982-11-25 | 1982-11-25 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5996758A true JPS5996758A (en) | 1984-06-04 |
| JPH0463544B2 JPH0463544B2 (en) | 1992-10-12 |
Family
ID=16526453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57206624A Granted JPS5996758A (en) | 1982-11-25 | 1982-11-25 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5996758A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4887352A (en) * | 1986-12-31 | 1989-12-19 | Texas Instruments Incorporated | Method for making matrix lead frame |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5294074A (en) * | 1976-02-04 | 1977-08-08 | Hitachi Ltd | Leading-in frame |
-
1982
- 1982-11-25 JP JP57206624A patent/JPS5996758A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5294074A (en) * | 1976-02-04 | 1977-08-08 | Hitachi Ltd | Leading-in frame |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4887352A (en) * | 1986-12-31 | 1989-12-19 | Texas Instruments Incorporated | Method for making matrix lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0463544B2 (en) | 1992-10-12 |
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