JPS5995726A - High speed dpcm encoder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Related Field of the Invention The present invention relates to the use of quantization circuits and estimated values calculated using prediction coefficients from preceding PCM signal values characterized by an integer delay index. PCM on the input side, with an arithmetic calculation element for determining the DPCM signal value by
It relates to a high speed DPCM encoder in which signal values are added. - For the digital transmission or storage of signals (in which the differential-ξ pulse code modulation (DP CM) method is often used, the signal to be transmitted is unsampled, yielding the P CM signal value s1. An estimated value ↑1 is calculated from the PCM signal value Si-k. The difference △s+ = si-↑ is quantized and then transmitted or stored. The purpose of this method is to achieve only a relatively low bit rate. This reduces the required transmission speed and storage capacity.A simple PCM Luso is shown in FIG. 1.The operation of this loop will be explained in more detail later. The calculation of the estimated value S1 is carried out in cow steps, which must be carried out within a time corresponding to the time interval tA of two consecutive PCM signal values "i" i+4, for example for broadband television signals. For such high data transmission rates, very little time is available for this calculation operation, so that it is difficult or impossible to realize it even using modern circuit technology.

OBJECT OF THE INVENTION An object of the invention is to provide a DPCM encoder with short processing times.

DESCRIPTION OF THE INVENTION Based on the known technology mentioned at the outset, this problem is solved according to the invention as follows. That is, two serially connected calculation units are provided as a DPCM encoder, and the first
The arithmetic unit includes a transformer filter having at least one multiplier and at least one subtractor, the transformer filter having a first intermediate value zl, 1''5l as an output signal. -As-Bs1-l-CS]k
1m -Ds -... 1-n (k(J'(m(n)), and the second calculation unit includes a quantization circuit that sends out a quantization error of the DPCM signal value as an output signal. , and an arithmetic calculation element is provided for determining the quantization error multiplied by the associated prediction coefficient, and the quantization error of the first intermediate value, evaluated as above, is reduced (both by one further subtraction). The output side of the last subtractor among the subtracters on the side whose subtraction input side is supplied with the quantization error multiplied by the prediction coefficient is connected to the input side of the quantization circuit.

Effects of the Invention By dividing into two calculation units, it is possible to calculate the estimated value S1 by mutually independent calculation processes. The first calculation is a transversal filter in which the actual PCM signal value is calculated reduced by the previous signal value multiplied by the associated prediction coefficient.

In the second calculation unit, also multiplied by the same prediction coefficients, 7) the quantization error is subtracted from the previously calculated intermediate value. as a result.

Original DPCMPCM signal value 8 that is quantized and sent out
1 will be given.

At least one output of the quantization circuit has at least one
It is advantageous to send out the quantization error multiplied by two prediction coefficients.

When calculating the estimated value S1, the preceding PCM signal value 81 is generally used.
-1 is important. The quantization circuit has already produced the product A.9,
is sent, the multiplication process can be omitted.

When calculating the estimated value from a plurality of preceding PCM signal values, in the second calculation unit a first subtractor with another subtractor is used.
a calculation loop is provided, the subtraction input of the subtracter is supplied with the quantization error from the output of the quantization circuit multiplied by the prediction coefficient, and is pre-connected to the first calculation loop; a second calculation loop with another third subtractor;
It is advantageous to calculate the quantization error which is multiplied by the associated remaining prediction coefficients in the calculation loop and subtract it from the first intermediate value.The division into the second calculation loop has the following advantages: That is, it is sufficient to perform only one reading process from the quantization circuit and one subtraction for the calculation operation of the second calculation process. In this case, an addition can also be performed instead of a subtraction, for example by the quantization circuit already delivering A, the one's complement.

It is advantageous if the quantization circuit has a further output, from which the quantized DPCM signal value is delivered.

If the quantization circuit directly delivers the quantized DP CM signal value, there is no need to calculate the DPCM signal value from the quantization error and the unquantized PCM signal value.

The first input terminal of the adder is connected to the input side of the quantization circuit, and the second input terminal is connected to the output side of the quantization circuit to obtain the quantized DPCM signal value. It is advantageous in terms of cost when connected to

quantization error Aq1' which is multiplied by the prediction coefficient A) If a quantization circuit is also provided which also directly sends out the quantization error q1, the quantized DPC is multiplied by the use of an additional adder.
M signal can be calculated. In the quantization circuit,
Sending out the quantized DPCM signal value is omitted. The transmission of the quantization error q1 is always advantageous when the calculation of the estimated value is carried out from a plurality of preceding PCM signal values.

To calculate the estimated value from the preceding PCM signal value,
The first calculation unit includes a multiplier, a first input of the multiplier is connected to the input of the DPCM encoder, a second input of the multiplier is supplied with prediction coefficients, and an output of the multiplier is connected to the first input of the multiplier. is connected to the subtraction input of a first subtractor, the first input of this subtractor is also connected to the input, and the output is connected to the first input of another subtracter, and the whose output side is connected to the input side of the quantization circuit and is evaluated by the prediction coefficients,
It is advantageous if the second output of the quantization circuit is connected to the subtraction input of a further subtractor.

In this circuit arrangement, the DPCM encoder principle used is particularly advantageous. In the second calculation unit, only the output output of the quantizer circuit 6 and the subtraction process tx must be performed during the sampling period of the PCM signal.

The temporally precise and critical calculation operations of the second calculation unit are carried out independently of the evaluation of the quantization error using the associated prediction coefficients.

It is advantageous to provide a randomly addressable memory as the quantization circuit.

Randomly Addressable Read Memory (ROM)
') is advantageously used as a quantization circuit. The DPCM signal value applied to the input side acts as an address. The transmitted data comprises quantized DPCM signal values and quantization errors.

In the design of an optimal high-speed DPCM encoder, it is advantageous if the quantization error evaluated by the prediction coefficients present at the output of the quantization circuit is supplied at all of its inputs.

The quantization circuit has the calculated DPC'MPCM signal value △
The quantization error q multiplied by the prediction coefficient A sent from the S quantization circuit is input as an address. Detection of the quantized DPCM signal values can also be carried out by reading the data stored in the form of a randomly addressable read memory (ROM) or by internally storing the corresponding DPCM signal values in whole or in part. It can also be done by calculating each time.

It is advantageous to provide a highly integrated logic circuit (logic array) as the quantization circuit.

The use of highly integrated logic circuits (logic arrays) increases the operating speed of the quantization circuit.This also allows for the combination of subtracters (adders) and ROMs.

Instead of a subtractor, it is advantageous to provide an adder whose second input is supplied with the complement of the value to be subtracted in each case.

This allows commercially available adders to be used.

Description of examples Next, the present invention will be explained in detail using illustrated embodiments. A conventional DPCM encoder is illustrated in FIG.

This DPCM encoder has a subtractor 1 whose input 11 forms the input E of the circuit arrangement. Output side 1 of subtractor l
3 is connected to the input side 21 of the quantization circuit 20. The output side 22 of the quantization circuit is a quantized DPCMPCM
The signal values 1+q form the output 0 of the DPCM encoder. The output side of the quantization circuit 2 is the first input side -3 of the adder 3.
1VC is also connected. The output 33 of the adder is connected to the first input 51 of the multiplier 5. is connected to the subtraction input side 12 of the subtracter and to the second input side 32 of the adder 3. 2nd manual side of multiplier 5
2, a constant prediction coefficient ≦1 is provided. At the input E of the circuit, a PCM signal s1 is supplied. Index 1 indicates the temporal order of the signals.

The operation of the DPCM encoder consists in calculating an estimate value 1 from the preceding sample values. Applied PCM signal value s
1 and the estimated value s1, the difference Δs1 is calculated, subsequently quantized and then transmitted. This quantized DPCM signal is Δs1. It is called q. DPCM
The time course of the signal value calculation takes place in four steps:

1. Until time t1: Calculation of △5l-8i-81 2. Until time t2: △S1→△s11. Quantization 3, up to time t3: ? Addition of +△S 1 q ton Until time t4: Multiplication: A value ↑, + to s ) = ↑1 + 11 1
, q These four calculation steps must be carried out within a time tA corresponding to the time interval l 1+1 of two consecutive PCM signal values 3'+S.

The DP CM encoder is only schematically shown.

In this case, it is assumed that an output signal is generated from each circuit element at each time point tl to t4. This can be done by selecting suitable modules, but also by additional delay elements or by suitable temporary memories (bistable multivibrators).

FIG. 2 shows a basic circuit illustrating the principle of the DPCM encoder of the present invention. This DPCM encoder consists of two calculation units) CI and C2. The input side of the DPCM encoder is also indicated by E, and the output side is indicated by 0.

The first calculation unit) C1 has a subtractor l.

Its first input 11 is directly connected to input E.

The second input 12 of the first subtractor, ie the subtraction input, is connected to the output 53 of the multiplier 5.

A first input 51 of this multiplier is also connected directly to input E. A second input 52 of the multiplier 5 is supplied with the prediction coefficient A. The second calculation unit C2 has another subtractor (second subtractor) 9.

The output side 93 of this subtracter is the input side 71 of the quantization circuit 70.
It is connected to the. The first output 72 of the quantization circuit is, for example, a quantized DPCM with a respective raw bit width.
The signal value Δ8 r, q is sent out, and the second output 73 is connected back to the subtraction input 92 of the second subtractor' (color. In the first subtractor; tl, 3 the signal is 1 occurs at the location shown in the figure and is held until the next signal change or the operation clock of the calculation element.
At all locations indicated by ln, the information changes at the same point in time.

In short, for example, the change in the PCM signal value at the input E and the output of the result at the outputs of the multiplier 5, the first subtractor and the quantization circuit 7 take place with the same operating clock T1. The second index n is simply the PC in the DPCM encoder.
It is only used to easily track the M signal value. The time point indicated by t2.n is the time point t1.
+n. A delay element of arbitrary length can be inserted between the first calculation unit C1 and the second calculation unit hC2, and the second subtractor 9 has two It is only necessary to consider providing the input values at the appropriate times.

In order to make the function of the DPCM encoder easier to understand, the explanation will be given by returning to FIG. 1 once again. "' +q appears in the quantized DPCM signal on the output side of the quantization circuit 2. If the quantization error is 91, then the following formula 1 △"i+q="i 'i+qi holds true.

In order to calculate the next estimated value ↑, the generated estimated value S1 is first added to the amount]+the output signal of the quantization circuit 2 in the adder 3. This gives equation 2 (S
, -31+q)+(s)'=s4+qil holds true.

FIG. 1 shows the signal display at this time t6. After multiplication with the prediction coefficient A at time t4, Equation 3 S1+1-A(S1+qi) holds true for the new signal value.

Equation 4 5j-A (S'i-1+q, -1) was established for the previous estimated value S.

Thereby, the DPCM signal value Δs1 can be calculated as follows.

Formula 5 △S=S・-8 II+ = (S, -A, )-(A, )1
8l-IQ! -1 The calculation of the first term 5i-ASi-1 is performed in the first calculation unit C1VC of the DPCM encoder of the present invention, and in the second
The calculation of the terms A-q, . is carried out in the second calculation unit C2. Here, it is assumed that the last signal value is used for calculating the estimated value.

A DPCM signal value S, is traced from input E to output 0 as it passes through the DPCM encoder of the invention. Input side E
, the PCM signal value changes at time t1 according to the operating clock T1. At time t1,1 the signal value s
1 is added to the input side E. At the same time, the output 5 of the multiplier 5
! .

The product A-8,-1 is sent out. These two values are fed to a first subtractor 1 and a first intermediate value Z = s - A
-8 occurs. This intermediate value l +J l
l-1Z1,1, the second calculation unit c2
can be used at any time. Assume that the next operating clock T1 occurs at time points t1 and 2, for example. The second subtractor 9 is supplied with the intermediate value Z11 and the quantization error Qi j multiplied by the prediction coefficient A from the second output 76 of the quantization circuit 7 .

DPC at the output 93 of the second subtractor at time t2,2
An M signal value ΔS is generated. All symbols in FIG. 2 are illustrated for this point.

Therefore, the next PCM signal value S. is already applied to the input side since time t1,2.

l+1 In FIG. 3, a time diagram with operating clocks T1 and T2 is shown for clarity.

After the next operating clock T1, the next quantized DPCM is output from the first output side 72 of the quantizer circuit 7 at time t1,3.
A signal value ΔS1,9 is sent out.

FIG. 4 shows the modified circuit of FIG. 2 in principle. A first delay element 6 is connected downstream of the multiplier 5 .

A second delay element 8' is inserted between the output side 13 of the first subtracter and the input side 91 of the second subtracter, and the output side of the quantization circuit 71 which is not clocked and the input side of the second subtracter. A third delay element is inserted between the subtraction input side 92 and the subtraction input side 92. As delay elements it is again possible to use bistable multivibrators or similar memories controlled by operating clocks T1 and T2.

The same applies to the second subtractor 9, in that the first delay element 6 allows the first subtractor l to be supplied with a new input signal at the same time. Otherwise, the operation is the same as the DPCM encoder shown in the basic circuit of FIG.

The calculation of the estimated value S, can also be performed from a plurality of preceding pcM signal values. This means, for example, that television
This is a case of DPCM encoding for a John signal. Fifth
The figure shows the pixels of two consecutive one-scan lines of a television image. In order to calculate the estimated value for pixel X, the signal values of pixels a to d are similarly used.

A corresponding encoder according to the invention is illustrated in FIG. The first calculation unit c10 of the DPCM encoder in which two-dimensional prediction is performed has four multipliers 5, 51 to 53.

These multipliers multiply the input signal value by the prediction coefficients A to d corresponding to the pixels a to d. The input E1 of the DPCM encoder is connected via a delay element 69 to a first subtractor and also to a multiplier 5, a delay element 6 . The output of the subtracter l is connected via an adder 11 and a further delay element 68 to the subtraction input of this subtracter l. Another delay element 60 is also connected to the input side of E.
Connected to 1. The delay time of this delay element corresponds to one scanning line-three pixels. The output side of the delay element 60 is connected to the second input terminal of the adder 11 via the second multiplier 51 , the delay element 61 , the adder 12 and the delay element 67 .

Similarly, a third multiplier 52 is connected to the output side of the delay element 60. The output side of this multiplier includes a delay element 62,
It is also connected to the second input terminal of the adder 12 via the adder 13 and the delay element 66 . Furthermore, the output side of the delay element 6o is connected to a delay element 65, a fourth multiplier 53, and a delay element 6.
3 to the second input terminal of the adder 13. The second calculation unit has a quantization circuit 72 with two outputs 73 and 74.

At the output 74, a quantization error Qi occurs. The quantized output signal at the output side o1 of the DPCM encoder is sent to the adder lO
This adder includes a quantization circuit 72
The output 74 of is also connected and is also supplied with the input signal of the quantization circuit.

The output 74 of the quantization circuit is connected to multipliers 55 to 57 via a delay circuit having a delay time of one scan line/subpixel.
is connected to a first calculation loop having a first calculation loop. These multipliers multiply the quantization error by the associated prediction coefficients in a timely manner. For this purpose, the input side of the multiplier 55 is
is connected to the output of the adder 14 via a further delay element 42 and a further delay element 46 is connected to the subtraction input of the third subtractor 8. This subtractor forms the input side of the second calculation unit C20. Multiplier 56 is also connected to the output side of delay element 40 and to the second input terminal of adder 14 via delay element 43 , adder 15 and delay element 45 .

Multiplier 57 is connected on the one hand via a delay element 47 to the output of delay element 40 and on the other hand via a further delay element 44 also to the second input of adder 15 . The output of the third subtractor 8 is connected via a delay element 41 to a first input of a further subtractor 9, which can be seen in FIG. Quantization error q1 multiplied by prediction coefficient A
The second output 73 of the quantization circuit 72, through which the quantization circuit 72 is delivered, is connected via a delay output to the subtraction input of a subtractor 90, the output of which is connected to the input 71 of the quantization circuit 720. It is connected to the. All delay elements except delay elements 4o and 6o act as a time delay by a period tA which corresponds to the period of the PCM signal value applied to input El.

These delay elements are advantageously realized by clocked bistable multi-node resistors (registers).

At the output 01 of the DPCM encoder there is usually a data word with a bit width larger than that which is normally available for the transmission of the PCM signal.

In this case the word width may be limited by the post-encoder.

In the first calculation unit, the first intermediate value is calculated according to FIG. 1=Cs, , m-1)8.　　.

is calculated.

The calculation of the quantization error evaluated by the associated prediction coefficients takes place in two calculation loops of the second calculation unit C20. Evaluation using prediction coefficients B, C and D is performed in the first calculation loop. The prediction coefficient is subtracted from the first intermediate value z1,1, so that a second intermediate value appears at the output of the subtracter 8 and the downstream delay element 41. -4 +, 2 1 -C91-m 'Si -m Qi -1(li
-m-Qi-n Since the indices in equations 6 and 7 are typically 1, a second calculation loop with a delay element 4 and a subtractor 9 is provided. This is because, as in FIG. 2, the last quantization error delivered by the quantization circuit must already be evaluated together with N. Indices l to n of equation 6
is always larger and represents the delay of the preceding signal value associated with the actual PCM signal value s + K, which is taken into account for the calculation of the estimated value s1. k.

1. m and n can be expressed as delay indices in this case. Therefore, after subtraction of A9□-e on the output side of the subtractor 9, Equation 8 △5-s-s, = s-A (+l to s4-
1] ]qi-k)-B
(Si-4ql-l) 10 (1-m Qj-7) −
D(si-n+Qi-n) holds true.

When configuring the circuit, the PCM signal value evaluated by the prediction coefficients A through quantization error subtraction is inserted between the input side E and the input side of the quantization circuit 720 via a delay element. It could also be done with different subtracters.

This only increases the transit time of the PCM signal.

Furthermore, the quantization circuits are of course B-q, C-q.

D Qi can also be sent, or B-q, z
, CQi-n, etc. are sent from the output side, -;
It can also be done by multiplying the product A-q by multiplying by -....

In FIG. 7, the operating speed is optimized. DI in Figure 2? A variant embodiment of the CM encoder is illustrated. The second calculation unit consists of a clocked ROM which is used as a quantization circuit 73. This R.O.
In addition to the output 13 of the subtractor, M has its own output 73 connected to its input 75 as an address, to which the quantization error multiplied by the prediction coefficient A is sent. The entire DPCM encoder can then be operated with a single operating clock T1. Highly integrated circuit devices (logic arrays) can be used instead of conventional ROMs. In this circuit device, when delay time is allowed,
A partial or complete subtraction can also be carried out, as in the subtractor 9 of FIG. 2. The DPCM decoder can be constructed according to the same principle as the DI) CM encoder.

[Brief explanation of drawings]

FIG. 1 is a basic circuit diagram of a conventional DICM encoder, and FIG. 2 is a circuit diagram of a conventional DICM encoder, and FIG.
3 is a diagram showing the principle of a PCM encoder, FIG. 3 is a diagram showing a time diagram for explaining the operation of the circuit of FIG. 2, and FIG. 4 is a diagram showing an embodiment having a clock-controlled memory; FIG. FIG. 5 is a diagram showing the positions of pixel points required for estimation calculation in a DP CMM encoder that performs two-dimensional prediction, and FIG. FIG. 7 is a block circuit diagram of a DPCM encoder in which one-dimensional prediction is performed.
) I) It is a principle circuit diagram of a CM encoder. 51-PCM signal value, Δs, -DPCM signal value,
Si...Estimated value, ql...Quantization error, A, B. Please...prediction coefficient, k+11+m+n...
...Delay index, z, = intermediate value, C1, C2, CIO, C
20...Calculation unit, 1,8.9...Subtractor, 5゜5
1~53.55~57...multiplier, 3.10~15...
Adder, 2, 7, 71.72 Quantization circuit, cow, 6.
8', 40-cow 7, 60-63. ．． 65-69 Delay element FIG 4 FIG 5

Claims (1)

[Claims] 1. A preceding PC characterized by a quantization circuit and an integer delay index (k, l, rn, n...)
and an arithmetic calculation element for determining the DPCM signal value (△31) by using the estimated value (s,) calculated from the M signal value using the prediction coefficients (A,, B, C, ...). In addition, in a high-speed DPCM encoder that receives a PCM signal value (S, ) on the input side, two serially connected calculation units (CIO, C20) are provided as the DPCM encoder, and the first calculation unit) (C1○) includes a transparsal filter having at least one multiplier (5) and at least one subtractor (1), which transpersal filter has as an output signal a first intermediate Value Z −s −A −B
-C1,1-ISt kS1-lSi-□ = D86 -... -n (k<A<m<n), and the second calculation unit (C20) outputs the DPCM signal value as an output signal. (△Si) quantization error (
q;), and to obtain quantization errors (A,, B ql-kqi-1 , C, D, . . . ) to be multiplied by the associated prediction coefficients. Calculation qi-
m qi−n arithmetic calculation elements (55 to 57) are provided and evaluated as described above, the first intermediate values (Z, , , ) have a small quantization error (both one another subtraction The output side of the last subtractor (9) is supplied with the quantization error (ql-4,) subtracted in the subtractor (Q, 8) and multiplied by the prediction coefficient A to the subtraction input side. A high-speed DPCM encoder, characterized in that it is connected to the input side (71) of the quantization circuit (72). 2. At least one output side (73) of the quantization circuit (72, 71) has at least one DPCM encoder according to claim 1, characterized in that the quantization error (A-q) is multiplied by the prediction coefficient.
9), the subtraction input side (92) of the subtractor is provided with a quantization error (92) from the output side of the quantization circuit (72), multiplied by the prediction coefficient A. A,
)q. is provided and is pre-connected to the first calculation loop and has a further third subtractor (8), in which the remaining predictions of the associated The quantization error (Bqi-1qi-m '14-n''') multiplied by the coefficients (B, C, D,...) is calculated and subtracted from the first intermediate value (Z, , 1) The high-speed DPCM encoder according to claim 2. 4. The quantization circuit (7, 71, 73) is connected to another output side (72
), and the quantized DPCM signal value (
ΔS ) is transmitted. A high-speed DPCM encoder according to any one of claims 1 to 3. (Figure 2) 5. Adder (10)
The first input side (101) of is connected to the input side (71) of the quantization circuit (72), and the second input side (102) of
The quantized DPCM signal value (△511
q), the high-speed DPC according to any one of claims 1 to 3, which is connected to obtain the
M encoder. (FIG. 6) 6. The first calculation unit (C1) includes a multiplier (5), the first input side (51) of the multiplier is connected to the input side (E) of the DPCM encoder, And the prediction coefficient (,4) is input to the second input terminal (52) of the multiplier (5).
is supplied, and the output (56) of the multiplier (5) is the first
It is connected to the subtraction input (12) of the subtracter, the first input (11) of which is likewise connected to the input (E), and the output (13) of the subtractor is connected to the subtraction input (12) of the subtracter. (9) 1st
It is connected to the input end (91), and the output side (
96) is connected to the input side (71) of the quantization circuit (7) and is the second output side of the quantization circuit, to which the quantization error (A1.) evaluated by the prediction coefficient AK is sent. (7
3) is a high-speed DPCM encoder according to claim 2, wherein the subtraction input side (92) of another subtractor is K-connected. (Figure 2) 7. Freely addressable memory (R
OM, FROM) is provided in claim 1.
7. The high-speed DPCM encoder according to any one of clauses 6 to 6. 8. Claim 1, wherein the input side (75) of the quantization circuit (73) is also supplied with the quantization error (Aql) evaluated by the prediction coefficient (A) appearing on the output side (73). High-speed DPC according to any one of Items 7 to 7
M encoder. 9. A high-speed DPCM encoder according to any one of claims 1 to 8, wherein a high-speed multiplication logic circuit (logic array) is provided as the quantization circuit (73). 10. An adder is provided instead of a subtracter,
10. A high-speed DPCM encoder according to claim 1, wherein the complement of the value to be subtracted is supplied to the second input of the adder.