JPS599473Y2 - Balanced DC bus circuit - Google Patents

Description

[Detailed description of the invention] Technical field to which the invention pertains The present invention relates to a bus circuit used as a common line for transmitting and receiving information signals between units in an information processing device, an electronic exchange, or the like.

In particular, the present invention relates to improvements for reducing noise generated in received outputs in bus circuits in which a plurality of units are connected in a balanced pair and DC signals are transmitted and received between the units.

2. Description of the Prior Art Conventionally, DC bus circuits of this type that utilize balanced pairs have been widely used as they are superior in that they are less susceptible to external noise.

Generally, in order to reduce the insertion loss of the transmission line for the transmission circuit connected to this DC bus circuit, inhibit control is used to electrically disconnect the output line of the transmission circuit and the transmission line except during transmission. They are trying to keep me away from them.

Therefore, when all the transmitting circuits connected to one transmission line are inhibited, there is no voltage on the transmission line, which is a DC balanced pair, and the receiving circuit connected to this transmission line becomes uncertain. It may generate noise or send out 0 or l indeterminately as its output.

Purpose of the invention The present invention improves on this by creating a balanced DC bus circuit in which the operation of the receiving circuit does not become uncertain even when connected to the DC bus circuit and all transmitting circuits are inhibited. The purpose is to provide.

Main points of the invention In this invention, a plurality of transmitting circuits and a plurality of receiving circuits are each connected to a balanced pair forming a DC bus circuit, and only one of the power supply impedances higher than the power supply impedance of the transmitting circuit connected between the balanced pairs is connected. The circuit is characterized by a DC offset voltage applied between the balanced pair from two power supply circuits.

Explanation by example This will be explained in detail below using the drawings.

FIG. 1 is a diagram showing the structure of a balanced DC bus circuit according to an embodiment of the present invention.

The inputs of a plurality of transmitting circuits 2 and a plurality of receiving circuits 3 are connected to a transmission line 1 constituted by balanced pairs.

The inputs of this receiving circuit 3 are differential inputs.

A terminator 4 is connected to both ends of the transmission line 1 .

The terminator 4 is generally Y-terminated, with the midpoints of the resistors connected in the balanced pair being further connected to ground by a resistor.

5 is a power supply circuit, and this power supply impedance is the transmission circuit 2.
The impedance of the power supply is higher than that of the output terminal of the transmission line 1, and a DC offset voltage is applied between the pair of transmission lines 1 from this.

In FIG. 1, the circuit from which the power supply circuit 5 is separated at the point indicated by PP' is a conventional bus circuit.

First, the operation of this conventional circuit will be explained using FIG. 2.

FIG. 2 is a waveform diagram for explaining the operation of the conventional example, and a to d are the waveform diagrams for explaining the operation of the conventional example.
The voltage waveforms at points with corresponding symbols indicated by cross marks in the figure are shown.

FIG. 2a shows a signal input to the transmitting circuit 2. When this is high level, the signal is 1, and when it is low level, the signal is 0.

b is an inhibit input of the transmitting circuit 2; when it is at low level, it is inhibited; when it is at high level, it is non-inhibited.

It is now assumed that in time period t1, one transmitting circuit 2 is non-inhibited, and the output of that transmitting circuit 2 is supplied to the transmission line 1.

At this time, signal power a is at a low level, so transmission line 1
Voltages shown as C1 and C2 are sent out from the two outputs of the receiver, respectively, and these are applied to the inputs of all receiving circuits 3 as differential inputs V.

Therefore, as shown in FIG. 2d, the output of each receiving circuit 3 is as follows.
Low level is output.

Next, in time period t2, the signal input to the transmitting circuit 2 becomes high level, and the output of the transmitting circuit 2 is inverted.

Since this signal is sent to the transmission path 1, the outputs of all receiving circuits 3 are inverted, and the outputs become high level as shown in FIG. 2d.

The operation in time period t3 is the same as the operation in time period t1 above. Time period t.

Since all the transmitting circuits 2 are electrically disconnected from the transmission line 1 by the inhibit signal, there is no current in the terminator 4, and the voltage across the transmission line 1 becomes zero.

Therefore, the output voltage of each receiving circuit 3 that receives this pair voltage as a differential input becomes uncertain, and noise as shown in Fig. 2d is generated, or the output voltage becomes uncertain at low level or high level. There are inconveniences such as sending out output.

This point is a problem of the present invention, and according to the present invention, the point PP' in FIG. 1 is connected, and an offset voltage is always applied from the power supply circuit 5 to the pair of transmission lines 1 .

FIG. 3 is a waveform diagram illustrating the operation of the embodiment of the present invention.

3a to 3d also show voltage waveforms at points with corresponding symbols marked with an X in FIG. 1.

Time period t shown in FIG.

In this case, all transmitter circuits 2 are inhibited, and transmission line 1
However, an offset voltage is applied from the power supply circuit 5, and a voltage V' is generated between the pair of transmission lines 1.

As a result, the differential input of each receiving circuit 3 is determined, and a stable low level output is obtained as shown in FIG. 3d.

Regarding the time periods t1 to t3, the detailed explanation will be omitted since the operation is the same as that in FIG. 2.

However, in the case of Fig. 3, an offset voltage is always applied from the power supply circuit 5, but since the power supply impedance of this power supply circuit 5 is higher than the output power supply impedance of the transmitting circuit 2, the transmission line shown in Fig. 3C is There is almost no effect on the voltage of 1.

Practically speaking, it is preferable to prepare one circuit equivalent to the transmitter circuit 2 as the power supply circuit 5, and connect a resistor with a large resistance value in series to its output terminal.

Note that it is preferable for the transmitting circuit 2 and the receiving circuit 3 described above to be integrated circuits from the viewpoint of packaging and economy.

Particularly in practice, while one unit is transmitting, it does not receive at the same time, so each unit has one amplifier in common for transmitting circuit 2 and receiving circuit 3. It is preferable to provide a circuit so that when non-inhibiting, the output is coupled to the transmission line 1 and used as a transmitting circuit, and when inhibiting, the input is coupled to the transmission line 1 and used as a receiving circuit. .

With such a structure, it is possible to further reduce the number of elements and downsize the device.

Description of Effects As described above, according to the present invention, even when all the transmitting circuits connected to the transmission line are inhibited, the differential input of the receiving circuit is stable, and the output is free from noise or uncertainty. No output is generated.

Compared to a circuit that also serves as a terminator for a balanced pair bus circuit and provides a bias voltage, the circuit of the present invention can have a higher power supply impedance, so the power consumption of the power supply is lower and the circuit can be made smaller. It has the advantage of being able to

The hardware for implementing the present invention is extremely simple, and its effects are significant, so it has high utility value.

Despite having multiple transmitter and receiver circuits,
Only one power supply circuit is required to provide the bias voltage, so
The present invention can also be implemented in existing equipment by simply adding a power supply circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is an operating waveform diagram of a conventional circuit, and FIG. 3 is an operating waveform diagram of a circuit according to an embodiment of the present invention. 1...Transmission path, 2...Transmission circuit, 3.
...Receiving circuit, 4...Terminator, 5...
...Power supply circuit.

Claims (1)

[Claims for Utility Model Registration] A transmission line 1 composed of a balanced pair, a terminator that terminates this transmission line, and a means voltage between the pair of transmission lines that is sent out and in an inhibited state, the connection is substantially In a balanced DC bus circuit including a transmission circuit 2 in which the transmission circuit 2 is disconnected, and a differential input receiving circuit 3 in which the pairs of transmission lines are connected to positive and negative inputs, the transmission circuit 2 is separated. The number of receiving circuits 3 is plural, and each output terminal of the sending circuit is connected in parallel between the pair of transmission lines, and the number of receiving circuits 3 is plural, and the differential input of the receiving gas is connected to the transmission line. connected in parallel between the pair of transmission lines, applying a DC offset voltage between the pair of transmission lines, setting the power source impedance to be higher than the output impedance of one of the transmission circuits, and providing it separately from the terminator. A balanced DC bus circuit characterized by having only one power supply circuit.