JPS5993490A - Font display type text editing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

The present invention generally relates to an electronic text display method used in word processors, text editing machines, etc., and particularly relates to text information including character information constituting the text to be output. , 7-ont information that determines the shape of the 7-ont used for a predetermined part of the text, composition information such as line spacing, etc. are all inputted, and the information is displayed on a display device such as a cathode ray tube (CRT).

[This is useful for electronic text typesetting devices. The textual information is stored in 7- an electronic photo plate making device that ultimately produces a negative film that is used to make printing plates in a manner known as the cold process.
composer). The negative film contains the characters of the text to be rendered in the desired 7-ont style and in the desired configuration according to the text information entered into the electronic text typesetting device. For example, [Printext (
Conventional text typesetting devices, such as the PrintText) J device, are limited to one 7-ont style of characters or symbols that can be displayed on a display medium. This has the disadvantage that the user of the text typesetting device, ie, the operator, cannot accurately grasp the actual 7-ont style that will ultimately appear printed on the page. A special symbol is displayed on the display medium, which allows
Although it may be possible to know that the character will ultimately be reproduced in a particular font style, the character actually displayed in the 8-font style on the display medium is still of one font style. . Therefore, when using conventional text typesetting equipment, the operator must use his imagination to determine in which 7-ont the final printed page will be printed. This is an inevitable situation. Furthermore, even if the composition of a single font style displayed on a display medium looks beautiful, when it is printed in the actual font style, it is bound to be disappointing. Compugrapl + i
There is a typesetting device manufactured by C.S. This typesetting machine employs a Brevigny screen which allows one to ascertain exactly the shape and weight of the various fonts as they will ultimately appear on the printed page. However, for this reason, it is necessary to first edit the text data and then compose the type using an ordinary cathode ray tube that can only display a type of 7-ont style. That is, only after editing and composing a page of text can the operator display an image of the constructed data on a separate preview screen prior to electronic phototypesetting. However, the information displayed on the preview screen can no longer be edited or reconfigured on the screen. Therefore, if you don't like what you've edited, you'll need to reproduce it on the original cathode ray tube and edit the page of data using a certain type of character set. Even if the information has been modified and configured using complex procedures, the operator cannot be sure that the configuration is actually as modified unless it is displayed on the preview screen again and confirmed. Not cloudy. Essentials of the Invention The present invention has been made to solve the above-mentioned drawbacks, and provides detailed information on various fonts and weights.
It is an object of the present invention to provide a method with a display screen that provides an accurate image and that allows the operator to edit and configure the information displayed on the screen multiple times. . This is accomplished by storing the characters of multiple font styles as digital information and filling the shape of each character with a unique set of characters in the digital word. The system of the present invention can also be provided with as many text editing configuration functions as desired. In a preferred embodiment of the invention, the display medium comprises a plurality of dots orpixels arranged at predetermined locations in a character cell of constant or variable size.
) to form a desired character. The character cell forms a space on the display medium in which the character is represented, and is preferably partitioned into a grid array consisting of a plurality of pixel positions, each containing one pixel. It's good. Lattice Arrangement-1 By placing pixels only at the selected pixel positions, a nearly desired 11-shaped character can be reproduced on the display medium. Additionally, in a preferred embodiment of the invention, the shape of each character is defined by a unique character group of multiple data words. These data words contain information regarding the location of pixels in the character cell required to reproduce the desired character shape. The number of characters and 7 ont styles reproduced in this way is determined by the number of pixel elements (pixel elements) in the character cell.
The versatility of the method of the present invention is determined by the size and number of elements (1 element) and the size of the 7-ont memory that holds the data words. It is wide. The text editing and composition functions of the present scheme are primarily made possible through the use of bit mapped random access memory (bit mapped RAM), with storage locations that correspond point-to-point with pixel locations on the display medium. It is something that In a preferred embodiment, the system of the present invention also includes a microprocessor that receives r input by an operator via a keyboard.
This instruction is constantly monitored and the entire device is controlled. The instructions entered from the keyboard correspond to information regarding the particular character and 7-ontotile that the operator wishes to display on the display medium. In addition, the keyboard can input information to the microprocessor to enable it to determine the position of the display medium on which the character created by the character hood should be displayed. can. Whenever a new instruction is output from the keyboard, the microprocessor erases the character represented by the character code and the group of characters associated with the 7-ont from the 7-ont memory and replaces it with the display medium on which the character is to be displayed. The data word of the character group is stored in the storage location in the bit write RAM corresponding to the location of . Since the display medium reproduces the pixel information stored in the bit write RAM on its own screen, the operator must first transfer the desired character from the selected font to the appropriate memory in the bit write RAM by the microprocessor. The location stores an appropriate character in response to an appropriate input on the keyboard. : can be brought to an appropriate position on display medium-1]. The shape of a character can be determined by determining the pixel positions in the character cell necessary to reproduce the shape of the character using a unique group of characters, and then storing that information at a desired location in the bit writing RAM. ,
The method of the present invention can perform substantially the same text editing and composition functions as used in conventional text editing and composition methods. In any case, such a text collection composition function itself is well known and is not a feature of the present invention, so the following explanation of the present invention will mainly be limited to the font display. However, depending on the convenience of the explanation, some text editing and composition functions may be mentioned; however, even if they are known or may be developed in the future, the text editing and composition functions are not included in the present invention. can be incorporated into the scheme of the present invention without departing from the scope of the invention. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which the same reference numerals are used for the same parts. The overall system of a font display type text editing device constructed in accordance with the present invention is shown at 10 in FIG. The heart of this method 10 is the micropro sensor 12.
and this is Intel Co
It may be a MicroProsensor of type 8086 from RP, ). Regarding the configuration and functions of this microprocessor, its uses, etc., please refer to Intel's manual dated August 21, 1981 [iPX 86. 88
It is described in detail in the User's Manual J, so it is listed here for reference. In the following explanation, reference may be made to a signal that takes two states, active low and 15-active high, but this signal will be briefly defined. An active low signal is a signal that is set (i.e., output) when it becomes a binary "0" level and is reset when it becomes a binary "1" level. Set when reaching u level (i.e.
output) and is reset when it reaches a binary "0"level; in particular, the former, i.e., an active low signal, is defined by adding a top line to the hail sign.
It is distinguished from an active high signal. (For example, signal D
EN is an active high signal, signal DEN is an active low signal, and so on. ) In addition, the input and output of the component circuit of method 10 are
Active high input and active high output, as well as active low power and active low output, are referred to as active low power (or output). ) = 16- This distinguishes it from an active high input (or output). An active low output will be activated if its input signal is in a binary ``0'' state, whereas an active low output will cause its output signal to be in a binary ``0'' state when it is activated. All inputs and outputs that are not specifically marked as active low are interpreted to mean active high. Microprocessor 12 writes address information to address bus 14 and also writes information to data bus 16. The microprocessor 12 communicates with other component circuits by
It has a common set of input/output ports (AO to A) 9, and these input/output ports are connected to both the address bus 14 and the data bus 16 via an address latch 18 and a transceiver 20, respectively. . When the microprocessor 12 outputs address information to the address bus 14, the binary signal corresponding to the desired address is first sent to the output port A.
1 to A19 (However, due to reasons explained later, output capo) AO
is not used for addressing. ), and then outputs the address latch enable signal ALE to the strobe input terminal STB of the address latch 18. Then, a 19-bit address signal is output from the microprocessor 12 to the address bus 14. However, since the output enable input terminal OE of the address latch 18 is grounded, the 19-bit address signal supplied to the latch 18 remains on the address bus 14 unless a new address signal is input to the strobe terminal of the latch 18. ing. A suitable address latch is commercially available from Intel Corporation as 82820cLa Latch. In the pIS1 diagram, latch 18
Although shown with a single block circuit, those skilled in the art will appreciate that three latch circuit arrangements are required to latch all nineteen output signals from microprocessor 12. This is easily understood. Needless to say, these three latch circuit devices are connected in parallel. The 16 least significant bits of the address signal are output on address lines A1-A16 of address bus 14, and these 16 bits are used to address storage elements 22-28 in Scheme 10. In addition, the three most-first address signals
The - bit is sent via address lines A17 to A19.
The signal is supplied to the decoder 32. This decoder 32 is equipped with eight output terminals 00 to 07 (output terminals 05 to 007 are not used in method 1()),
If there is an input to the address input terminals A O to A2 via the address lines A17 to A19, the output terminals 0() to ()
For example, Intel's [82 () 5 type 0neof
A decoder commercially available as EigbL DecoderJ is sufficient. In the present invention, decoder 32 is adapted to generate the chip enable signal necessary to enable only one of storage elements 22-28 at a given time. Therefore, when the binary signal [000J is supplied to the input terminal of the decoder 32, one terminal OO of its output 19 is set (that is, it becomes a state of 0 level).
However, the remaining output terminals are reset (ie, in the level state). Similarly, binary address signal rO(NJ
is supplied to the input end of the decoder 32, output end 01 is set and the remaining output ends are reset. In this way, the decoder 32 is enabled in response to the address signal, but only the signal E2 is inverted by the inverter 34 connected to the next stage, that is, the output terminal o1 of the decoder 32. The signal becomes E2. Once the appropriate address is output on address bus 14, microprocessor 12 can write data to data bus 16, or read data from data bus 16 and store it in internal memory. This operation can be performed by using the transceiver 2o, but this transceiver 20 is commercially available from Intel Corporation [8286 type 0ctal Bus Transc.
Eiver J and 20- are fine. In the method 10 disclosed here, all the information is 1
Data is transferred in either 1-bit words or 16-bit words. Therefore, only the output terminal AO-A+5 of the microprocessor 12 is connected to the transceiver 2(). Therefore, the data enable signal D[N] is supplied to the output enable input 01E of the transceiver 20, and
If the transfer signal DT/R is in the level state, the 16-bit data output from the output ports AC) to A15 of the microprocessor 12 is transferred from the transceiver 20 to the data bus 16. However, although the data enable signal DE is output, if the data transfer signal DT/R is at the 0 level, the data on the data bus 16-1 is transferred to the microprocessor 1.
2 ports AO to A15 and read into the internal memory of the microprocessor 12. 8286 mentioned above
Since the type transceiver is an octal transceiver, two of these transceivers must be connected in parallel to process a total of 16 data bits. The microprocessor 12 includes software stored in a program read-only memory (ROM) 22;
That is, the operation of method 1 ( ) is controlled according to the program. This program, which will be described later in the flowcharts shown in FIGS. 5 through 7, is stored in the ROM 22 in the form of machine language as a plurality of 16-bit words. The microprocessor 12 is configured to sequentially execute various program steps while periodically obtaining new program instructions from the ROM 22 at intervals determined by clock pulses generated by a clock signal generator 36 of the system. Each time microprocessor 12 requires a new program instruction, the aforementioned address signal corresponding to the storage location of the desired program instruction is output on lines A1-A16 of address bus 14, and decoder 32 outputs the chip enable signal. E1 is output, and at the same time, a read signal [<[) is output. As a result, a 16-bit word containing the desired program instruction is retrieved onto data bus IG. 5-16 bit word is microprocessor]2
is read into the internal memory of the transceiver 2 (). Although any type of memory may be used, an 8Kx8LIV erasable programmable ttohq, such as the one commercially available from Intel Corporation as [2-64 type PRC) Ml, is suitable. Since each FROM can only store 8 bits of information, two FROM
M are connected in parallel so that one address signal output from the microprocessor 12 is applied to the address inputs of both F'ROMs, so that each PR
The 8-pit output 77 from the OM is combined with each other to form a 16-bit word -1- which is output to the data bus 6. According to the program instruction 1 stored in the PR(-)M22, the microprocessor sensor 12 inputs the input device fP?( to the display device (preferably a CRT) 4(1).
Preferably, the shape of a character of a specific font generated by the character code generated by the electronic keyboard 38 is displayed. The resolution of the displayed character shape is then sufficient for the operator to see the same image as it will appear on the final printed page. For this purpose, each line of the CRT 40 must be 800 to 11
It is preferable that it be capable of resolving 800 to 1100 lines divided at 00 pixel positions. Each pixel (pi
In order to make each character consisting of a combination of pixels appear smooth and continuous, it is better to have a smaller diameter (preferably, the diameter of the ogre is 0.01 inch. , the CRT40 has one line per line.
It is divided into 1024 lines having 024 pixel positions. In other words, it has 1024 scanning lines. The raster configuration of this CRT 40 is schematically shown in FIG. 2, where each square 42 in FIG. 2 represents one pixel position. Needless to say, and as is well understood by those skilled in the art, the grid lines shown in FIG. ``Convenience'' 2. The grid lines are simply inserted intentionally.Therefore, as far as I can see in Figure i12;
You can see the RT40 area. Therefore, electron beam or CRT
As the surface of il is scanned, the electron beam is modulated to excite only the corresponding pixel location 42. The pixel position 42 excited in this manner forms a desired character by emitting light (fluorescence) as shown as a pixel 44. In the illustrated embodiment, a CRT 4. (l is 64
It is divided into character cells 46 of columns and 64 rows, and the size of each character cell 46 is such that it has an area including 16 pixels in the width direction and 1G pixels in the height direction. selected. Therefore, since one character is formed in each character cell 46, 64×G 4 =4096 characters are displayed on the entire screen of the CRT 40. This is one page of text. Although disclosed as character cells 46 always having 16×16 pixels, the invention should not be so limited; rather, each character cell 46 may be wider than shown, or even narrower. It's good. For example, each character cell 46 may be composed of 20×16 pixels or 28×18 pixels, and further,
For the first character, the character cell consists of 20 x 16 pixels, for the next character, it is 28 x 18 pixels.
It may also be displayed in a character cell made up of pixels. Another method is to keep the size of the character cells constant, but the characters that are actually displayed may be displayed using a portion of the pixels that make up each character cell, or pixels that exceed the frame. . Although various modifications to the structure of the character cell will require a more complex structure than in the preferred embodiment, it is undeniable that one skilled in the art can easily think of one.
The character is displayed in a predetermined character cell 4G, using the pixel positions 42 forming the predetermined character cell. The particular pixel location 42 used to form the desired character is 1 of 16 bits lft.
It is defined by a six-pinary word group (hereinafter abbreviated as a data word group). Each group of 16 data words defines the shape of the character to be displayed and will be referred to as a character group in the following description. fjS, '1A and 3B, the individual words of the character group and the pixel position 42 in the character cell 4G are shown.
Indicates the relationship between In Figure 3A - for example, 1
"S" is shown displayed in one character cell 46. In FIG. 3B, the 16 data words of the character group defining the letter "S" are shown. As shown in FIG. 3A, "S" is displayed. It can be seen that S'' is formed by several of the pixels 44, one at pixel location 42. There is no pixel 44 in pixel row 0 of character cell 46, so data word 1 (the Figure 3B) is binary 2
7- The number “0000000000000000”. Coming to the next pixel row 1, data word 2 is stored as "000000111iooooooo" since there are pixels 44 in four pixel positions 42 corresponding to pixel columns 6, 7, 8 DEG 9. Similarly, data word 1 is set such that the 16 data words of the character group contain all the information necessary to display one character in each character cell 46.
The sequence is performed up to 6. In this way, any type of character will be represented by a unique set of 16 data words of 16 bits in length. As mentioned above, the shape of the character that should not be displayed on the CRT 40 is determined by the 16-word character group, or the shape of the character to be displayed is determined by the 7-ont R
, is limited only by the size of the OM memory 24 and the resolution of the 16x16 pixel character cell. Therefore,
By simply inputting an appropriate command into the input device 38, CR
Not only can the T40 be used to display characters in any desired 7-ont style, but it also provides great versatility, such as being able to store various font styles. It is. Once the operator of the device 10 has entered the desired characters, the next step is to rearrange the positions of the characters on the CRT 4 (I J-) by using the text m collection function. The same character image that is printed as a vane is formed. Let us take an example to explain the case where the operator calls the following sentence: 5HER'1 in Hebrew is * In this example, Characters of two types of fonts (thick Roman font and Hebrew 7-ont) are stored in ROM in advance.
24 to CRT4.0. After inputting this text data, the operator
Suppose we want to distinguish that word from the rest of the sentence by representing it in a different 7-ont style. In this case, as will be described later, the method 10 is operated to replace the bold Roman 7-ont character representing the word "814EM" with another 7-ont character, for example, a cursive Roman 7-ont character. This is in bold type [s
I-(Achieved by writing the cursive print [sNiMJ where EMJ is. As a result, the following sentence is expressed on the CRT 40. SHE/'I fn Hebrevvis is O'L)
, ) In the following explanation of method 10, the 7-on) ROM 24 contains three types of 7-on, for example, Roman 1 (
Roman 2 (for cursive Roman letters), and Hebrew (for Hebrew) were given the names 7.
Let us assume that the ont is memorized. However, instead of just these three types of 7-onts, it is also possible to store more 7-onts or different 7-onts. In the illustrated embodiment, each seven-ontostyle has a total of 128 characters, including uppercase and lowercase letters, punctuation, blank spaces, and other characters to be displayed on the CRT 40. The font of Roman 1 is the 1st style, that is, the σ-maji type necessary to express English in bold type, and the font of Roman 2 is the 2nd style, soku9, cursive type. IJ: The Roman typeface needed to express words. And suppose that the Hebrew 7 ont has a strange typeface to represent the Hebrew 8ti in the desired style. In any 7-ont, each character is assigned a unique character food, which allows r<
The address positions of the 16-fold character group specifying the characters in oM;z are shown. tiif
As mentioned above, each of the 7 onts has +284 characters or 3 characters, so 128×3=384 character hoods are required to process all the fonts. This hood can be represented by 52 9-bit binary words. For example, ', a lowercase letter in the Roman 1 font [a-1 has the character code rob
(In binary, "(1(1(1(1(1(-1(100J)
), and the lowercase letter [1) 1 is the character food “1
” (Give the code in binary as “0=31-+300 (,+00014).” For Roman 2, it is the lowercase letter “a.”
If so, the character code [128J (binary "
01, 00000 (1 (Monday), character code [129J (binary [ol, oo
oo. Furthermore, in Hebrew fonts, the lowercase Hebrew letter equivalent to "aleph'" has the character hood "256" (11 in binary).
QOOOOOOOOJ) The lowercase Hebrew letter corresponding to "bet" is given a hood, such as the character code r257J (l'-100000001J in binary). Continuing the explanation with the above settings, when storing the 16 words of each character group in the ROM 24, it is preferable to store the characters in the order of the hail character code. Specifically, the 16-word character group corresponding to the 7-ont lowercase letter raJ of Roman 1 is:
At address positions 0 to 15 of the ROM 24, the 16-word character group corresponding to the lowercase letter rbJ is the same <
To 1632-; (Memorize 1 address t. Then, the 128 characters in all Roman 1 fonts are 0N124 + 28 x 16 = 21 - 1.18 address signal position (+) 204.7). Even if the characters are written in Roman 2 font or Hebrew font, they occupy the same number of address positions. 40ri6・～4
It is number 111. That is, the lowercase letters Ja, -l and 167-to' characters corresponding to Roman 2's 7-ont characters are located at addresses 2 (1/l 8 to 2053 and 2 () 54 to 206',), respectively. , lowercase Hebrew 7-ont letters [alel+I+l and I' l)e I
The 16-word character groups corresponding to : , , l are stored at addresses 4.096 to 4111 and 4112 to 4127, respectively. The 128 characters of the Hebrew font are recorded at addresses 4096-6]□-13 of ROM24!
be done. The 9-pinto character code corresponding to the address position in the ROM 24 of the 16-word character group is
! 38. This input device 38 may be of any known type, and in this embodiment an electronic keyboard is used. It is also possible to use other input devices, such as those using menu selection methods or voice-responsive input devices. The keyboard 38 is described in a pending application filed on October 1, 1982, with application number M-9760, named 7-ont display and editing system, which has the feature of overlaying characters. preferable. This keyboard 38 is provided with character keys and command keys. The character keys are used to input characters to be displayed on the CRT 40, and the command keys are used to specify the 7-ont character to be displayed, and perform normal functions such as cursor movement left and right, carriage return. , and is used to command functions such as backspace. When a character or command key is pressed,
”1 Keyboard 38 is a ROM displayed on CRT 40
1: to output either a character code that specifies a character of 24 or an instruction code that specifies information on a bet command to be executed. Preferably, the keyboard information is an 11-bit word having a 2-bit 7-bit block with an f]-bit data block. -1- The 7 omat block specifies a data block of keyboard information regarding instruction code or character food. 1. When the 9-bit data block is an instruction code, it specifies the particular instruction code to be executed by the microprocessor sensor 12. When the above 9-bit data block is a character food, it is
Specifies a particular character that should be displayed. As described in the ongoing publication W4 document (M-9760), the operator or user' must first press the 1 or 2 command key pointing to the 7 font of the character to be used, and then press the CRT 40 Press the appropriate character key to display the desired 7-ont character selected. Whenever the user wishes to change the font style of subsequent characters represented in CR35-T2O, the user presses one or more command keys that specify the new 7-ont to be used, and then presses the appropriate character key to display the desired font on the screen. Insert the character. Microprocessor 12 activates keyboard latch 3 to determine whether new keyboard information has been entered.
The output of the keyboard 38 is constantly monitored by causing the decoder 32 to periodically generate a chip enable signal to strobe 0. Keyboard latch 30 receives 11 bits of keyboard information originating from keyboard 38 and connects data bus 16 whenever it is strobed by enable signal EL.
output to data lines AO to AIO. Latch 30 is formed from 8282 octal latches connected in parallel. When the data block of keyboard information is a character food, the microprocessor 12 determines that the 16 word character specified by the character code is R.
It is determined where in the OM 24 the 16 words of the character group are placed in the random access memory (RAM) for display. Then, the display RAM 26 stores this character in a suitable character cell 4 of CRT 4.0.
6. As previously mentioned, each data word of each character code stored in ROM 24 is 16 bits long. A commercially available font ROM 24, such as that described for programmable ROM 22, is capable of storing such data words at sequence addresses. When microprocessor 12 reads a data word of a selected group of characters from ROM 24, address bus 14
An appropriate address signal is output to lines A1 to A16 of the decoder 32, which outputs an enable signal E4 to the microprocessor 12.
A read signal RD is simultaneously outputted from both. Thereby,
A 16-bit data word appears on bus 16 and is read into the internal memory of microprocessor 12. This data word is then output to the appropriate display RAM 26 by outputting the appropriate address signals on lines A1-A16 of bus 14 and placing the data from ROM 24 on lines AO-A1.5 of data bus 16. is transferred to a storage location. At the same time address and data information appears on address and data buses 14 and 16, microprocessor 12
The decoder 32 is caused to output the chip enable signal E5, and the microprocessor 1
The write signal set (is also output from 2. In this case, R
AM26 sends the 16-bit data word on bus 16-hi to
The data will be read into the address storage location specified by the address signal on bus 14. It is necessary for the microprocessor 12 to read specific data from the display RAM 26 when the microprocessor 12 is ready. This can be achieved by outputting two read signals RD simultaneously. As shown in FIG. 4, the display RAM 26 includes a CRT 4
(i J2 pixel position 44 corresponds to 1,020
<l, (Divided into 124 pixel positions 44゛.Pixel-inclusive display RAM, CRT display device, and pixel information stored in the display RAM is displayed on the display device. Image Automation I: (Tm
There is an rGMDM-1 (100-inch bit-writable high-resolution CRT display device) manufactured and sold by AuLomation+ Inc.
16 bits at a time to the display RAM 26! be included. Therefore, RA for display at 16 consecutive pixel positions 44°
One address position of M26 is determined. Consecutive address locations are adjacent to each other in a pixel row. Therefore, address address 00000 is the first storage location in pixel row 0, address address 00101 is the first storage location in pixel row (
), and so on. Since the partition width of RAM 1G corresponds to 1,024 pixels, and the length of each data word corresponds to 39-16 pixels, each pixel row of RAM 26 has
This means that data words at addresses 000-06300-063 are stored. The 64th data position is 63-1
It is the leftmost position of pixel row 1 storing 64 data words at address location 27. Similarly, RAM
64 pixels in each row of 26 pixels (each row has 1,024 pixel positions)
The data word will be stored. The storage space of the RAM 26 is logically divided into 46 character cells, which are
There is a one-to-one correspondence with 40 character cells 46. In other words, character cell 4 in the upper left corner of RAM 26
6' corresponds to the character cell 46 in the upper left corner of the CRT 40. If you follow this protocol, the RAM
Character cell 46' in the upper left corner of 26 is CR
A group of 16-word characters will be stored that define the character to be displayed in the upper left corner of T40. The 16 data words of the character group are stored in RAM 26 at 0.
64,128,192...1.040-24 is stored at the storage location. Appropriate bias signals (for example, vertical synchronization signal, horizontal synchronization signal, data flow, etc.) are automatically supplied to the CRT 40 from the display RAM 2G, so the CRT 4.0 must be stored in the RAM 26. Certain character information can be displayed. Therefore, RAM2
As information is written to CRT 6, that information is written to CRT 40.
- is also displayed. To clarify the specific character cells 46, 46' in CRT 4') and RAM 2G, CR
Logically, T40 and RAM26 have 64 cell rows and 6
It is divided into 4 cell columns. In Figures 2 and 3,
Like the cell rows, the cell columns are also numbered from 0 to 63. Therefore, each character cell 46,46' has coordinates. For example, the letter "S" shown in FIG. It is displayed in . Character cell 46 in which the next character to be written by the character code output from the keyboard 38 should be placed.
are referred to as "active" character cells. Microprocessor 12 then continues to track the location of the active character cell by storing cell row and cell column pointers CR, CC in scratchpad RAM 28. This is signaled to the operator by bringing the cursor 48 to the active cell. In the illustrated embodiment, cursor 4
8 is in the form of an underline formed by the lowest pixel 44 in the active cell 46, as shown in FIG. This cursor 48 is moved by the microprocessor 12 one character cell at a time to the right every time a character code corresponding to a character to be entered into an active cell is output from the keyboard 38. Eventually,
When the cursor 48 is positioned on the last character cell 46 in a row, the cursor 48 is shifted by the microprocessor 12 to the left character cell 46 in the next row of cells. Further, in the illustrated embodiment, the position of the active cell, that is, the position of the cursor 48 can also be moved to the left or right in response to a cursor left command or a cursor right command. Also, if desired, it may be changed so that a one line command or a cursor down command is output to the cursor.
Other cursor movements such as those used in conventional text editing and composition devices and word processors may also be provided. Therefore, when changing the position of the cursor in response to a command to the right of the left cursor, cursor 4
8 only moves, and the character pointed to by the out-of-place cursor 48 in the character cell 46 does not move accordingly. However, if this cursor 48 is moved in response to a space or backspace command, the character cell 46
The character pointed to by the cursor 48 is erased by the microprocessor 12. Furthermore, the position of the cursor 48 is
In this case, the cursor is moved by the microprocessor 12 to the left character cell of the next cell row. Even if the cursor is moved to a new character cell 46 in this way, it is possible to prevent the character stored in that cell 46 from being deleted. As previously mentioned, microprocessor 12 continually strobes keyboard latches 30 to determine whether another instruction has been output from keyboard 38. New character information is loaded by microprocessor 12 into display RAM 26 and/or cursor 4B is moved in response to this keyboard information. microprocessor 12
is the text buffer and scratchpad RAM2
Each data word corresponding to a character code produced by 8 is stored in a memory location corresponding to the character cell 44-46 of the character identified by the stored character code. In this manner, text buffer and scratchpad RAM 28 contains character code information corresponding to all characters stored in display RAM 26. This text buffer and scratchpad RA
An appropriate memory is used as M28, but the product name is 2186RAM,! An 8,192.times.8-bit integrated RAM marketed by Intel Corporation is preferred. The two 2186 RAMs are connected in parallel since each 2186 RAM stores 8-bit words and microprocessor 2 outputs 9 or 16-bit words to RA 28. The address input terminals of both 2186-type RAMs are address bus 1.
The data output terminal of each RAM is connected to the data line A (
1 to A7, and the data output terminals of the remaining RAMs may be connected to data lines 88 to A15 of the data bus 16. The information stored in the RAM 28 can be displayed in R for display as needed.
It can be used to switch the memory contents of AM26, that is, to perform a +77 retrieval. Moreover, if all the information of one page is stored in the display RAM 26, it is necessary to erase it in order to input the information of the next page. In this case, the character code stored in the RAM 28,
That is, one page of information to be erased may be transferred to a large capacity storage medium for permanent storage, such as a floppy disk or a hard disk. By doing so, it is possible to store character code information for many pages in a large capacity storage medium. Needless to say, information stored on mass storage media can be recalled at any time and transferred to an optical typesetter that produces photo negatives for printing plates. This optical type setter, known as a 7-ont setter, contains font information corresponding to the 7-ont information stored in the ROM 24, so the characters copied by the 7-ont setter are identical to those displayed on the CRT 40. They can have substantially the same shape. R
The transfer of information from AM 28 to mass storage media is well known to those skilled in the art and will not be discussed here for convenience. Just to be sure, as an example, the "System Data Catalog (Sysl, em Data Catalog)" published by Intel Corporation in January 1982.
The transfer of information between RAM 28 and mass storage media is described in Caj, alog)J. As mentioned above, the least significant bit (output cap) AO of the address outputted by the microprocessor 12
bits output to address bus 14) are not output to address bus 14. As a result, the addresses entered into memories 22-28 are equal to the addresses created by microprocessor 12 and split in two. The reason for this somewhat unusual arrangement is due to the special structure and capabilities of the 186-type microprocessor, as detailed in the [1APX86.88 User's Manual]. The 8086 microprocessor can access 8 or 16 bits of memory information at a time. Therefore, for the 8086 microprocessor to recall the storage contents of a 16-bit word during a single bus cycle, Output port A-A
It is necessary to output an even number address (ie, 2, 4, 6°, . . . ) to 19. However, when outputting an odd number of addresses, the microprocessor must access external memory one byte (8 bits) at a time over two bus cycles. In method 10 of the present invention, 1-byte addressing is unnecessary, and if 1-byte addressing is used, method 1
Since 0 is complicated, a microprocessor that outputs even-numbered addresses is sufficient. Although it is desirable for the microprocessor 12 to output even-numbered addresses in this way, it would be a waste of money if the odd-numbered addresses of the memories 22 to 28 cannot be used. However, the problem with this wasteful use is that the address line AO (microprocessor 1
Port where the least significant bit of the address from 2 is output)
This problem can be solved by not connecting the atto 48-res bus 14. In this way, the even numbered addresses will be output from the microprocessor 12, but the even numbered addresses will be supplied to the memories 22-28 of the system. Therefore,
Address 2.4 output from microprocessor 12
,6. The deceased... has address 1 on the address bus 14,
2, 3, 4... are applied. 7 programs stored in the programmable ROM22
The operation of Scheme 10 will now be described with reference to FIGS. 5 through 7, which are shown as 0-charts. In addition, 5th A,
Figures B and C are main programs, and Figures 6 and 7 are subroutine programs. The main program is instruction step 10
(Start with +. Step 1 of this instruction
At 00, the microprocessor 12 controls the display RA.
M26 and text pan 7 ask padded RAM2
8 is cleared, and at the same time, the character code previously stored in the RAM 28 is transferred to the external mass storage medium. As mentioned above, the information transferred to the external mass storage medium will eventually be recalled and transferred to the typesetter. In any case, once RAM 26.28 is cleared in this way, proceed to the next step 102,
Cell row pointer CR and cell column pointer CC are set to zero. These pointers CR and CC define the character cell 46 located at the upper corner of the CRT 40 as the active cell. Thereafter, in step 104, the cursor subroutine 200 (FIG. 6) is instructed to execute and then return. This subroutine 200 causes the cursor 4
8 is active cell 4 indicated by pointers CR and CG
I am made to come under 6. Specifically, in FIG. 6, in step 202 of subroutine 200, microprocessor 12 calculates and sets register B therein as follows. To HE B =lCRx64xl 6+64X+
5+CC]2... (1) Each cell row of formula l≧A M 2 G has 64 X I 6
= I (Is there 124 memory locations?) In term 11 of formula (1), character cell 46 of RAM 26 corresponding to active character cell 46 of CR""/I O
The address of the last data word of is determined. This address requires that the address output by microprocessor 12 be twice the address appearing on address bus 14 (in this regard, the least significant bit of the output address of microprocessor 12 is either output port AO or address latch 18). (Remember that it is not connected to the address bus 14, so it is not supplied to the address bus 14.)
2 and Kake are interposed. When the above calculation is completed, steps 202 to 2C
) 4, address DRADr) = REGr', /
2, the data word stored in the RAM 26 is read out, the word is inverted, and then the data word stored in the RAM 26 is read out again.
Write 51- to address REGB/2. As a result, the cursor 48 is brought to the left of the CRT 40 under the "Nicona" character cell 46. At that time, microprocessor 12 resumes the main program. Returning to FIG. 5A, upon completion of subroutine 200, the process proceeds to step 1.06 to determine whether keyboard information has been entered from the keyboard. microprocessor 12
makes this determination by periodically strobing the keyboard latches 30. When microprocessor 12 determines that a data word has been created by keyboard 38, it proceeds to step 108 and determines whether the 9-bit data block of keyboard information is an instruction code. This is done by examining a 2-bit 7-bit block of keyboard information. if,
If it is an instruction code, microprocessor 1
2 proceeds to step 128 shown in FIG. 5B. In this case, microprocessor 12 follows the various programs shown in Figures 5B and 5C to move the cursor in a manner determined by the instruction code. If the keyboard information is not a command hood, it must be a character code specifying the character displayed in the active character cell 4G. When the keyboard information is not an instruction food, the microprocessor 12 proceeds to step 110 and registers an internal register A.
Set equal to the character code set in the keyboard information data block. The code specifies the location in ROM 24 for the group of characters representing the character specified by this hood. The microprocessor 12 then performs step 112
Then, with the text buffer address in formula (2) below, write the text buffer and the flap parameter RAM.
The character code is stored in 28. TB ADr) = CRX64 + CC (2) There are 64 cell rows in the Musha cell column, so the above calculation can be done using the keyboard 28.
At the address location where the character code specified by corresponds to the special character cell 46,
8 to be memorized. The character specified by this character code is displayed on CRT 4.0. Now, suppose microprocessor 12 proceeds to step 114, goes to subroutine 300, and then returns to the main program. The display character subroutine 300 is shown in FIG. 7 and associates the character with a character code specified by the keyboard 38 and entered into the active character cell 46 of the RAM 26. This causes characters to be displayed one after the other in the active character cell 46 of CR,T 40. In FIG. 7, the microprocessor 12 first proceeds to step 302 and sets the following number in the internal register B of the microprocessor 12. REG B=REGAX16X2 Equation (3) The result of this calculation results in a numerical value stored in register B corresponding to the address location of ROM 24. Above ROM2
4 stores the first data word of the character specified by the character code specified by the keyboard 38. Note again that the multiplier 2 is used in equation (3) to ensure that the address created by the microprocessor 12 is twice the address created by the ROM i2. be. The microprocessor 12 then performs steps 30,
1 and sets the next value in its internal register C. R[・”, G=CRX64XI 6X2+CCX2(7
1) Since each cell row of formula display RAM M 26 has 64 x 16 address positions, formula (4) is the display RA for the data word of t51 of active character cell 16.
Identify the address in M2G. Further, the address created by the microprocessor 12 is twice the actual address signal given to the display RAM 2G. This is because the lowest address of the address generated by the microprocessor bus 12 is the address bus 1.
55- Because it is not given to 4 and given to 55-. Microprocessor 12 then proceeds to step 306 and sets incremental pointer IP=O. This value is stored in the appropriate storage location. Next, proceeding to step 308, the microprocessor 12
is 7 on as shown below) 7 on at ROM address) ROM2
4 and stores the word in internal register D. FRADI)=REG B/2+IP (5) "The above incremental pointer IP is zero."The microprocessor 12 determines whether the incremental pointer IP is zero or not. is read into register D from ROM24. Microprocessor 12 then proceeds to step 310 and displays the word stored in register D for display in R,A.
Write to M26 with the next address. 56-nRAI')l')=l-? l':G C/2
+ T PX34 (6) type incremental pointer IF'1'8 (Since it is written, the data word stored in the microprocessor 121 and register 1') is transferred to the display RAM2.
G is written with the -1- RAM address corresponding to the first address of the active character cell 46'. Proceeding to step 312, microprocessor 12
increments the incremental pointer by one and then proceeds to step 314. If the incremental pointer is less than 16, the microprocessor 12 returns to step 308 and reads the data stored at the next address in the ROM 24 into the register D (now the incremental pointer H' is equal to 1 but 6). . This data word is then read into the second storage location of the active character cell 46' and the incremental pointer is again incremented by -. This process is such that the 16 data words of the character group corresponding to the character hood created by the keyboard 38 are RO
This is repeated 16 times until the data is stored in the 16 storage locations of the active character cell 46' of M26. At the same time R
AM26 causes this character to appear in active character cell 46 of the CRT 4.0. After microprocessor 12 has performed steps 308-312 sixteen times, microprocessor 12 returns to the main program. Returning to the $SA diagram again, microprocessor 12 proceeds to step 116 and increments cell column pointer CC by one. Proceeding to step 118, microprocessor 12 determines whether the cell column pointer is equal to 64. If there are fewer than 64, microprocessor 12 proceeds directly to step 126. If the cell column pointer above is equal to 64, this means that the cursor is
Refers to the fact that it must be reset to the leftmost character cell 46' of the next cell row, away from the right edge of RT 40. Finally, microprocessor 12 performs step 1
20, where the cell column pointer is set to zero and the cell row pointer is incremented by -. The microprocessor 12 then proceeds to step 122 and asks, ``Is the cell row equal to 64?'' 11 I refuse. If it is 64, this means that the attempt has dropped the cursor below the bottom edge of the CRT4 (l), which is a useless condition.
The microprocessor 12.1 emits a signal tone (this can be done in any known manner). and,
It alerts the user of the device Ft.10 to an incorrect condition. The microprocessor sensor 12 then proceeds to step 125 and resets the cursor row and cursor column points at 63 to move the cursor 48 into the "-" cell.
47F% (see step 126). after that,
The program returns to step 106 where the microprocessor waits for other keyboard information to be entered via the keyboard. If there are fewer than 64 in cell rows, the microprocessor 12 proceeds to step 126 to the 59-subroutine 200 and returns. As a result, the cursor appears at the bottom of the active character cell 46 specified by the cursor matrix pointer. In this respect,
Microprocessor 12 returns to step 106 and awaits additional keyboard information generated by keyboard 38. Referring now to Figures 5B and 5C, the manner in which microprocessor 12 responds to instruction codes generated by keyboard 38 will now be described. After the microphone ty 7' o processor 12 determines that the keyboard information produced by the keyboard 38 is an instruction code (step 1
08), the microprocessor 12 proceeds to step 200, executes subroutine 200, and returns. This causes the cursor 48 to be removed from the active character cell 46 identified by the cell matrix pointer. Proceeding to step 130, the microprocessor processor 12 determines whether the keyboard information is a cursor right instruction code. If so, then microprocessor 12 performs step 132
Go to and increment the cell column pointer by one. Proceeding to step 134, microprocessor 12 determines whether the cell column pointer is equal to 64. if,
If it is equal to 64, the 1-mark cursor 48 is not moved further to the right in the current cell row. Rather, it must be moved to the leftmost character cell 46 of the next cell row. Finally, microprocessor 12 sets the cell column pointer to zero and increments the cell row pointer by one, as shown in step 136. If the cell column pointer is less than or equal to 64 and has been reset according to step 136, the microprocessor 12 proceeds to decision step 138 and determines that the cell row pointer is less than or equal to 64.
Determine whether it is equal to or not. If it is equal to 64, this means that an attempt will be made to move the cursor 48 to the CRT 40.
It means that it was done in order to move it from the bottomed side. Since this is an invalid condition, microprocessor 12 generates an alarm signal (see step 140), sets it in the cell column pointer 63, and empties one cell row pointer (see step 142). This has the effect of moving cursor 48 to the last cell column of the last cell row of CRT 40 as soon as microprocessor 12 proceeds to step 144 . If the above cell row pointer is not equal to 64 (
(see step 138), microprocessor 12 proceeds to step 144 and positions cursor 48 at the bottom of active character cell 46. Returning to step 130, if the microprocessor 12 determines that the keyboard information is not a cursor right instruction code, the microprocessor 12 proceeds to step 146 to determine whether it is a cursor left instruction hood. If so, the process proceeds to step 148, where the cell column pointer is decremented by one. Microprocessor 12 then determines whether the second column pointer is less than zero (see step 150). If this is not the case, the process advances to the microblock 121 step 152 and places the cursor 46 at the bottom of the active character cell specified by the modified cell column pointer. At this point, the program returns to step 10G, where microprocessor 12 awaits the next data word generated by keyboard, 38. Returning from step 1501, if the cell column pointer written in - is less than zero, this means that the first color is at the cursor,
This means that you are trying to move the cursor 4) from the left edge of the CRT 40.
must be moved one cell row and must be moved to the rightmost column. At the end of this, the micro processor 12 resets the cell column pointer to 63 and decrements the cell row pointer by -1 (step 15).
4). Proceeding to step 15G, the microprocessor 12 determines whether the cell row pointer is less than zero.
cut off If it is less than zero, this means that the attempt is 1-
4. Move the cursor to the CRT. This means that an attempt has been made to move the cell line 63- from the cell row at the top of l. Since this is an inappropriate condition, the microprocessor 12 moves as shown in step 158. It issues an alarm signal, resets the cell column pointer to zero, and increments the cell row pointer by one. At this point, the program returns to step 106, where microprocessor 12 waits for the next keyboard information issued by keyboard 38. Returns to step 156, where the cell row pointer is less than zero. If not, microprocessor 12 performs step 1
Proceeding to 62, the cursor 48 is placed at the bottom of the character cell 64 specified by the cell row and column pointers. The program then returns to step 106 where microprocessor 12 waits for the next keyboard information generated by keyboard 38. Returning to step 146 (see FIG. 5B), 64
- The microprocessor 12 determines whether the keyboard information is a cursor left interrupt signal f:11 and proceeds to step 164 as shown in FIG. 5C. From step 164, the microprocessor 12 determines whether the keyboard information is a carry return code. If so, microprocessor 12 proceeds to step 166 and determines whether the cell row pointer is equal to 63. -1- If the cell row pointer is equal to 63, a carriage return instruction code is attempted to place the cursor 48 on the bottom edge of the CRT 2O. Since this is an incorrect state, the microprocessor 12 assumes that 'iEL<
To alert the user of the absent condition, an alarm signal is generated, as shown in step 168. Since cursor 18 was moved in step 128, it must now be replaced. In this final step 172, microprocessor 12 makes two passes through subroutine 2 o o and returns. Otherwise, microprocessor 12 returns to decision step 10G where it waits for the next keyboard information generated from keyboard 38. - If the cell row pointer is less than 63, microprocessor 12 proceeds to step 170 and sets the cell column pointer to zero and increments the cell row pointer by one. Or muttering microprocessor 12 is step 17
2, so that the cursor 48 is placed in the first character cell 46 of the next cell column. Otherwise, the murmur program is returned to step 106, where microprocessor 12 again awaits the next keyboard information from keyboard 38). Returning to step 164, if the microprocessor 12 determines that the keyboard information is not a carriage return instruction code (it has already been determined that the keyboard information is not a cursor left or right instruction hood), the apparatus disclosed herein Since there are only four commands, this keyboard information must be the backspace command code.) At step 1 and step 2, the microprocessor 12 determines whether the cell row and column pointers are both zero. If so, backspace ω
The order is an inappropriate order. In such a case, microprocessor 12 issues an alarm as shown in step 176 and as shown in step 178, the microprocessor 12 issues the CII T 4 ('
The cursor 48 is placed at the bottom of the character cell 46 located at the upper left corner of the cursor 48. Or whisper-1
- The program returns to step 1' - 6 and the microprocessor again waits for the next keyboard information issued by the keyboard 38. Returning to step 174, the character points of the cell row and cell column are If both are not equal to zero, microprocessor 12 proceeds to decision step 180 and determines whether the cell column pointer is equal to zero. If not, microprocessor 12 proceeds to step 1) 32. Decrement the cell column by one, step 136, as shown.
Proceed to. If the cell column pointer is equal to zero, the cell column pointer=67- is reset to 63 and the cell row pointer is decremented by one. See step 184. This has the effect of moving the pointer to the right-most edge of the next higher row. Since the backspace instruction deletes the newly stored character in active character cell 46, microprocessor 12 proceeds to step 186 and sets internal register A for a blanking character code. Proceeding to step 188, microprocessor 12 jumps to character subroutine 300 and writes a blank to the new active character cell 46. The microprocessor 12 then proceeds to step 190 and goes to the cursor subroutine 200 to move the cursor 4
8 will be placed at the bottom of the active character cell 46 specified by the most recent cell column and cell row pointers. The program then proceeds to step 106 where microprocessor 12 waits for additional keyboard information to be generated by keyboard 38. 68- In this specification p1), the term alphabetic characters is understood to include alphanumeric characters as well as ideographic characters. This invention can be implemented in the form of a pond without departing from the spirit and essence to which it belongs. Therefore, the criteria for determining the scope of the invention should be determined from the claims, including their dependent forms, rather than from the foregoing embodiments. It should be rejected.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the hardware for the 7-ont display and text editing system of the present invention, FIG. 2 is a schematic diagram of the CRT shown in FIG. 11, and FIG. A diagram showing the characters
! Figure 3B is a diagram showing the binary words used to identify the characters shown in Figure 3A, Figure 4 is a diagram schematically representing the display ram of Figure 1, Figure 5A, 5B and 5C are flowcharts showing the main program stored in the program ROM of FIG. 1, and FIGS.
The figure is a flowchart showing a subroutine stored in the program ROM of FIG. 12...Microprocessor, 18...Address latch, 22.24=・ROM, 26.28・, -RAM
. 30...Latch, 32...Decoder, 38...Keyboard, 40...CRTo Patent Applicant: High Technology Solutions, Inc. Agent: Patent Attorney: 2 people mentioned above - T go 5.3
A. m=u=2-3f3-wa-g/: 00000000000000002
: 000000 1 1 1 +0000003
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ooooo. /:0O00111000111000s: oooo
+ + oooooo + oo. 6: ooo+ + + ooooooooooo. 7: 00001 + 00000oooo. , 5:0OOOOI I I I 1000oO
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+ 0000/i: 0001000000+
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0/J:0000+ +1000011oo. M: 000001 1 1 1 1 1 10000
Za:oooooo○QI I + 100000/
/:OOOOOOOOOOOOOOOOOOOO JP-A-59-9
3490 (22) Continued from page 1 0 Inventor Lynel A. Neem New York, United States of America Wallkill Box 300 R.A. No. 41 Procedural Amendment (, eh. December 15, 1981 Patent Application No. 184327 2 Name of the invention 7 Ont display text editing method 3 Person making the amendment 4 Agent 5 Date of amendment order: Voluntary power of attorney for amendment (translation ('I') >.

Claims (1)

[Scope of Claims] (1) A display medium; a memory for storing denotational information in which each group of a plurality of alphabetic characters constitutes each font, and the shape of each alphabetic character of the plurality of said groups. and; outputting a signal representing the alphabetic character selected by the user to enable the user to select an alphabetic character to be displayed at a specific position on the display medium from among the plurality of groups of alphabetic characters. A font-displayed text editing system comprising: a responsive input device; and circuitry responsive to said signal for displaying said selected alphabetic character at said location on said display medium. (2) The system according to claim 1, wherein different groups of the alphabetic characters can be simultaneously displayed on the display medium. (3) In the system according to claim 1, the input device and the circuit cooperate so that positions 1-7 of the characters displayed on the display medium 1- are changed. N
The method is to make it 1+. (4,) ``2 Claim 1 [In the system described herein, the circuit described in -1- is responsive to the generation of two successive signals generated by an input device; The successive signals form parts of different groups of alphabetic characters by simultaneously displaying a first character in a first position of the display medium and a second character in a second position of the display medium. A method for specifying the first and second characters, respectively. (5) In the system as claimed in claim 1, each character is stored in the memory as a unique set of binary numbers describing the shape of the character. method. (6) In the method described in claim 5, the shape of each character is specified by a binary array of 0 rows and 9m columns, and each number is a pixel on the display medium. "(7)" in which "n" and "m" are positive integers. Claim 6
In the scheme described in Section 1, the binary array is stored as one binary word, each word containing m bits of information. (8) J1 In the method described in claim 7, each word of a given character is stored in consecutive locations in the memory. (9) In the method described in claim 8 above, each character is assigned a unique character code specifying the storage location of the memory in which the first word of that character is stored. method. (10) J-. The method according to claim 9, wherein the signal generated by the input device specifies the character code of the character selected by the user. (11) In the system as set forth in claim 10, the circuit reads each word of the character specified by the character hood from the memory and displays it on the display medium. A method that responds to the 1U signal by displaying the corresponding character. (12) Scope of Patent RtF and a second memory for storing signals corresponding to the one page of text displayed on the display device. (13) In the method recited in Claim 12, the circuit described in "-" generates a page of information displayed on the display device from the writing blade device. The -1 distribution formula is such that when the circuit erases the -1 page of information displayed on the display device, the memory 2 This method is equipped with a means to transfer all of the signals stored in memory to large-capacity memory. (14) - In the system according to claim 1, the circuit has a focus writing arrangement having an array of storage locations of g x p (where R and 1 are both positive integers greater than 1). A random access memory 3-1, and means for displaying information stored in the random access memory on a display device, the display device being divided into gXrl pixel positions. In addition, the second storage position corresponds one-to-one with the -1- pixel position. (15) In the system according to claim 14, the g and p are selected such that the relationship of 800 pg to 1100 and 800 p to 1100 hold, respectively. (16) In the method according to claim 15, the display device is composed of a cathode ray tube divided into 800 to 1100 information lines, and each line has 800 to 1100 information lines. A method that has pixel positions, and each pixel position has a one-to-one correspondence with a corresponding position in the storage position. (17) In the system according to claim 15, each character has two characters representing the shape of the character.
A system that is stored in the secondary memory as a unique group of base numbers. (18) In the above-mentioned claim 17, the shape of each character is 0 in binary digits.
is determined by a matrix arrangement Fi of rows and columns (where n and [n are both positive integers smaller than 8 and 1]), and the pixel is one of the above display media, or A method in which each binary number indicates whether a pixel can be located at a pixel position corresponding to two pairs of windows. (19)j-A system according to claim 18, wherein the arrangement is stored as n binary words comprising m bits of information. (2+11') In the method described in claim 19, each word of the given character is "
A method in which data is stored in consecutive locations in memory. (21) In the method set forth in claim 20, each character is assigned a unique character code that determines the storage location in the memory where the first word of that character is stored. method. (22) The method according to claim 21, wherein the signal output from the input device represents a character food selected by the user. (23) In the method set forth in claim 22 of the Jz patent, the circuit sequentially reads each word of the character written in the character code from the memory, and stores the information of the corresponding bit in the random access mode. A method that responds to the above signal by storing it in the corresponding storage location in memory. (24) The system according to claim 14, wherein the English characters of the hole group are simultaneously displayed on the display medium. (25)] 2. In the system according to claim 14, ``the input device and the circuit are capable of allowing a user to change the position of the character displayed on the display device; A way of working together. <26)-l- The method according to claim 14, wherein the circuit is ``responsive to the generation of two successive signals from the input device; The signal is obtained by simultaneously displaying the l-sugar character on the first signal of the display medium and the second character on the second position of the display device. This method specifies the first and second characters forming the part, respectively.