JPS5992603A - Out-band spurious suppressing circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit which varies the band of a filter automatically according to a bit rate by obtaining a DC voltage proportional to a sampling clock frequency and controlling a voltage variable capacity element on the basis of the voltage. CONSTITUTION:A sampling clock (a) is delayed by using an internal fast clock (b) as timing signals of D-type flip-flops FF1 and FF2 and a clock waveform with a delay difference corresponding to one cycle of the internal fast clock (b) is ORed exclusively by an exclusive OR circuit G to obtain a pulse waveform (e) of repetitive frequency proportional to the sampling clock frequency while having pulse width equal to one cycle of the internal fast clock (b). This pulse waveform (e) is converted by an RC smoothing circuit into the DC voltage proportional to the sampling clock period. Then, this DC voltage is impressed to the voltage variable capacity element Cv constituting the filter, whose pass band is varied corresponding to the sampling clock frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION (B) 8 Technical Field of the Invention The present invention relates to a modulator, and particularly to a digital processing type modulator with variable bit rate.

(b), Conventional technology and problems When trying to generate a modulated wave by digital signal processing, it is necessary to sample and hold the input data at the sampling clock frequency, and the noise component caused by this sampling clock is generated by the modulated wave. Since it remains as an out-of-band spurious in the signal, it is necessary to attenuate it with a filter.

In the case of a variable bit rate modulator, the band of this filter differs for each bit rate for reasons explained below.

For this reason, conventionally, when the bit rate changes, the filter band also changes, so it was necessary to change the filter band by replacing the filter or switching the elements that make up the filter, which was very complicated in terms of operation. .

(C)9 OBJECTS OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and to provide a circuit for automatically changing the filter band according to the bit rate.

cd)0 Structure of the Invention According to the present invention, the above object is to provide an exclusive OR of a sampling clock waveform and a clock waveform obtained by delaying the sampling clock waveform in a bit rate variable digital modulator. By taking the pulse waveform, a pulse waveform whose repetition frequency is proportional to the sampling clock frequency is generated, and by smoothing the pulse waveform, a DC voltage proportional to the sampling clock frequency is obtained, and the DC voltage is used. This is achieved by providing an out-of-band spurious suppression circuit characterized in that the pass band of a filter including the voltage variable capacitance element is changed in accordance with the sampling clock by controlling the voltage variable capacitance element using the voltage variable capacitance element. be done.

(e) 9 Embodiments of the Invention FIG. 1 shows an embodiment of the present invention, in which FFI, F
F2 is a D-type flip-flop, G is an exclusive OR circuit, A1 is an amplifier, R1-3 are resistors, 01-3 are capacitors, Ll, L2 are coils, Cv is a voltage variable capacitance element, A
2 is an operational amplifier, a sampling clock is connected to the a terminal, and b
The highest internal clock is applied to the terminal, the baseband signal is applied to the f terminal, and the g terminal is connected at the output to a conversion circuit to a carrier wave.

Figures 2, 3, and 4 are all reference diagrams for explaining the embodiment shown in Figure 1. The figures represent waveforms at terminal a, terminal b, point 0, point d, and point e in FIG. 1, respectively.

In a digital processing type modulator, the signal wave is normally spectrum-shaped by a transmission band-limiting filter in order to narrow the modulated wave spectrum and eliminate interference with other channels. The first filter used here has cosine roll-off, Gaussian characteristics, etc. so that code amount interference due to band limitation is minimized.

However, since the signal after passing through the first filter is processed by digital signal processing, the noise component due to the sampling clock is
After the A conversion, it is necessary to suppress the signal using a second filter.

The frequency at which this noise component occurs is expressed by the following equation, assuming that the number of bits of the sampling clock S1 is the data period T and n=1.2.3...

fs=nx2　XI/T The noise level becomes lower as the harmonic order n becomes larger.

Also, the larger S, that is, the higher the sampling clock frequency, the smaller the noise level, but the value of S is determined by the limit imposed by the response speed of the logic element.

Therefore, the second filter needs to have a sufficient amount of attenuation in the fs=2 xl/T equation, and to have a sufficiently wider band than the first filter so as not to cause code amount interference.

In a modulator whose bit rate is variable, in order to always satisfy the above conditions, it is necessary to change the band of the second filter according to the bit rate.

To do this automatically, as shown in Figure 1, the internal high-speed clock (the peak in Figure 2) is used as the timing of the D-type flip-flop, and the sampling clock [ia in Figure 2] is used as the timing for the D-type flip-flop.
Figure 1] is delayed, and by creating an exclusive OR of clock waveforms with a delay difference of one cycle of the internal high-speed clock, the pulse duration is equal to one cycle of the internal high-speed clock, and the repetition frequency is sampled. A pulse waveform [(e1) in FIG. 2] proportional to the clock frequency is obtained. This pulse waveform is converted into a DC voltage proportional to the sampling clock period by the R, C smoothing circuit.

On the other hand, if the second filter is constituted by a circuit including a voltage variable capacitance element as shown in FIG. 1, the band of the filter can be changed in accordance with the sampling clock frequency.

That is, if the second filter is a first-order low-pass filter using a differential amplifier as shown in FIG. 1, the cut-off frequency rc is given by the following equation, as is well known. fc
= 1/2πCv-R Therefore, as the sampling clock frequency increases, Cv should be reduced, and this can be fully realized by using a voltage variable capacitance element with the characteristics shown in Figure 3. It is.

02 and C3 in Figure 1 are capacitors for the DC block and are sufficiently large compared to Cv, so R = 1 /
2 rc f, yCv. However, Vr = k, X f sIk, is a constant, and f is the sampling clock frequency.

Also, as shown in Figure 3, the voltage variable capacitance element is expressed by the following formula, Cv.
Since it is easily available that has the characteristic that XVr = is multiplied by a (k is a constant), R should be selected so as to satisfy the following equation.

As explained above, according to the present invention, it is possible to change the passband of the filter in accordance with the sampling clock frequency.

(f) 1. Effects of the Invention As explained in detail above, according to the present invention, the filter band can be automatically changed in accordance with the bit rate, so it is possible to provide a good out-of-band spurious suppression circuit. There is a big effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, in which FFI, F
F2 is a D-type flip-flop, G is an exclusive OR circuit, A1 is an amplifier, R1-3 are resistors, 01-3 are capacitors, Ll, L2 are coils, Cv is a voltage variable capacitance element,
A2 is an operational amplifier, the sampling clock is applied to the a terminal, the highest internal clock is applied to the b terminal, the baseband signal is applied to the f terminal, and the g terminal is connected to the conversion circuit to a carrier wave at the output. Ru. FIG. 2, FIG. 3, and FIG. 4 are all reference views for explaining the embodiment shown in FIG. 1. 11 Procedural Amendment Form) 1. Incident display Showa! 7 Year Patent Application No. 2 o3 o 7
22) Name Fujitsu Ltd. 4, Agent Address Fujitsu Ltd. 5, 1015 Kami Elementary School, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Amended Order [1 attached February 22, 1939 (shipping date) 6 , the number of inventions increased by h1 due to amendment None? , Target of correction
The brief description column of drawings in the specification and Vl! lff1 1st
Figure 8, contents of the amendment As shown in the attached sheet (1) “Figure 2, Figure 3,
FIG. 4 is a reference diagram for explaining the embodiment shown in FIG. 1. ' shall be corrected as follows. ``Figure 2 shows terminal a, terminal b, point 0, point d, in figure 1,
It is a figure which shows the waveform of e point. FIG. 3 is a diagram showing how the capacitance of the voltage variable capacitance element changes depending on the voltage. FIG. 4 is a diagram showing the relationship between sampling clock frequency fsl and voltage. (2) Figure 1 of the drawings shall be amended as shown in the attached sheet.

Claims (1)

[Claims] In a digital modulator with variable bit rate, the repetition frequency can be made proportional to the sampling clock frequency by taking the exclusive OR of the sampling clock waveform and a clock waveform obtained by delaying the sampling clock waveform. By generating a pulse waveform, smoothing the pulse waveform to obtain a DC voltage proportional to the sampling clock frequency, and controlling the voltage variable capacitance element using the DC voltage, the voltage variable capacitance element is controlled. An out-of-band spurious suppression circuit characterized in that the passband of a filter including a filter is changed in accordance with the sampling clock.