JPS5992519A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5992519A
JPS5992519A JP57202125A JP20212582A JPS5992519A JP S5992519 A JPS5992519 A JP S5992519A JP 57202125 A JP57202125 A JP 57202125A JP 20212582 A JP20212582 A JP 20212582A JP S5992519 A JPS5992519 A JP S5992519A
Authority
JP
Japan
Prior art keywords
thin film
type
wall
contamination
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57202125A
Other languages
Japanese (ja)
Inventor
Akira Goto
明 後藤
Shinichi Muramatsu
信一 村松
Sunao Matsubara
松原 直
Kenichiro Nakao
健一郎 中尾
Masatoshi Utaka
正俊 右高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Maxell Ltd
Original Assignee
Hitachi Ltd
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Maxell Ltd filed Critical Hitachi Ltd
Priority to JP57202125A priority Critical patent/JPS5992519A/en
Publication of JPS5992519A publication Critical patent/JPS5992519A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03GELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00Apparatus for electrographic processes using a charge pattern
    • G03G15/75Details relating to xerographic drum, band or plate, e.g. replacing, testing
    • G03G15/754Details relating to xerographic drum, band or plate, e.g. replacing, testing relating to band, e.g. tensioning
    • G03G15/755Details relating to xerographic drum, band or plate, e.g. replacing, testing relating to band, e.g. tensioning for maintaining the lateral alignment of the band

Abstract

PURPOSE:To prevent a semiconductor device from contamination according to a different kind dopant by a method wherein a semiconductor layer is adhered previously on the inside face of a reaction vessel. CONSTITUTION:After a p-i-n junction type element is formed in a reaction vessel, when the wall of the vessel is etched by plasma using CF4, a thin film adhered on the wall can not be removed wholly, and because a part of the thin film is left as an etching remainder, it result in generation of a contaminating material when formation of a next p-i-n junction type element is to be formed. Because it is hard to remove completely the contaminating material according to etching, the element can be prevented from contamination by covering the upper part of the contaminating material with a semiconductor thin film not to apply a bad influence when the element is to be formed. When the p-i-n junction type element is to be formed, the wall of the vessel is covered with a p-type or an i-type semiconductor thin film according to the plasma CVD method, for example.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は多層半導体装置の製造方法に係シ、特にプラズ
マCVD法によりp−n、或いはp−1−n接合多層装
置を連続的に形成するのに好適な製造方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a multilayer semiconductor device, and particularly to a method for continuously forming a p-n or p-1-n junction multilayer device by a plasma CVD method. It relates to a manufacturing method suitable for.

〔従来技術〕[Prior art]

一般に、多層半導体薄膜を用いた半導体装置、たとえば
a−8i  pin太陽電池やラインセンサは、プラズ
マCVD法によ、bp型*xfi及びn型の半導体薄膜
を同一容器内で連続的に形成することによシ作製されて
いる。この際、pin型素子を同一容器内で〈シ返し作
製すると、再現性の良い素子特性が得られなかった。こ
れは、pin型素子杉成後はn型ドーパントによる汚染
が容器内に残っておシ、次にpin型素子を形成する際
にp層に混入するために特性に悪影響を与えるものであ
る。従来、このようなn型ドーパントの混入を防ぐため
に、CF4プラズマエツチングによシ容器内をりIJ−
ニングした後、pin型素子をJ成するという方法がと
られていた。しかし、このクリーニング法ではn型ドー
パントの汚染を完全には除けないという欠点があった。
Generally, semiconductor devices using multilayer semiconductor thin films, such as A-8I PIN solar cells and line sensors, require the continuous formation of BP-type*XFI and N-type semiconductor thin films in the same container by plasma CVD. It is made by the manufacturer. At this time, when the pin type element was fabricated in the same container, element characteristics with good reproducibility could not be obtained. This is because contamination by the n-type dopant remains in the container after the pin-type element is formed, and is mixed into the p-layer when the pin-type element is formed next, which adversely affects the characteristics. Conventionally, in order to prevent the contamination of such n-type dopants, CF4 plasma etching was used to remove IJ-
The conventional method was to form a pin-type element into a J-type structure after processing. However, this cleaning method has a drawback in that it cannot completely remove n-type dopant contamination.

一方、最近、この汚染を完全に除く方法としてpeje
”型の薄膜をそれぞれ別の容器で形成する方法が提案さ
れている。(Y、KuWano 、 15thIE″ 
photovoltaic  5peci31ist 
 Conference)この方法はドーパントによる
汚染を除くには有効であるが、床面、漬を大きくとる、
搬送系が長く機構が煩雑になる、等の欠点があった。
On the other hand, recently, peje has been proposed as a way to completely remove this pollution.
A method has been proposed in which each type of thin film is formed in a separate container. (Y, KuWano, 15thIE)
photovoltaic 5peci31ist
Conference) This method is effective in removing contamination from dopants, but requires a large amount of floor surface and dipping.
There were drawbacks such as a long conveyance system and a complicated mechanism.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、多層半導体膜から成る半導体装置を連
続的に製造するに際し、多数の容器を用いることなく、
異種ドーパントによる汚染を防ぐことのできる半導体装
置の製造方法を提供することにある。
An object of the present invention is to continuously manufacture semiconductor devices made of multilayer semiconductor films without using a large number of containers.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent contamination due to different types of dopants.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明は、容器の壁をエツ
チングすることによって汚染を除くのではなく、容器の
壁に汚染のない半導体薄膜を被覆することによ)汚染を
除Xものである。
To achieve the above object, the present invention eliminates contamination by coating the container wall with a contamination-free semiconductor thin film rather than by etching the container wall. .

pin型素子を形成した後、容器の壁をCF4を用いて
プラズマエツチングをした場合には、壁に被着した薄膜
のすべてを除くことはできず、電極から遠い部分には一
部エッチング残シが生ずる。
When plasma etching the wall of the container using CF4 after forming the pin type element, it is not possible to remove all of the thin film adhered to the wall, and some etching residue remains in the part far from the electrode. occurs.

すなわち、堆積とエツチングでは放電の状況が異なシ、
一部エッチング残シになると思われる。このエツチング
残シが、次のpin型素子形成の際に汚染切質になると
考えられる。従って、エツチングによって完全に汚染物
質を除くことは極めて困難であると考えられるので、汚
染物質の上を素子形成の際に悪影響を及ぼさない半導体
薄膜で覆うことにより、汚染を防止することが可能にな
る。
In other words, the discharge conditions differ between deposition and etching.
It seems that there will be some etching residue. It is thought that this etching residue will become a contaminating cut during the next formation of a pin type element. Therefore, it is considered extremely difficult to completely remove contaminants by etching, so it is possible to prevent contamination by covering the contaminants with a semiconductor thin film that does not have a negative effect on device formation. Become.

たとえば、pin型素子の場合には、p型もしくはi型
の半導本薄膜で容器壁をプラズマCVD法により被覆す
る処理を行った。このようにすれば、容器壁土の汚染勿
曖を素子特性に対して完全に、無害な半導体薄膜で覆う
ことができ、これによって汚染物質の悪影響を除くこと
ができた。
For example, in the case of a pin type element, the container wall was coated with a p-type or i-type semiconductor thin film by plasma CVD. In this way, the contamination of the container wall soil could be completely covered with a semiconductor thin film that is harmless to the device characteristics, thereby eliminating the adverse effects of the contaminants.

〔発明の実施例〕[Embodiments of the invention]

以F1本発明の第10夾施例を示す。 Hereinafter, a tenth embodiment of the F1 invention will be described.

実施例1 第1図に示したブロック図に従い、第2図に示した断面
構造の半4本装置を形成した。すなわち、まず、半導体
薄膜を形成する反応容器の内壁面をpm半導体薄膜で被
覆した。このために、反応答器内に水素希釈の10%モ
ノシランと、水素希釈の5001plジポランを、モノ
シラン/ジボラン=110.01の割合で導入しプラズ
マCVD法でp型アモルファスSi薄膜を形成した。壁
面での被覆厚さは明らかでないが、基板位置では500
0人の厚さになるように被覆を行った。
Example 1 According to the block diagram shown in FIG. 1, a semi-four-piece device having the cross-sectional structure shown in FIG. 2 was formed. That is, first, the inner wall surface of a reaction vessel in which a semiconductor thin film was to be formed was coated with a pm semiconductor thin film. For this purpose, 10% monosilane diluted with hydrogen and 5001 pl diporane diluted with hydrogen were introduced into the reactor at a ratio of monosilane/diborane=110.01, and a p-type amorphous Si thin film was formed by plasma CVD. Although the coating thickness on the wall surface is not clear, it is 500 mm at the substrate location.
The coating was applied to a thickness of 0.

次に、第2図に示した断面構造を有する半導体装置を作
表するために、透明導電膜2を有するガラス基板1を反
応容器に導入し、アモルファスS1薄膜を形成した。透
明導電膜2は1000人(D I TO(In*Os 
、 8nOx)を電子ビーム蒸着法で形成したものを用
いた。p型薄膜3、n型薄膜4、n型薄膜5は以下の仕
様で順次連続的に形成した。p型薄膜3は水素希釈の1
0%モノシランと、水素希釈5001plのジボランを
、モノシラン/ジボラン=110.01の割合で用い、
プラズマCVD法によ、!7100人の膜厚に形成した
。1厘薄膜4は水素希釈10%のモノシランを用い、プ
ラズマCVD法によfi5000人の膜厚に形成した。
Next, in order to tabulate a semiconductor device having the cross-sectional structure shown in FIG. 2, a glass substrate 1 having a transparent conductive film 2 was introduced into a reaction vessel, and an amorphous S1 thin film was formed. Transparent conductive film 2
, 8nOx) formed by electron beam evaporation. The p-type thin film 3, the n-type thin film 4, and the n-type thin film 5 were sequentially and continuously formed according to the following specifications. The p-type thin film 3 is diluted with hydrogen.
Using 0% monosilane and 5001 pl diborane diluted with hydrogen at a ratio of monosilane/diborane = 110.01,
By plasma CVD method! It was formed to a film thickness of 7,100 people. The 1-layer thin film 4 was formed using monosilane diluted with 10% hydrogen to a film thickness of fi5,000 by plasma CVD.

n型薄膜5は水素希釈10%のモノシランと、水素希釈
500pのホスフィンを、モノシラン/ホスフィン=1
10.01の割合で用い、プラズマCVD法によりso
o人の膜厚に形成した。
The n-type thin film 5 consists of monosilane diluted with 10% hydrogen and phosphine diluted with hydrogen 500p, monosilane/phosphine=1.
10.01, and the plasma CVD method
It was formed to a film thickness of 100 mm.

上記工程によってアモルファス81層3,4゜5を形成
した基板1を反応容器から取シ出し、金属マスクを用い
て、電極6をAtの抵抗加熱蒸着によj55000A膜
厚に形成した。
The substrate 1 on which the amorphous 81 layer 3,4°5 was formed by the above process was taken out from the reaction vessel, and an electrode 6 was formed to a thickness of J55000A by resistive heating vapor deposition of At using a metal mask.

以上の工程によって形成した半導体装置の光起電力特性
を測定した結果を第1表に示す。さらに、第   1 
  表 比較のために、従来の製法である、CF4によるプラズ
マエツチングによシフリーニングを行った場合の特性も
合せて示す。なお、再現性確認のためそれぞれ、2回ず
つ形成した結果を示しである。
Table 1 shows the results of measuring the photovoltaic characteristics of the semiconductor device formed through the above steps. Furthermore, the first
For comparison, the table also shows the characteristics when the conventional manufacturing method, plasma etching with CF4, was used for schiff cleaning. The results shown are the results of forming each layer twice to confirm reproducibility.

開放電圧、短絡電流1曲線因子、変換効率のいずれにお
いても本発明の方が従来法よ)まさっている。さらに特
性の再現性においても、まさっていることは明らかであ
る。
The present invention is superior to the conventional method in all of the open circuit voltage, short circuit current 1 fill factor, and conversion efficiency. Furthermore, it is clear that the reproducibility of characteristics is also superior.

次に本発明の第2の実施例を以下に示す。Next, a second embodiment of the present invention will be shown below.

実施例2 本発明の第2の実施例では、第1図の製造工程に加えて
、第1の工程として、容器壁をCF4プラズマでエツチ
ングする工程を加えて、第2図に示した半導体装置を形
成した。まず、ガラス基板を反応容器内に入れない状態
で、容器内をCPaプラズマエツチングを行った。この
とき、二つの11に極は完全にクリーニングできたが、
容器の壁には、それまでに堆積したアモルファスSiが
一部の領域で残った。次に、水素希釈の10%モノシラ
ンを容器内でプラズマCVD反応させ、容器壁を1型の
アモルファスSiで被覆した。この後、透明導電膜2を
有するガラス基板lを容器内に導入し、実施例1とまっ
たく同じ手順で、p型、i型、およびn型のアモルファ
スSiを形成した。
Embodiment 2 In a second embodiment of the present invention, in addition to the manufacturing process shown in FIG. 1, a step of etching the container wall with CF4 plasma is added as a first step to produce the semiconductor device shown in FIG. was formed. First, the inside of the reaction vessel was subjected to CPa plasma etching without placing the glass substrate inside the reaction vessel. At this time, the two 11 poles were completely cleaned, but
The amorphous Si deposited up to that point remained in some areas on the wall of the container. Next, 10% monosilane diluted with hydrogen was subjected to a plasma CVD reaction in the container to coat the container wall with type 1 amorphous Si. Thereafter, a glass substrate l having a transparent conductive film 2 was introduced into the container, and p-type, i-type, and n-type amorphous Si were formed in exactly the same manner as in Example 1.

ついで容器から試料を取シ出し、Atを金属マスク蒸着
して、第2図に示した構造の半導体装置を作製した。
Next, the sample was taken out from the container, and At was deposited using a metal mask to produce a semiconductor device having the structure shown in FIG. 2.

以上の工程によって形成した半導体装置の光起電力特性
を測定した結果を第2表に示す。また、第   2  
 表 比較のため、i型ではなく、n型のアモルファスSiを
容器壁に被覆シ、容器壁を故意に汚染して形成した半導
体装置の光起電力特性もあわせて示す。n型層の被覆に
は、水素希釈の10%モノシランと水素希釈の500P
ホスフインを、モノシラン/ホスフィン=110.01
の割合で導入し、プラズマCVD法で堆積した。なお、
再現性確認のため、それぞれ2回ずつ形成した結果を示
す。
Table 2 shows the results of measuring the photovoltaic characteristics of the semiconductor device formed through the above steps. Also, the second
For comparison, the table also shows the photovoltaic power characteristics of a semiconductor device formed by coating the container wall with n-type amorphous Si instead of i-type and intentionally contaminating the container wall. For coating the n-type layer, 10% monosilane diluted with hydrogen and 500P diluted with hydrogen were used.
Phosphine, monosilane/phosphine = 110.01
It was deposited by plasma CVD method. In addition,
In order to confirm reproducibility, the results of forming each layer twice are shown.

いずれの特性についても実施例2は、実施例1に近く、
再現性も良い結果が得られた。これに対して比較例では
特性が非常に悪く、容器壁の汚染によって、半導体装置
特性が非常に悪くなることが確認された。
For all characteristics, Example 2 is close to Example 1,
Results with good reproducibility were obtained. On the other hand, in the comparative example, the characteristics were very poor, and it was confirmed that the semiconductor device characteristics were very poor due to contamination of the container wall.

〔発明の効果〕〔Effect of the invention〕

上記説明から明らかなように、本発明によれば、反応容
器壁面の汚染の影響を防止する仁とができ、特性のすぐ
れた半導体装置を得ることが可能である。
As is clear from the above description, according to the present invention, it is possible to prevent the influence of contamination on the wall surface of a reaction vessel, and it is possible to obtain a semiconductor device with excellent characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
本発明によって形成された半導体装置の断面構造を示す
図である。 l・・・ガラス基板、2・・・透明導電膜、3・・・p
型薄膜、第1図
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a cross-sectional structure of a semiconductor device formed according to the present invention. l...Glass substrate, 2...Transparent conductive film, 3...p
Type thin film, Figure 1

Claims (1)

【特許請求の範囲】[Claims] 反応容器内で複数の半導体層を積層して被着すく方法に
おいて、上記反応容器の内面上に、あらかじめi形もし
くは第1層と同じ導電形の半導体層を被着することを特
徴とする半導体装置の製造方法。
A method of laminating and depositing a plurality of semiconductor layers in a reaction vessel, characterized in that a semiconductor layer of the i-type or the same conductivity type as the first layer is deposited on the inner surface of the reaction vessel in advance. Method of manufacturing the device.
JP57202125A 1982-11-19 1982-11-19 Manufacture of semiconductor device Pending JPS5992519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57202125A JPS5992519A (en) 1982-11-19 1982-11-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57202125A JPS5992519A (en) 1982-11-19 1982-11-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5992519A true JPS5992519A (en) 1984-05-28

Family

ID=16452373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57202125A Pending JPS5992519A (en) 1982-11-19 1982-11-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5992519A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172422A (en) * 1987-01-12 1988-07-16 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US4845043A (en) * 1987-04-23 1989-07-04 Catalano Anthony W Method for fabricating photovoltaic device having improved short wavelength photoresponse
JPH07326589A (en) * 1993-12-28 1995-12-12 Applied Materials Inc Single chamber cvd process for thin film transistor
JPH0855803A (en) * 1994-07-28 1996-02-27 Applied Materials Inc Thin film preparation
WO2004086475A1 (en) * 2003-03-26 2004-10-07 Hitachi Kokusai Electric Inc. Substrate treating apparatus and process for producing semiconductor device
EP1524703A2 (en) 2003-10-17 2005-04-20 Sharp Kabushiki Kaisha Method of manufacturing a Silicon-based thin-film-photoelectric conversion device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172422A (en) * 1987-01-12 1988-07-16 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US4845043A (en) * 1987-04-23 1989-07-04 Catalano Anthony W Method for fabricating photovoltaic device having improved short wavelength photoresponse
JPH07326589A (en) * 1993-12-28 1995-12-12 Applied Materials Inc Single chamber cvd process for thin film transistor
JP2007134706A (en) * 1993-12-28 2007-05-31 Applied Materials Inc Single chamber cvd process for thin film transistor
JPH0855803A (en) * 1994-07-28 1996-02-27 Applied Materials Inc Thin film preparation
WO2004086475A1 (en) * 2003-03-26 2004-10-07 Hitachi Kokusai Electric Inc. Substrate treating apparatus and process for producing semiconductor device
EP1524703A2 (en) 2003-10-17 2005-04-20 Sharp Kabushiki Kaisha Method of manufacturing a Silicon-based thin-film-photoelectric conversion device
EP1524703A3 (en) * 2003-10-17 2007-10-10 Sharp Kabushiki Kaisha Method of manufacturing a Silicon-based thin-film-photoelectric conversion device

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