JPS5991029U - AGC circuit - Google Patents

AGC circuit

Info

Publication number
JPS5991029U
JPS5991029U JP18836182U JP18836182U JPS5991029U JP S5991029 U JPS5991029 U JP S5991029U JP 18836182 U JP18836182 U JP 18836182U JP 18836182 U JP18836182 U JP 18836182U JP S5991029 U JPS5991029 U JP S5991029U
Authority
JP
Japan
Prior art keywords
amplifier
agc circuit
output
diagram showing
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18836182U
Other languages
Japanese (ja)
Inventor
豊 吉田
菊地 吉隆
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP18836182U priority Critical patent/JPS5991029U/en
Publication of JPS5991029U publication Critical patent/JPS5991029U/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はFM磁気記録再生装置の再生系の回路例を示す
構成図、第2図はアンプの周波数特性を示す線図、第3
図は本考案の一実施例を示す構成図、第4図はその具体
団結を示す接続図、第5図は一実施例の入出力特性を示
す線図、第6図は本考案の他の実施例を示す構成図であ
る。 3A及び3Bは夫々高周波増幅用のアンプ、9゜9A及
び9Bは夫々検波回路、IOA及びIOBは夫夫制御回
路である。
Fig. 1 is a configuration diagram showing an example of a circuit of a reproducing system of an FM magnetic recording/reproducing device, Fig. 2 is a diagram showing frequency characteristics of an amplifier, and Fig. 3 is a diagram showing a circuit example of a reproducing system of an FM magnetic recording/reproducing device.
The figure is a configuration diagram showing one embodiment of the present invention, Fig. 4 is a connection diagram showing its concrete integration, Fig. 5 is a line diagram showing input/output characteristics of one embodiment, and Fig. 6 is a diagram showing another embodiment of the present invention. FIG. 2 is a configuration diagram showing an example. 3A and 3B are amplifiers for high frequency amplification, 9°9A and 9B are detection circuits, respectively, and IOA and IOB are husband control circuits.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号が第1のアンプに供給され、この第1のアンプ
の出力が第2のアンプに供給され、この第2のアンプよ
り出力信号が得られ、この出力信号のレベルが検出され
、この検出出力によって上記第1及び第2のアンプのゲ
インが制御されるようになされたAGC回路。
The input signal is supplied to a first amplifier, the output of this first amplifier is supplied to a second amplifier, an output signal is obtained from this second amplifier, the level of this output signal is detected, and this detection An AGC circuit in which the gains of the first and second amplifiers are controlled by the output.
JP18836182U 1982-12-13 1982-12-13 AGC circuit Pending JPS5991029U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18836182U JPS5991029U (en) 1982-12-13 1982-12-13 AGC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18836182U JPS5991029U (en) 1982-12-13 1982-12-13 AGC circuit

Publications (1)

Publication Number Publication Date
JPS5991029U true JPS5991029U (en) 1984-06-20

Family

ID=30406372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18836182U Pending JPS5991029U (en) 1982-12-13 1982-12-13 AGC circuit

Country Status (1)

Country Link
JP (1) JPS5991029U (en)

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