JPS5990961A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS5990961A JPS5990961A JP57201560A JP20156082A JPS5990961A JP S5990961 A JPS5990961 A JP S5990961A JP 57201560 A JP57201560 A JP 57201560A JP 20156082 A JP20156082 A JP 20156082A JP S5990961 A JPS5990961 A JP S5990961A
- Authority
- JP
- Japan
- Prior art keywords
- rays
- section
- semiconductor chip
- protective film
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/18—Circuits for erasing optically
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
この発明はＸ ＃、ｌｉｔを照射して半導体チップ内の
記１、ヲ内容を消去できる簡易構造の半導体記憶装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device with a simple structure that can erase the contents of a semiconductor chip by irradiating it with X#, lit.
一般に、間外線消去型のＥＰＲＯＭ（つまり１ｉｒａｓ
ａｂｌｅ ａｎｄ ｅｌｅｃｔｒｉｃａｌｌｙ ｐｒｏ
ｇｒａｍｍａｂｌｅ ｒｔｒａｄｏｎＩｙ ｒｎｅｒｎ
ｏｒｙの略称）の場合、１ン○Ｍの部分のみに紫外線が
当たるように透明な樹脂等で窓状の構造をした特殊なパ
ッケージを作る必要があり、コスＩ・的に割高となって
いた。In general, an EPROM of the line erasing type (i.e. 1 iras
able and electrically pro
grammable rtradonIy rnern
In the case of (abbreviation for "ory"), it was necessary to make a special package with a window-like structure made of transparent resin so that only the 1n○M part was exposed to ultraviolet rays, making it relatively expensive in terms of cost. .
本発明は上記点に鑑み、通常のプラスチックパッケージ
とｆｉＪ様の構造にし゛Ｃ成型しゃＪ−＜、かつ低コス
トの半導体記憶装置を提供゛４るごとを目的とする。In view of the above points, it is an object of the present invention to provide a low-cost semiconductor memory device that uses an ordinary plastic package and a FIJ-like structure, and is capable of C-molding.
そのため本発明では、リード部及びチップ搭載部を有す
るリードフレーム、と、前記デツプ搭載ｆｆ１ｔに載置
された記１を素子形成領域を有する半導体チップと、こ
の半導体チップ」二において少なくとも前記記憶素子形
成領域を除＜ ｔｐ＋＋分に形成されたＸ線遮えい部材
と、前記半導体−ｆ ノブ及び０；１記デツプ搭載部及
び前記リード部の一部を被覆するモールド部材とからな
り、前記デツプ搭載部の表面側より前記モールド部材を
介しζＸ線を照射しｎ；１記半導体チップ内の記憶内容
を消去′する構造とり、たことを特徴とする。Therefore, in the present invention, there is provided a lead frame having a lead portion and a chip mounting portion, a semiconductor chip placed on the depth mounting ff1t and having an element formation region, and a semiconductor chip in which at least the memory element is formed. It consists of an X-ray shielding member formed in an area < tp++ excluding the region, and a molding member that covers the semiconductor-f knob and a part of the depth mounting part and the lead part, and The semiconductor chip is characterized in that it has a structure in which the memory contents in the semiconductor chip are erased by irradiating ζX-rays from the front surface side of the semiconductor chip through the mold member.
次に、本発明の一実施例につい一ζ説明する。Next, one embodiment of the present invention will be explained.
第１図及び第２図は半導体記憶装置の断面図及び平面図
である。１．２はリードフレームを構成するリード部と
チップ搭載部、３は記憶素子形成領域（ＩＥ ｌ） Ｒ
ＯＭ ２部分）を有する半導体チップで、この記憶素子
形成領域（第３図中領域３ａ）及びホンディングワイヤ
５などによる信号取出し部分（第３図中領域３ｂ）を除
く表面部分をＸ線遮へい部材である保護１１ｉａ４で被
覆されている。この保ｉ！１ｆ１９４１；ｌ、鉛などＸ
線を透過しにくい材料またはその混合物から構成されて
おり、使用されるＸ＃ｆＡのＩＩ＜ｌ射強度を考慮しζ
そのヰ］質や膜厚は適宜選択されている。第３図は半導
体チップ部分を拡大図したもので、半導体チップ３」二
におい“Ｃ保１（ＮＡ４は、記憶未了・形成領域３ａを
鮪出さ（る露出部４ａと被覆部４ｂからなる。６はエポ
キシ樹脂等のプラスデックモールド部材である。1 and 2 are a sectional view and a plan view of a semiconductor memory device. 1.2 is the lead part and chip mounting part that make up the lead frame, 3 is the storage element formation area (IE l) R
This semiconductor chip has an X-ray shielding member for the surface area excluding the memory element forming area (area 3a in FIG. 3) and the signal extraction area by the bonding wire 5 (area 3b in FIG. 3). It is coated with protection 11ia4. This protection! 1f1941; l, lead etc.
It is made of a material or a mixture thereof that does not easily transmit radiation, and considering II<l radiation intensity of X#fA used, ζ
Its quality and film thickness are appropriately selected. FIG. 3 is an enlarged view of the semiconductor chip portion, where the semiconductor chip 3 consists of an exposed portion 4a and a covered portion 4b, which expose the unmemorized/formed area 3a. 6 is a plus deck mold member made of epoxy resin or the like.
そこで、この半導体装置のＥ Ｐ ＲＯＭ部分の記憶内
容を消去するには、プラスチソクパノケーシ」二面から
所定強度のＸ線を照射すればよい。Ｘ線はモールＦ部材
６を透過し保ｉ１膜４の掲出部４ａを通して半導体デツ
プ３のｌｆｆ１ ＰＲＯＭ部分に到達する。そごでＥ
Ｐ ＲＯＭのフローティングゲート中の電荷を放出させ
、記憶内容を消却できる。この際、Ｅ Ｉ） ＲＯＭ以
外のチップ部分は保護膜４で覆われているためＸ線によ
る損傷から保護されることになる。Therefore, in order to erase the stored contents of the EP ROM portion of this semiconductor device, it is sufficient to irradiate X-rays of a predetermined intensity from two sides of the plastic pan casing. The X-rays pass through the molding F member 6 and reach the lff1 PROM portion of the semiconductor depth 3 through the raised portion 4a of the insulating i1 film 4. Sogode E
The charges in the floating gate of the PROM can be released and the stored contents can be erased. At this time, the chip portions other than the EI) ROM are covered with the protective film 4 and are therefore protected from damage caused by X-rays.
なお、」ニド実施例では保１１１Ｑ４を半導体チ・ノブ
３上に被覆するようにしたが、所定の露出穴を有゛４る
Ｘ線遮へい板を用い、プラスチ・ツクモールド時に、こ
の遮へい板が半導体チ・ノブ」二の所定位置に固定され
るようにしＣもよい。In addition, in the Nido Example, the semiconductor chip 111Q4 was coated on the semiconductor chip knob 3, but when an It may also be fixed in a predetermined position on the second knob.
上記実施例では１チツプマイクロコンピユータなどＩＺ
Ｐ １１０Ｍを一部分に搭載するものについて説明し
たが、全体がＲＯＭからなりその一部が１２゜１３ Ｒ
ＯＭからなるものにも同様に適用できる。In the above embodiment, a one-chip microcomputer, etc.
I explained about a model with P 110M installed in a part, but the whole is made up of ROM and part of it is 12゜13R.
The same applies to those made of OM.
以」二述べた如く、本発明によれば通常のプラスチック
モールＶ品と何ら構造的に変化がなく、しかも安価な手
段により、Ｘ線消去可能な半導体記憶装置を提供できる
。As described above, according to the present invention, it is possible to provide an X-ray erasable semiconductor memory device that is structurally unchanged from ordinary plastic molded V products and is inexpensive.
第１．２図は本発明装置の一実施例を示１°断面図と、
１１１面図、第３図は半導体チ・ノブｎ１ζ分を１珪二
大した図である。
ｌ・・・リード部、２・・・チ・ノブ搭載部、３・・・
半導体−ブツブ、４・・・Ｘ線遮へい部材をなす保護膜
、６・・・プラスチックモールド部材。
代理人弁理士 岡 部 隆
第１１掲 第２１４
第 ３ １゛：１
４０ ３ｂFigure 1.2 shows an embodiment of the device of the present invention, a 1° cross-sectional view, and
The 111th view and FIG. 3 are views in which the semiconductor chip n1ζ is enlarged by 1×1. l...Lead part, 2...Ch knob mounting part, 3...
Semiconductor-bubble, 4... Protective film forming an X-ray shielding member, 6... Plastic mold member. Representative Patent Attorney Takashi Okabe No. 11 No. 214 No. 3 1゛: 1 40 3b
Claims (1)
、ｔ）：１記チ、ゾ搭載部に載置された記憶素子形成ｖ
Ｉ域を有する半導体チップと、この半導体チップ上に才
？いて少なくとも前記記ｉｆｆ素子形成領域を除く部分
に形成されたＸ線遮えい部材と、前記半導体−ノーソゾ
及びｆｌｉｌ記チノゾ搭載部及びｆｌｉｌ記リードリー
１部を被覆するモールド部月とがらなり、ｔ’＋ｉｌ記
チノゾＩδ載ａ＋＋の表面側よりｎ：１記モ一ルド部材
を介してＸ線を照射し前記半導体−ｆ〜ツブ内の記１゜
な内容を？ｌｉ去する構造の半導体記１σ装置。A lead frame having a saw 1' portion and a chip mounting portion, and t): 1.
Is there a semiconductor chip with an I region and a semiconductor chip on this semiconductor chip? t'+il X-rays are irradiated from the surface side of the chinozo Iδ mounted a++ through the n:1 molded member to examine the contents of the semiconductor -f to lumps as described above. A semiconductor 1σ device having a structure in which li is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57201560A JPS5990961A (en) | 1982-11-16 | 1982-11-16 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57201560A JPS5990961A (en) | 1982-11-16 | 1982-11-16 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5990961A true JPS5990961A (en) | 1984-05-25 |
Family
ID=16443071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57201560A Pending JPS5990961A (en) | 1982-11-16 | 1982-11-16 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5990961A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033257A (en) * | 1989-05-30 | 1991-01-09 | Mitsubishi Electric Corp | Semiconductor device |
| US5656521A (en) * | 1995-01-12 | 1997-08-12 | Advanced Micro Devices, Inc. | Method of erasing UPROM transistors |
-
1982
- 1982-11-16 JP JP57201560A patent/JPS5990961A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH033257A (en) * | 1989-05-30 | 1991-01-09 | Mitsubishi Electric Corp | Semiconductor device |
| US5656521A (en) * | 1995-01-12 | 1997-08-12 | Advanced Micro Devices, Inc. | Method of erasing UPROM transistors |
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