JPS5990407A - Peak detecting circuit - Google Patents

Peak detecting circuit

Info

Publication number
JPS5990407A
JPS5990407A JP20020282A JP20020282A JPS5990407A JP S5990407 A JPS5990407 A JP S5990407A JP 20020282 A JP20020282 A JP 20020282A JP 20020282 A JP20020282 A JP 20020282A JP S5990407 A JPS5990407 A JP S5990407A
Authority
JP
Japan
Prior art keywords
voltage
operational amplifier
diode
inverting input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20020282A
Other languages
Japanese (ja)
Other versions
JPS6333326B2 (en
Inventor
Tsunemi Gonda
権田 常躬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nikon Corp
Nippon Kogaku KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp, Nippon Kogaku KK filed Critical Nikon Corp
Priority to JP20020282A priority Critical patent/JPS5990407A/en
Publication of JPS5990407A publication Critical patent/JPS5990407A/en
Publication of JPS6333326B2 publication Critical patent/JPS6333326B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00Demodulation of amplitude-modulated oscillations
    • H03D1/08Demodulation of amplitude-modulated oscillations by means of non-linear two-pole elements
    • H03D1/10Demodulation of amplitude-modulated oscillations by means of non-linear two-pole elements of diodes

Abstract

PURPOSE:To detect a peak position at an input voltage being a negative voltage below zero by deciding the polarity of the 1st and the 2nd diodes being at the same polarity between an output and a non-inverting input of an operational amplifier and giving an input voltage between the non-inverting input and a common. CONSTITUTION:The output of the operational amplifier OP1 is connected to an anode of a diode D1. The input voltage (ei) is applied between the non-inverting input and a common of the operational amplifier OP1, and an output voltage l0 is extracted between the output of the operational amplifier OP1 and the common. As the input voltage (ei) increases, a voltage between an inverting input and the non-inverting input of the operational amplifier OP1 is decreased gradually less than the forward voltage of the diode D2 and reaches the voltage finally, and when the voltage exceeds the value, the output voltage (eo) of the operational amplifier OP1 rises positively, the diode D1 is conductive, the diode D2 is nonconductive, the circuit restores to the state similar to the first state. Thus, the peak position is detected.

Description

【発明の詳細な説明】 本発明は入力電圧のピーク位置を検出するためのピーク
検波回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a peak detection circuit for detecting the peak position of input voltage.

従来この種の回路は第1図、第2図のごとき構成、であ
り、第1図は一回限わのピーク位置不検出する為に用い
られ、第2図は連続的な交流のピーク位置を検出する為
に用いられるものである。
Conventionally, this type of circuit has a configuration as shown in Figures 1 and 2. Figure 1 is used to detect one-time peak positions, and Figure 2 is used to detect continuous AC peak positions. It is used to detect.

第1図で示した従来のピーク検波回路は、演算増幅器O
PIの出力端子をダイオードDのアノードに接続し、ダ
イオードDのカソードをコンデンサCの一方の端子と演
算増幅器OP2の非反転入力端子に接続し、コンデンサ
Cの他方の端子を共通端子(アース)に接続し、コンデ
ンサの端子間に放!用スイッチSを設け、演算増幅器O
P2の反転入力端子と出力端子とを接続してバッファを
構成し、この出力端子を演算増幅器OP1の反転入力端
子に接続して構成さねている。そして、演算増幅器OP
Iの非反転入力端子と共通端子(アース)との間に入力
電圧eiが印加され、演算増幅WOPIの出力端子と共
通端子(アース)との間から出力電圧eoが取り出され
る。
The conventional peak detection circuit shown in Fig. 1 consists of an operational amplifier O
Connect the output terminal of PI to the anode of diode D, connect the cathode of diode D to one terminal of capacitor C and the non-inverting input terminal of operational amplifier OP2, and connect the other terminal of capacitor C to the common terminal (ground). Connect it and release it between the terminals of the capacitor! A switch S is provided for the operational amplifier O.
The inverting input terminal and output terminal of P2 are connected to form a buffer, and this output terminal is connected to the inverting input terminal of operational amplifier OP1. And operational amplifier OP
An input voltage ei is applied between the non-inverting input terminal of the operational amplifier WOPI and the common terminal (earth), and an output voltage eo is taken out between the output terminal of the operational amplifier WOPI and the common terminal (earth).

なお、ダイオードDのカソードとコンデンサCの一方の
端子と演算増幅器OP2の非反転入力端子との接続点を
Qとする。
Note that Q is the connection point between the cathode of the diode D, one terminal of the capacitor C, and the non-inverting input terminal of the operational amplifier OP2.

このような回路において、第3図(a)に示すごときパ
ルス的な電圧e+を入力すると、第1図のQ点の電圧及
び出力電圧eoは第3図(b)、(C)に各々Q、eo
で示すごとく変化をし、入力電圧eiのピークP、の位
置が出力電圧eoにて検出される。ところが入力電圧e
iにおいて、第3図(a)に破線で示したごとく、第1
のピークP1に続いてピークP1より小さい撮幅の第2
のピークP2が来た時には、コンデンサー〇の電荷が放
電しきっていない為に、演算増幅器OPIは動作をせず
、出力電圧eoとしては第2のピークP2が検出されな
い。その為に第1のピークP1を検出した後にただちに
コンデンサCの電荷を放電させるべき、図示されていな
い放電開始回路によりスイッチSをタイミング良く閉じ
なければならない。従って第1図の回路は放電開始回路
が必要であるという欠点が有る。
In such a circuit, when a pulsed voltage e+ as shown in FIG. 3(a) is input, the voltage at point Q and the output voltage eo in FIG. ,eo
The position of the peak P of the input voltage ei is detected by the output voltage eo. However, the input voltage e
At i, the first
Following the peak P1, a second peak with a smaller imaging width than the peak P1
When the peak P2 of is reached, the charge in the capacitor O has not been completely discharged, so the operational amplifier OPI does not operate, and the second peak P2 is not detected as the output voltage eo. For this reason, the switch S must be closed in a timely manner by a discharge starting circuit (not shown) to discharge the charge in the capacitor C immediately after detecting the first peak P1. Therefore, the circuit of FIG. 1 has the disadvantage that a discharge starting circuit is required.

さらに第1図の回路は第3図(d)のei’に示すごと
く、入力のパルス的な電圧に負の直流電圧が重畳し、そ
のピークPが負の電圧の時にはダイオードDが逆バイア
スになり、非導通になり、ピークPは検出されないとい
う欠点を有している。
Furthermore, in the circuit of Figure 1, as shown by ei' in Figure 3(d), a negative DC voltage is superimposed on the input pulse voltage, and when the peak P is a negative voltage, the diode D becomes reverse biased. This has the drawback that the peak P is not detected because the current becomes non-conductive.

次に第2図の回路の説明に入るが、第2図の回路が第1
図の回路と異なる点は、コンデンサCに並列に接続した
放電用のスイッチSの代わりに、コンデンサCに並列に
抵抗Rを接続したことである3、第2図の入力電圧e1
として第4図(a) にeiで示したごとく周期Tのく
り返し信号を入力すると、コンデンサCと抵抗Rの時定
数CRが周期Tに比べて充分大きい場合、第2図のQ点
の電圧は第4図(b)のQのごとくになる。これは入力
電圧eiの正の傾きの時は演算増幅器OPIの出力イン
ピーダンスは低いので急速にコンデンサCを充電し、は
ぼ入力電圧と同一波形になるが、ピークPを通過すると
、入力電圧e1は低くなるので、コンデンサCに蓄えら
れた電荷による電圧により、ダイオードDは逆バイアス
されて非導通になり、コンデンサCと抵抗Rの時定数C
Rで定まる放電特性でコンデンサCが放電されることに
よる。
Next, I will explain the circuit in Figure 2.The circuit in Figure 2 is the first circuit.
The difference from the circuit shown in the figure is that instead of the discharging switch S connected in parallel to the capacitor C, a resistor R is connected in parallel to the capacitor C. 3. Input voltage e1 in Fig. 2
As shown by ei in Figure 4(a), if a repeated signal with period T is input, then if the time constant CR of capacitor C and resistor R is sufficiently large compared to period T, the voltage at point Q in Figure 2 will be It becomes like Q in FIG. 4(b). This is because when the input voltage ei has a positive slope, the output impedance of the operational amplifier OPI is low, so the capacitor C is rapidly charged, and the waveform becomes almost the same as that of the input voltage, but when the input voltage e1 passes through the peak P, the input voltage e1 becomes As the voltage decreases due to the charge stored in capacitor C, diode D becomes reverse biased and becomes non-conducting, and the time constant C of capacitor C and resistor R increases.
This is because the capacitor C is discharged with a discharge characteristic determined by R.

その結果、出力電圧eoは第4図(C)のeOのごとき
波形となりピークPの位置が検出される。
As a result, the output voltage eo has a waveform like eO in FIG. 4(C), and the position of the peak P is detected.

ここで入力電圧eiの周期Tを太きくし時定数CRに近
ずけていくと、第2図のQ点の波形は第4図(d)のQ
′で示すごとく、ピーク付近では入力電圧ei (第4
図(a)参照)に近すいてしまう為に、その出力電圧e
Oは第4図(e)の信号eo’に示すごとく、検出され
るピークPの位置には時間tの遅れ誤差を生じてしまう
。この事は、時定数CRに対して入力電圧e1の周期T
はある範囲内でなければならないという欠点を有してい
る事を示している。
If the period T of the input voltage ei is made thicker and approaches the time constant CR, the waveform at point Q in FIG.
′, near the peak the input voltage ei (4th
(see figure (a)), the output voltage e
As shown in the signal eo' in FIG. 4(e), O causes a delay error of time t in the position of the detected peak P. This means that the period T of the input voltage e1 with respect to the time constant CR
This indicates that it has the disadvantage that it must be within a certain range.

さらに第4図(f)のei′に示すごとく入力電圧e1
が負の電圧範囲で生じている場合、第1図の場合と同様
にダイオードDは常に逆バイアスされるために非導通と
なり、ピークPの位置は検出されないと云う欠点がある
Furthermore, as shown in ei' in FIG. 4(f), the input voltage e1
occurs in the negative voltage range, the diode D is always reverse biased and non-conductive, as in the case of FIG. 1, and the position of the peak P cannot be detected.

本発明はこれらの欠点を解決し、周波数依存性(5) が小さく、パルス的入力及びくり返し入力電圧にも対応
が出来ると共に、入力電圧が零ボルト以下の負の電圧に
おいてもそのピーク位置が検出出来るピーク検波回路を
得る事を目的とする。
The present invention solves these drawbacks, has small frequency dependence (5), can handle pulsed inputs and repeated input voltages, and can detect the peak position even when the input voltage is a negative voltage of zero volts or less. The purpose of this study is to obtain a peak detection circuit that is possible.

以下、図面に示した実施例に基づいて本発明を説明する
The present invention will be described below based on embodiments shown in the drawings.

第5図は本発明の第1実施例であり、演算増幅器OPI
の出力端子をダイオードD1のアノードに接続し、ダイ
オードDIのカソードをコンデンサCの一方の端子とダ
イオードD2のアノードと演算増幅器OPIの反転入力
端子に接続し、コンデンサCの他方の端子を共通端子(
アース)に接続し、ダイオードD2のカソードを演算増
幅器OP2の出力端子に接続し、演算増幅器OP2の非
反転入力端子を演算増幅器OPIの非反転入力端子に接
続し、演算増幅器OP2の反転入力端子をその出力端子
に接続して成る。第5図の回路において、演算増幅器O
PIの非反転入力端子と共通端子との間に入力電圧ei
を印加し、演算増幅器OP1の出力端子と共通端子との
間から出力電圧(6) eoを取り出す。なお、ダイオードD1のカソードとコ
ンデンサCの一方の端子とダイオードD2のアノードと
演算増幅器OP1の反転入力端子との接続点をQとする
FIG. 5 shows a first embodiment of the present invention, in which an operational amplifier OPI
The output terminal of the capacitor C is connected to the anode of the diode D1, the cathode of the diode DI is connected to one terminal of the capacitor C, the anode of the diode D2, and the inverting input terminal of the operational amplifier OPI, and the other terminal of the capacitor C is connected to the common terminal (
ground), connect the cathode of diode D2 to the output terminal of operational amplifier OP2, connect the non-inverting input terminal of operational amplifier OP2 to the non-inverting input terminal of operational amplifier OPI, and connect the inverting input terminal of operational amplifier OP2 to connected to its output terminal. In the circuit of Fig. 5, the operational amplifier O
Input voltage ei between the non-inverting input terminal of PI and the common terminal
is applied, and an output voltage (6) eo is taken out from between the output terminal of the operational amplifier OP1 and the common terminal. Note that Q is the connection point between the cathode of the diode D1, one terminal of the capacitor C, the anode of the diode D2, and the inverting input terminal of the operational amplifier OP1.

上述の回路において入力電圧eiとして第6図(a)の
ごときくり返し信号eiを入力すると演算増幅器OP2
の出力端子には入力電圧eiと同一電圧が生じている事
は言うまでもない。他方演算増幅器OPIはコンデンサ
Cの電荷が零から始まるので、ダイオードD1は導通し
、Q点は第6図(b)に示すごとく、入力電圧elと同
一振幅で増加する。入力電圧eiがビークPになる位置
までの演算増幅器OPlの出力電圧eoは入力電圧ei
に対して第6図(c)に示した如く、ダイオードD1の
順方向電圧Vf1分だけ高い電圧で変化する。
In the above circuit, when the repetition signal ei as shown in FIG. 6(a) is input as the input voltage ei, the operational amplifier OP2
It goes without saying that the same voltage as the input voltage ei is generated at the output terminal of . On the other hand, in the operational amplifier OPI, since the charge on the capacitor C starts from zero, the diode D1 becomes conductive, and the Q point increases with the same amplitude as the input voltage el, as shown in FIG. 6(b). The output voltage eo of the operational amplifier OPl up to the point where the input voltage ei reaches the peak P is the input voltage ei
On the other hand, as shown in FIG. 6(c), the voltage changes to a higher voltage by the forward voltage Vf1 of the diode D1.

また、ダイオードD2の両端の電圧は各々入力電圧e1
と同じ[直であるので、ダイオードD2は何ら動作に寄
与しない。そして入力端子eiがビークPの位置を通過
するとコンデンサCはビーク電圧に充電されているので
演算増幅器OPIの反転入力端子もピーク電圧になる。
Also, the voltage across the diode D2 is the input voltage e1, respectively.
The diode D2 does not contribute to the operation. When the input terminal ei passes the position of the peak P, the capacitor C is charged to the peak voltage, so the inverting input terminal of the operational amplifier OPI also becomes the peak voltage.

続いて入力電圧e+は減少しだすので、演算増幅器OP
Iの非反転入力端子の電圧は反転入力端子の電圧より低
くなり、その出力電圧eOは第6図(c)に示したよう
に演算増幅器OPIのマイナス飽和電圧■8まで低下す
る。その結果、ダイオードD1は逆バイアスされて非導
通になる。そして入力電圧eiがさらに減少し、演算増
幅器OP2の出力端子の電圧がQ点の電圧よりダイオー
ドD2の順方向電圧■f2以下に低下するとダイオード
D2は導通したし、コンデンサCの電荷はダイオードD
2を通して演算増幅器OP2の出力端子に放電し、その
後、Q点の電圧は入力電圧eiよりも712分だけ旨い
電圧で変化する。この様子を第6図(b)に示す。同図
における二点鎖線は、従来のC’R放電特性を示す(第
4図(b)参照)・ この様にビークPの位置を通過後は従来と異なり、コン
デンサCの電圧はダイオードD2の順方向電圧Vf2分
のみの差で入力電圧eiに追従しているので、余分な電
荷の蓄積がなく、その後の入力変化に対して追従しやす
い状態になっている。
Subsequently, the input voltage e+ begins to decrease, so the operational amplifier OP
The voltage at the non-inverting input terminal of I becomes lower than the voltage at the inverting input terminal, and its output voltage eO drops to the minus saturation voltage 8 of the operational amplifier OPI, as shown in FIG. 6(c). As a result, diode D1 becomes reverse biased and non-conducting. Then, when the input voltage ei further decreases and the voltage at the output terminal of the operational amplifier OP2 drops below the voltage at point Q to the forward voltage f2 of the diode D2, the diode D2 becomes conductive, and the charge on the capacitor C is transferred to the diode D.
2 to the output terminal of the operational amplifier OP2, and then the voltage at the Q point changes by a voltage 712 times better than the input voltage ei. This situation is shown in FIG. 6(b). The two-dot chain line in the same figure shows the conventional C'R discharge characteristic (see Figure 4 (b)). In this way, after passing the position of the peak P, the voltage of the capacitor C is different from the conventional one, and the voltage of the diode D2 is Since the input voltage ei is followed with a difference of only the forward voltage Vf2, there is no accumulation of excess charge, and the state is such that it is easy to follow subsequent input changes.

すなわち周波数依存性が少ない。In other words, there is little frequency dependence.

続いて入力電圧eiが増加しだすと、演算増幅器OPI
の反転入力端子と非反転入力端子間の電圧は電圧Vf、
の匝よりもしだい小さくなりついには同一となり(第6
図(b)の1点)、その直を越すと演算増幅器OPIの
出力電圧eOは正の方向に立ち上ると共に、ダイオード
D1は導通しダイオードD2は非導通になり、初めの時
と同様な状態になる。この様にしてビーク位置Pは検出
される。
Subsequently, when the input voltage ei starts to increase, the operational amplifier OPI
The voltage between the inverting input terminal and the non-inverting input terminal of is the voltage Vf,
It gradually became smaller than the box of
1 point in Figure (b)), the output voltage eO of the operational amplifier OPI rises in the positive direction, and the diode D1 becomes conductive and the diode D2 becomes non-conductive, returning to the same state as at the beginning. Become. In this way, the beak position P is detected.

さらに入力電圧e1として第6図(d)に示すごとく、
全体として負の電圧で変化している場合においても、相
対的に各素子間の電圧は前記と同様であるので同様にビ
ークPの位置は検出される。
Furthermore, as shown in FIG. 6(d) as the input voltage e1,
Even when the overall voltage is negative, the relative voltage between each element is the same as described above, so the position of the peak P can be detected in the same way.

ただしその時の出力電圧eOは第6図(e)のようにな
る。
However, the output voltage eO at that time is as shown in FIG. 6(e).

このように第5図の回路によれば、入力電圧の周波数に
依存することが少なく、かつ従来のものでは検出出来な
かった負の電圧範囲においてもビ(9) −り位置の検出が可能であるという利点がある。
In this way, according to the circuit shown in Figure 5, there is little dependence on the frequency of the input voltage, and it is possible to detect the bias position even in the negative voltage range, which could not be detected with conventional circuits. There is an advantage to having one.

なお、上述の実施例では演算増幅器OP2によるバッフ
ァを用いていたが、出力インピーダンスの低い信号源か
ら電圧を入力する場合には、バッファを用いない第7図
のような構成でも良い事は云うまでもない。本発明の第
2実施例を示した第7図の動作は第5図と全く同じであ
るので、同一部材には同一図番を付し説明を省略する。
In addition, in the above embodiment, a buffer using the operational amplifier OP2 was used, but it goes without saying that if a voltage is input from a signal source with low output impedance, a configuration as shown in FIG. 7 without using a buffer may also be used. Nor. The operation of FIG. 7 showing the second embodiment of the present invention is completely the same as that of FIG. 5, so the same parts are given the same numbers and the explanation will be omitted.

また、第5図、第7図において、ダイオードD1、D2
の接続方向を逆にすれば入力電圧の最小位置が検出出来
るのは当然である。
In addition, in FIGS. 5 and 7, diodes D1 and D2
It goes without saying that the minimum position of the input voltage can be detected by reversing the connection direction.

さらに第8図に示すごとく、第7図の回路に演算増幅器
OP 2’を加えることにより、第9図(a)の信号e
i、e’、ei“いずれの場合も、同第9図(b)に示
すようにビークPの位置が演算増幅器OP2の出力端子
に矩形波として検出される。なお、第9図(e)に演算
増幅器OPIの出力端子の電圧eOを示す。
Furthermore, as shown in FIG. 8, by adding an operational amplifier OP2' to the circuit in FIG. 7, the signal e in FIG.
i, e', ei" In any case, the position of the beak P is detected as a rectangular wave at the output terminal of the operational amplifier OP2 as shown in FIG. 9(b). In addition, as shown in FIG. 9(e) shows the voltage eO at the output terminal of the operational amplifier OPI.

もちろん第9図の回路は第3図(a)のごときパルス的
入力に対しても使用できる。
Of course, the circuit of FIG. 9 can also be used for pulsed inputs as shown in FIG. 3(a).

(10) 以上の様に本発明によりば、パルス的入力及びくり返し
入力に対しても各々のピーク位置を検出できるのみなら
ず周波数依存度も小さく、かつ直流分が多く含まねてい
る信号においてもピーク位置が検出々来るという利点が
ある。
(10) As described above, according to the present invention, not only can each peak position be detected even for pulsed inputs and repetitive inputs, but also the frequency dependence is small, and even for signals containing a large amount of DC component. There is an advantage that the peak position can be detected every time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来のピーク検波回路の回路図、第
3図は第1図の各部の波形図、第4図は第2図の各部の
波形図、第5図は本発明の一実施例の回路図、第6図は
第5図の各部の波形図、第7図及び第8図は本発明の他
の実施例の回路図、第9図は第8図の各部の波形図であ
る。 〔主要部分の符号の説明〕 OPI・・・・・・・・・・・・演算増幅器C・・・・
・・・・・・・・・・・・・・コンデンサD1、D2・
・・・・・・・ダイオード。 (]1) 矛5図 、t−6図 /−1=″7図 りり 矛q囚
Figures 1 and 2 are circuit diagrams of conventional peak detection circuits, Figure 3 is a waveform diagram of each part in Figure 1, Figure 4 is a waveform diagram of each part in Figure 2, and Figure 5 is a diagram of the waveform of each part in Figure 2. A circuit diagram of one embodiment, FIG. 6 is a waveform diagram of each part in FIG. 5, FIGS. 7 and 8 are circuit diagrams of other embodiments of the present invention, and FIG. 9 is a waveform diagram of each part in FIG. 8. It is a diagram. [Explanation of symbols of main parts] OPI・・・・・・・・・Operational amplifier C・・・・
・・・・・・・・・・・・・・・Capacitor D1, D2・
·······diode. (]1) 5 figures, t-6 figures/-1 = ″7 figures, q prisoner

Claims (1)

【特許請求の範囲】[Claims] 演算増幅器の反転入力端子と共通端子との間にコンデン
サを接続し、前記反転入力端子と前記演算増幅器の出力
端子との間に第1のダイオードを設けると共に、前記反
転入力端子と前記演算増幅器の非反転入力端子との間に
第2のダイオードを設け、前記出力端子と前記非反転入
力端子間で前記第1のダイオードと前記第2のダイオー
ドとが同方向になる如く互いの向きを定め、前記非反転
入力端子と共通端子との間に入力電圧を印加し、前記出
力端子と共通端子との間から出力電圧を取り出す如く成
したことを特徴とするピーク検波回路。
A capacitor is connected between the inverting input terminal of the operational amplifier and a common terminal, a first diode is provided between the inverting input terminal and the output terminal of the operational amplifier, and a first diode is provided between the inverting input terminal and the common terminal of the operational amplifier. a second diode is provided between the non-inverting input terminal, and the first diode and the second diode are oriented in the same direction between the output terminal and the non-inverting input terminal; A peak detection circuit characterized in that an input voltage is applied between the non-inverting input terminal and a common terminal, and an output voltage is extracted from between the output terminal and the common terminal.
JP20020282A 1982-11-15 1982-11-15 Peak detecting circuit Granted JPS5990407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20020282A JPS5990407A (en) 1982-11-15 1982-11-15 Peak detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20020282A JPS5990407A (en) 1982-11-15 1982-11-15 Peak detecting circuit

Publications (2)

Publication Number Publication Date
JPS5990407A true JPS5990407A (en) 1984-05-24
JPS6333326B2 JPS6333326B2 (en) 1988-07-05

Family

ID=16420493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20020282A Granted JPS5990407A (en) 1982-11-15 1982-11-15 Peak detecting circuit

Country Status (1)

Country Link
JP (1) JPS5990407A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59118511U (en) * 1983-01-28 1984-08-10 株式会社新潟鐵工所 Sewage storage device for concrete mixer truck
CN111721999A (en) * 2020-06-30 2020-09-29 上海创功通讯技术有限公司 Peak voltage detection circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59118511U (en) * 1983-01-28 1984-08-10 株式会社新潟鐵工所 Sewage storage device for concrete mixer truck
JPS6237688Y2 (en) * 1983-01-28 1987-09-26
CN111721999A (en) * 2020-06-30 2020-09-29 上海创功通讯技术有限公司 Peak voltage detection circuit

Also Published As

Publication number Publication date
JPS6333326B2 (en) 1988-07-05

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