JPS5989082A - Picture information processor - Google Patents

Abstract

PURPOSE:To obtain excellent reproduced pictures by driving in parallel two horizontal shift registers after storing the information of one line to both shift registers. CONSTITUTION:Horizontal shift registers 1, 3 and 4 store the charge information equvalent to a horizontal line respectively. The external signal is led to a register 1 from an input terminal 16 via a voltage charge converting circuit 2 and then sent in parallel to a memory 2. The electric charge of the memory 2 is stored in registers 3 and 4 with each pair of lines and then read out approximately at a time. Then the even line information is recorded on a disk; while the odd line informationis successively stored in the memory 2. Thus the reading is over with a field. The odd line information is read out of a processor via an amplifier 5 in the 2nd field and recorded on a disk.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image information processing device. In particular, the present invention relates to a processing device F1 for converting 1 second worth of image information into a signal suitable for 1V reproduction.

A conventional television camera is configured to form a 17-frame screen with 2941 fields by sequentially supplying image information of each field taken at different times to a television monitor.

Therefore, for a moving subject, although the images for each field are different, this does not pose much of a problem when viewed as a continuous image.

However, when viewed as a still image, the IC must first record the conversion of these two fields in a memory such as a 9° recording medium, and then replay the two fields over and over again, making the images of each field different in time. Time 7') Since the glass is moving, the problem is that the subject's image is blurred by clothing, ivy, etc.

On the other hand, there is also a method called field skimming for still image reproduction. When shooting with Fi, record one field at a time, and P3. 2 images of this 1 field force at birth
This is a method of forming one frame by reproducing the image twice, but this method has the drawback that the resolution is low and the image quality is poor.

Therefore, a method has been proposed in which an excitation field for two fields is formed at the time of photographing, and each field is interlaced and reproduced when this is monitored.

However, for that reason, the image of CCD, MOS, etc.
All the image information formed in the odd or even lines/edges must be read out, and the remaining lines must be read out afterwards.

In order to realize f'L, an example is an Innotar line type CC.
Although it is possible to use X-Y address type sensors such as L) and M (JS (VQ construction is also messy.

On the other hand, the frame transfer type (CI) 1-1 generally has only a transfer electrode, so the υ1-J ratio is large;
It has excellent visibility and resolution, and is easy to manufacture.

However, it is said that the frame transfer type CCDT cannot read out odd lines and even lines separately for each field.

The purpose of the present invention is to provide an iAi image information processing system that can overcome the drawbacks of the prior art.One feature of the present invention is to provide an iAi image information processing system that can overcome the drawbacks of the prior art. The point is that it is read out in the same way. Another feature is that one of the parallel readout outputs is read out after at least one field delay type.

Also, for this purpose, the memory section in which information was stored up to 1'L was used as a delay memory.

In addition, two horizontal shift registers are provided in order to perform the parallel output of 2 lines/2 lines as described above with pJ function.

Other features of the present invention are clearly defined as VC as explained below.

Below is a detailed explanation of failures based on the examples.
cormorant. t61" indicates the configuration of the half-camera body device that was unexploded during Q14 VC week.
, 4 is a horizontal shift register that corresponds to one horizontal line. It has a capacity to accommodate 7'A. 2 is a memory section that stores image information for one frame;
? I'J transfer machine is capable of transfer. 5 and 6 are output amplifiers, and 7 is an output terminal of the amplifier 5. Reference numeral 16 denotes an external gLl signal input terminal, and an eight-digit voltage/charge depletion conversion circuit. For example, the memory section is composed of a plurality of shift registers, and each register may be exposed to perform a dog-to-horse conversion function. You may also configure it so that it is transferred. Note that the memory section 2 simply converts the signal input from the external 1.3 input terminal 16 into 2.
It can be used to separate fields, or it can be used as a memo'J
Light on rjli 2? Shutter total η for selective incidence
〈'Structure structure J that performs all conversion of light 1 in the memory section-
(Also good.

Book: g'j, l! 4 has the characteristics of a ten-dimensional body device having the structure as shown in the first figure.

ffs 2 nq ti book Jri QIJ i/ζ related ILlil image'IW 4iJ processing outfit: D1.1
and - (...1 is not shown, m - (the same as the 1st and 4th one is the same E, the right 1 is /'1.1゛o, the middle 9 is the recording circuit,
12 is a storage head, 13&''1 disk-shaped recording medium, 1
4 is a motor, 10'; 4. The control circuit according to the invention drives a half-body device at a timing similar to that of the previous one.
Su Z. Reference numeral 11 denotes a synchronization signal generation mustache for supplying a reference synchronization signal to the motor 14 input control circuit 1o. Since it is structured in this way, as will be explained in detail later, the memory 2
Registers 3, 41/il in pairs for each 2 lines
:Stored, and then read out the rfF direction ft in each register almost simultaneously. Then, the even number line information is recorded on the disk, the odd number line information is stored in the memory 2, the reading of one field is completed, and the odd number line information is stored in the second field via the amplifier 5. The data will be read out from the processing device of the present invention and recorded on the disc. Incidentally, the disc is constructed so that one track can record one field's worth of signals.

3 and 4 are diagrams for explaining the operation of the image information processing apparatus of the present invention shown in FIGS. 1 and 2. Items with the same reference numerals as in FIGS. represent. The memory section 2 shown in FIG. 3 is composed of A4×4 bit pixels on the wb side. Reference numerals 18 to 20 are gates for controlling the movement of the memory section 2 and the horizontal shift registers 1, 3.4-. Further, φ, to φ4 charge shift pulse input terminals, GX, GY, and GZ are gate control input terminals.

Also, l-7 is a switch circuit, which inputs external inputs to the horizontal shift register 1 as input means, i, j.
Select the signal from JR and register number 121 from register 4.
It is for guiding purpose.

FIG. 5 shows 1"-1 from the first illustrated device control circuit 10.
This is a diagram showing an example of the timing of the Rikishiki code. Although not shown, the charge in the CCD is once cleared before time t1. Then time 1. -12 and the shutter is opened to form a predetermined amount of image signals in the memory section 2. Then, from time t3 to time t4, the shift pulse input terminal φ1 and
fli control input terminal ox y, . . . By setting the high level, the electric light in the memory section 2 is shifted by one line, and the gate 18 is opened and the l line/th charge A shown in the third figure is shifted.
1- input is stored in the horizontal shift register 3. Next, the gate 19 is opened by supplying a pulse to the input terminal ( ) Y, and the charges in the register 3 are further stored in the horizontal shift register 4 . Next, by setting the ++S pulse input terminal φ1 and the gate input terminal OX to a high level from time t to time t6, the charge in the memory section shown in the third figure is further shifted downward by one line, and the charge is shifted downward by one line as shown in the fourth figure. The electric charge that met my eyes ■chi~
B4 is stored in the horizontal shift register 3. Then, by supplying pulses as shown in the figure to the input terminals φ2 to φ4, each shift register 3 to 5'ft is driven in parallel in the horizontal direction, and from the output terminal 7 as shown in the figure m? 171B, . Then, from time t to t8, the input terminal G
By supplying pulses as shown in the ZVc diagram, 2 shown in the third diagram
The charges A and -9 of the line are stored in the fourth line of the memory section 2. By repeating this sequence once again, the charges A1 to A4' shown in the third diagram are generated. ! : On the second line of the memory section 2, the charges C and -C are stored in the fourth line, and the charges D1 to J)4 shown in the third diagram are read out from the output terminal 7.

Next, by repeating such a sequence, the charges A, -A, , C, which are odd numbered lines / shown in the third diagram are obtained.
~Read C4.

As the information of the mercy 2 field, the order i1 field was entered. The signals are outputted from the output terminal 7 one by one.

In the present invention, since the information for two fields is obtained from one output terminal in this way, +1'' η formation is simplified when recording or the like.

FIG. 5 shows another embodiment of the present invention. In this embodiment, the shift registers 1 and 4 shown in FIG. 1 are connected by a CCD structure 4'. By configuring in this way, the number of output amplifiers 5 can be reduced to only one. Therefore, compared to the configuration shown in FIG. 1, for example, it is possible to eliminate signal fluctuations from field to field due to variations between amplifiers. In this embodiment, the focus number U of the U-CCD 4' is the horizontal shift register 1,
It is set to an integral multiple of the number of hints in 3.4. This has the effect that the charge is shifted from the register 4 to 1 in synchronization with the read timing of the register 3.

In the embodiments shown in FIGS. 1 to 5, the horizontal shift register 3,
The output of the white lower register of 4 is input to register l, but the output of upper register 3 is input to register 1,
It goes without saying that the output of register 4 may be read out via an amplifier instead.

Next, FIG. 6 is a diagram showing a third embodiment of the present invention, and FIG. 7 is a diagram showing a fourth embodiment. The feature is that all the light receiving sections 15 are provided so that image information can be input in parallel. This eliminates the need to use a shutter as long as the memory section is shielded from light and the image can be incident only on the light receiving section.

That is, the electric charge of the light receiving section 15 may be discharged prior to imaging, and the electric charges accumulated in the light receiving section may be stored in the memory section 2 after a predetermined period of time has elapsed. Thereafter, by performing driving in the same manner as described in FIGS. 1 to 4, signals of two fields can be obtained from the output terminal 7 successively one field at a time.

As explained above, according to the present invention, once stored information for one frame can be converted into two field outputs for each field by a simple fi-Vj configuration.

[Brief explanation of the drawing]

1N shows an example of a semiconductor device suitable for the 4 invention, and 1J shows an example of a semiconductor device suitable for the present invention.
Figure 3 is a diagram showing an example of the image information processing device of the present invention.
FIG. 4 is a diagram showing an example of the drive timing of the IJ control circuit 10 of the present invention, and FIG. 5 shows other examples of the cow conductor device suitable for the present invention. Figures 1-7 are the third and fourth Ushienoki VI devices suitable for the present invention. It is a figure showing a 4th example. 1.3.4...Horizontal shift register, 2...Memory section, 5.6...tl, i amplifier, 8...m pressure~
Free load conversion section. 16...External image number input terminal. Patent Applicant Canon Co., Ltd. Procedural Amendment (Method) Commissioner of the Patent Office Kazuo Wakasugi 1 Case Description 1981 Patent Application No. 120801 2
Name of the invention Image information processing device 3 Person making the amendment/Relationship with the 1r matter Patent applicant Location Tokyo Metropolitan II] Shimomaru f-3-30-2 Name (too)
Canon Co., Ltd. Canon Co., Ltd. (Telephone: 758-2111 > 5. Date of amendment order: November 29, 1982 (shipment date) 6. Application subject to amendment and specification 7. Contents of amendment (1) As shown in the attached sheet. Stamp clearly after the name of the patent applicant's agent on the application. (2) Print the specification as attached (no changes to the contents).
0

Claims (1)

[Claims] ], a memory section capable of storing information for 11 pages of jLj;
two registers capable of storing information on two horizontal lines of ks ttz in the memory section, a path for inputting the output of one of the registers to the neJ memory section, and one line of information on each of the two registers. , and then push both registers to dynamically drive the VC.
- An image information processing device for viewing.