JPS5989050A - Frame synchronism pull-in system - Google Patents

Abstract

PURPOSE:To improve a synchronism pull-in system by providing a frame synchronizing bit and code inserting circuit to the transmission side to prevent the pseudo synchronism pull-in to accelerate the synchronism pull-in. CONSTITUTION:The reception side of a PCM end office device detects a step-out and transmits a signal to inform the step-out to the transmission side. In this case, a switch SW2 of the transmission side is switched to the side of a control signal generating part 13, and a switch SW3 is closed by the control signal of the part 13. As a result, the frame synchronizing bit given from a frame synchronizing bit pattern generator 7 is put into the production process of data together with a code train decided previously by a code train generator 14. Then the data of frame structure including frame synchronizing bit regions 5- 5'' and data regions 12-12' formed with a code train (110010) are transmitted to the reception side from the transmission side. The reception side monitors only the original frame synchronizing bit with elimination of the pseudo synchronism pull-in. Thus the synchronism pull-in is accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a frame synchronization pull-in method that can shorten the synchronization pull-in time and prevent pseudo-synchronization pull-in when a PCM terminal station device is out of frame synchronization.

(b) Prior Art and Problems The frame synchronization pull-in method will be explained using FIGS. 1 to 4.

Fig. 1 is a conceptual diagram of a PCM terminal equipment, Fig. 2 is a frame configuration diagram of a signal in a conventional example, Fig. 3 is a block diagram of a frame synchronization bit insertion circuit on the transmitting side in a conventional example, and Fig. 4 is a conventional example. This is a block diagram of a frame synchronization detection circuit on the receiving side in the case where the data area is 6 bits.

In the figure, 1 and 2 are terminal equipment, 3 and 4 are transmission lines, 5, 5',
5'', 5'' are frame synchronization bit areas, 6, 6', 6
``, 6'' are data areas, 7 is a frame synchronization bit pattern generator, 8, 8', 8'', 8'' are 1-bit shift registers, and 9, 9', 9'' are 6-bit shift registers. 1 with 1-bit shift register 8, 8', 8''
It is for one frame. 10 is a NOT circuit, 11 is an AND circuit, and SW1 is a switch.

The frame structure of conventional data is as shown in Figure 2, with frame synchronization bit areas 5, 5', 5'', 5 at the beginning of each frame.
'' and data areas 6, 6', 6'', 6'', for example, frame synchronization bit areas 5, 5', 5'', 5
'' are respectively configured as "1", "0", "1", and "1", and the data is received from the transmitting section of the terminal device 1 shown in FIG. Synchronization is performed by detection.Frame synchronization bit area 5
, 5', 5'', 5'' are the above frame synchronization pits "1"
Inserting ``0'', ``1'', and ``1'' means that if the data area is 6 bits in FIG.
', 5'', 5'', the switch SW1 is controlled to be connected to the frame synchronization bit pattern generator 7 side that sequentially generates frame synchronization bits "1", "0", "1", and "1";"1","0","1", and "1" are sequentially inserted into the frame synchronization bit areas 5, 5', 5'', and 5''. Of course, when the data is in the data areas 6, 6', 6'', 6'', the switch SW1 is connected to the data side. In Figure 4, the frame synchronization bit is detected on the receiving side by sequentially sending the received data string to the shift register and placing the frame synchronization bit in the 1-bit shift register 8, 8', 8'', 8'' position. When "1", "0", "1", and "1" are received, the output of the AND circuit 11 becomes "1" level, and the frame synchronization bit can be detected. However, in this method, "1
If codes such as ``0'', ``1'', and ``1'' exist, there is a high possibility that pseudo synchronization will occur during the synchronization process.For this reason, in order to prevent this, conventionally, frame synchronization bits were set between several frames of the subsequent data string. Monitors “1” and “0”
Since the synchronization pull-in state is established after confirming that the codes "1" and "1" can be detected one after another at intervals of one frame, there is a drawback that it takes time.

In FIG. 1, when the receiving section of the terminal device 2 detects an out-of-synchronization, for example, the transmitting section sends a signal indicating that the synchronization is out to the terminal device 1 via the transmission path 4 until the synchronization pull-in state is reached. Continue to do so. This indicates that the data transmitted from the terminal device 1 cannot be correctly received by the terminal device 2 during that time.

(e) Object of the Invention The object of the present invention is to provide a frame synchronization pull-in method that eliminates the drawbacks of the conventional frame synchronization pull-in, shortens the synchronization pull-in time when frame synchronization is lost, and prevents pseudo-synchronization pull-in.

(d) Structure of the Invention In order to achieve the above-mentioned object, the present invention has the object of The device transmits the out-of-synchronization signal from the receiving side by inserting a code string having a predetermined configuration in a position other than the frame synchronization bit insertion position in the frame configuration of the transmission data being received, and The device performs synchronization pull-in using the newly inserted code string as a synchronization bit, and after synchronization pull-in, the transmitting device switches to the original frame synchronization bit configuration, and the receiving device only uses the original frame synchronization bits. It is characterized by synchronous bit monitoring.

(e) Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. FIG. 5 is a frame configuration diagram of the embodiment of the present invention, FIG. 6 is a block diagram of the frame synchronization bit and code string insertion circuit on the transmitting side of the embodiment of the present invention, and FIG. 7 is a reception diagram of the embodiment of the present invention. In the block diagram of the frame synchronization detection circuit on the side, the data area is 6.
This is the case for bits.

In the figure, parts having the same functions as those in FIGS. 2 to 4 are indicated by the same symbols. 12, 12', 12'', 12'' are 1 in the data area.
2 and 12' show a case where a predetermined code string is inserted. 13 is a control signal generation unit when synchronization is lost; 1
4 is a code string generator, 15 and 15' are 6-bit shift registers, 16 to 21 are NOT circuits, 22 to 24 are AND circuits, SW2 to SW4, S1, S2 are switches, R1,
R2 indicates resistance.

In the case of the present invention, when the receiving unit of the terminal device 1 shown in FIG. “0”“
The switching transmitter transmits 1" and 0 as data. FIG. 5 shows an example of data areas 12, 12', 12",
'' is 6 bits, and "1", "1", "0", "0", "1", and "0" are inserted into the 6 bits of the data areas 12 and 12'. A method of inserting a predetermined code string will be explained with reference to Fig. 6.The switch SW2 is switched to the solid line side by the control signal indicating that the synchronization is lost, and the control signal from the control signal generation section 13 when the synchronization is lost is activated. When the switch SW3 is connected, and during data frame configuration, the frame synchronization bit from the frame synchronization bit pattern generator 7 and a predetermined code string from the code string generator 14 (for example, "1", "1", "0") ”“0”
While inserting "1" and "0", switch SW4 is switched to the solid line side. By doing this, while receiving a signal indicating that synchronization has been lost, in addition to the frame synchronization bit, data areas 12, 12', such as "1", "1", "0", " 0”, “1”, and “0” can be inserted. Of course, when the signal indicating that synchronization is lost disappears, switch SW2 is switched to the dotted line side, and switch SW2 is switched to the dotted line side.
3 is also opened, and the switch SW4 is controlled by the synchronization control signal of 7 times the 1 bit as in the case of FIG. Bit area 5, 5'5'', 5'
When the transmitter of the terminal device 1 in FIG. 1 transmits the data string having the frame structure shown in FIG. Synchronization bit and “1” “1” “0” “0” “1”
Switch to include “0”. This method will be explained using FIG. 7.

The difference between FIG. 7 and FIG. 4 is that the terminals of the 6-bit shift registers 9 and 9' in FIG.
When “1” and “0” come, the outputs of AND circuits 22 and 23 become “1”.
``The shift registers 15 and 15' are provided with NOT circuits 16 to 21 so as to be at the ``level'' and the AND circuit 2.
2 and 23 are provided with switches S1 and S2 that close the frame synchronization detection circuit of the receiving section of the terminal device 2 while the terminal device 2 is transmitting a signal indicating that the synchronization has been lost. and the outputs of the AND circuits 22 and 23 are connected to the switch S1,
The difference is that the AND circuit 24 has a terminal input via S2 other than the terminal for detecting the frame synchronization signal. Frame synchronization is achieved while the transmitter is transmitting a signal indicating that synchronization has been lost in the frame detection circuit shown in Figure 7 (switch S
1 and S2 are connected) The received data string is sequentially sent to the shift register 8 and 8'.
, 8″, 8′″ are frame synchronization bits “1” and “0”.
"1""1" is input, and "1""1""0""0""1""0" is input to the 6-bit shift register 15, 15'.
When this occurs, the outputs of the AND circuits 22 and 23 go to the "1" level, and the output of the AND circuit 24 also goes to the "1" level, indicating that a synchronized state has been achieved. In this case, during the synchronization pull-in process, since the data areas 12 and 12' contain a predetermined code string, pseudo-synchronization does not occur, so once the synchronization state is achieved, the synchronization pull-in state can be established. Because it is possible, the synchronization pull-in time becomes faster. When the synchronization pull-in state occurs, the transmitter of the terminal device 2 in FIG. 1 stops sending out a signal indicating that the synchronization has been lost, so the transmitter of the terminal device 1 in FIG. 1 restores the original frame synchronization as explained earlier. Switching to the bit configuration, in the frame synchronization detection circuit shown in FIG. 7 of the receiving section of the terminal device 2 shown in FIG. 1, the switches S1 and S2 are opened, and the AND circuit 24 side of the switches S1 and S2 is
The "1" level is always supplied from the 5V power supply via the resistors R1 and R2, and the frame synchronization detection circuit is the same as that shown in FIG. 4, and the synchronization bit is monitored using the original frame synchronization bit.

It is better to use the entire data area for the length of the code string output from the code generator 4 in order to prevent pseudo-synchronization, but a certain length may be sufficient as long as it can prevent pseudo-synchronization. In addition, in the frame synchronization detection circuit shown in FIG. 7, only the 6-bit shift register between two frames with frame synchronization bits "1" and "0" is used as the shift register 15 for code string monitoring.
, 15' is set because in this case, synchronous pull-in is possible if these are monitored.

(f) Effects of the Invention As explained in detail above, according to the present invention, pseudo-synchronization is eliminated and synchronization can be achieved very quickly when synchronization is lost.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of a PCM terminal equipment, Fig. 2 is a frame configuration diagram of a signal in a conventional example, Fig. 3 is a block diagram of a frame synchronization bit insertion circuit on the transmitting side in a conventional example, and Fig. 4 is a conventional example. 5 is a block diagram of a frame synchronization detection circuit on the receiving side, FIG. 5 is a frame configuration diagram of an embodiment of the present invention, and FIG. 6 is a block diagram of a frame synchronization bit and code string insertion circuit on the transmitting side of an embodiment of the present invention. , FIG. 7 is a block diagram of a frame synchronization detection circuit according to an embodiment of the present invention. In the figure, 1 and 2 are terminal equipment, 3 and 4 are transmission lines, 5, 5',
5'', 5'' are frame synchronization bit areas, 6, 6', 6
″, 6′″, 12, 12′, 12″, 12′″ are data areas, 7 is a frame synchronization pit pattern generator, 8, 8
', 8'', 8'' are 1-bit shift registers, 9, 9
', 9'', 15, 15' are 6-bit shift registers,
10, 16-21 are knot circuits, 11, 22-24 are AND circuits, 13 is a control signal generator, 14 is a code string generator, SW1-SW4, S1, S2 are switches, R1, R2
shows resistance.

Claims (1)

[Claims] In a PCM terminal device, when the receiving device detects an out-of-synchronization and sends a signal indicating that the synchronization has been lost to the sending device, the sending device receives the out-of-synchronization signal from the receiving device. A code string having a specific pattern is inserted and transmitted at a position other than the frame synchronization bit insertion position in the frame structure of medium transmission data, and the receiving device also synchronizes the code string having the specific pattern as a synchronization bit. A frame synchronization pull-in method characterized in that after synchronization pull-in, the transmitting side device switches to a normal frame synchronization bit configuration, and the receiving side device monitors the synchronization bit using only the original frame synchronization bit.