JPS5989035A - Up-down counter - Google Patents

Abstract

PURPOSE:To actuate accurately an up-down counter by erasing both count-up and-down clocks in case a count-up pulse overlaps a count-down pulse. CONSTITUTION:When a count-up pulse I1 does not overlap a count-down pulse I2, a timing shift exists between outputs Q2 of shift registers 301 and 302. Therefore no clear pulse S1 is produced from an AND gate 303, and an up-down counter 305 performs a prescribed count-up/down operation. If the pulse I1 overlaps the pulse I2, an overlap is produced for the outputs Q2 of the registers 301 and 302. Therefore, the pulse S1 is set at logic ''1'' to reset both registers 301 and 302. As a result, no pulse is delivered to an output Q4, and no change is caused for the state of the counter 305.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an up-down counter 4, and more particularly to a counter having a count-up clock input and a count-down clock input.

The conventional up/down counter can be explained using the circuit diagram of FIG. 1 and the waveform diagram of FIG. 2 which explains its operation. When counting up, set the DOWN input to logic 10M and input the clock to the UP terminal. vice versa,
When counting down, use UP large input logic '11,
Input the clock to the DOW2J terminal. As mentioned above,
If the count-up pulse and count-down pulse do not overlap, the system operates normally, but if they do, only one pulse takes priority and malfunctions occur.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks, and to provide an up-down counter that erases both clocks when the count-up pulse and count-down pulse overlap, and operates normally.

Next, the present invention will be explained in detail with reference to the drawings.

FIGS. 3 and 4 are circuit diagrams showing an embodiment of the up/down counter of the present invention and waveform diagrams illustrating its operation. In Figure 3, step 1 is a count up pulse,
2 is a countdown pulse, 3 is a clock pulse for the shift register, and 2 is a clear pulse for the shift register. Further, 301 and 302 are shift registers, 303 is an anti-game that detects overlapping pulses, and 3
04 is an inverter for inverting the clock pulse generator 3, and 305 is a conventional up/down counter. For example, an up/down counter having the configuration shown in FIG. 1 may be used. The pulse widths of count-up pulse 1 and count-down pulse 5 are equal, and the period of lock pulse 3 for shift register is 1 from the bar of those pulse widths.
Set between.

This is to minimize the number of shift register stages. In the waveform diagram of FIG. 4, the first case is shown where the count pulses do not overlap, and since the outputs Q2 of the shift registers 301 and 302 are out of timing, the clear pulse s1 is not generated. Therefore, shift register 30
Since time-shifted pulses are output to the outputs Q4 of 1 and 302, the up/down counter 305 first counts up and then counts down.

Next, a case will be shown in which count-up pulse wave 1 and count-up pulse wave 2 overlap. shift register 301
Since the overlapping cuff rear pulse S1 becomes logic 111 at timing T1, the shift registers 301 and 302 are reset. Therefore, the output Q
No pulse is output to 4, and the up/down counter 30
The state of 5 does not change. Similarly, there is no change at timing T2.

As explained above, the present invention has the advantage that when the count-up pulse and the count-down pulse overlap, both clocks are erased, so that the up-down counter can be operated accurately.

Therefore, the present invention is effective when the count up pulse and count down pulse are asynchronous.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional 7-up-down counter, Fig. 2 is an operation waveform diagram of the circuit shown in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the up-down counter of the present invention, and Fig. 4 is an operating waveform diagram of the circuit of FIG. 3; - Count up pulse I211 + 1 count down pulse E3 e. Clock pulse for shift register S1 ・
Clearance for shift register 301.302・-
Shift register 303, AND gate 304, Φ inverter 305, up/down counter and above Applicant: Suwa Seikosha Co., Ltd. Agent, Chief Patent Attorney

Claims (1)

[Claims] An up-down counter having a count-up clock input and a count-down clock input, and a circuit connected to the clock input of the up-down counter to detect an overlap between the count-up clock and the count-down clock and to erase both clocks.