JPS5985549A - Check code generating and error correcting integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the number of input and output terminals and to attain a large-scale integration for a check code generating and error correcting IC, by using the input terminals of the 1st and 2nd receivers and the output terminals of the 1st and 2nd drivers as the 1st and 2nd common terminals. CONSTITUTION:An IC is provided with the 1st and 2nd receivers 10 and 12, the 1st and 2nd drivers 11 and 13, a check code generating circuit 14, a syndrome generating circuit 15, a decoding circuit 16, a correcting circuit 17, selecting circuits 18 and 19, a writing register, a reading register, etc. The input terminal of the receiver 10 and the output terminal of a driver 11 are connected to a system bus S as common terminals; and at the same time the input terminal of the receiver 12 and the output terminal of the driver 13 are connected to a memory bus M as common terminals. Thus the number of input and output terminals is decreased for a check code generating and error correcting IC, and a large-scale integration is facilitated with said IC.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a check code generation and error correction integrated circuit widely used in information processing devices including storage devices.

When transmitting and receiving data between a first device and a second device, as is well known, a check code generation circuit and an error correction circuit are used to control the error code of the data. It is known to improve sexual performance.

When writing an information code read from a first device into a second device as a write information code (full write), or a part of the information code read from the first device and a second When writing a part of the information code read from the device into the second device as a write information code (partial write), a check code is generated based on each write information code. The generated check code and the write information code are sent to the second device and written therein.

The error correction circuit performs an error check on the read information code based on the information code and check code read from the second device during the read operation. As a result, when all errors are detected, the error bits are corrected and the corrected read information code is sent to the first device. It should be noted that some devices are known in which the error correction circuit functions even during the write operation, and the write information code is used for error diversion and error correction in the same manner as the read information code, thereby further improving reliability. It is being

Since both the check code generation circuit and the error correction circuit are data-based circuits and may involve the exchange of data between them, it is desirable that they be housed in one integrated circuit.

A conventional check code generation and correction circuit of this type includes a check code generation circuit that generates a check code based on an information code from at least a first device during a write operation, and a check code generation circuit that generates a check code based on an information code from a second device at least during a read operation. It includes an error correction circuit that performs error checking and error correction of the information code based on the information code and the check code.

In such a conventional configuration, each of the check code generation circuit and the error correction circuit is separately connected to the first device and the second device.
Since it is necessary to provide input terminals and output terminals between the integrated circuit and the device, the number of internal terminals (chip terminals) as well as the external terminals of the integrated circuit increases, resulting in a disadvantage that the chimp size becomes large.

An object of the present invention is to provide a check code generation and error correction integrated circuit that has a small number of input/output terminals and is suitable for large-scale integration.

The integrated circuit of the present invention includes a first luciver that receives an information code on a first bus during a write operation, and a check code that generates a check code based on a write information code that includes at least the output of the first luciver during the write operation. a code generation circuit; a second driver that transmits the write information code and the check code on the second bus during the write operation; and a second driver that receives the information code and the check code on the second bus during the read operation at least. and a second receiver whose input terminal is the same as the output terminal of the second driver, and at least during the read operation, performs error checking and error correction of the information code on the second bus based on the output of the second receiver. a first error correction circuit that transmits the information code corrected in the error correction circuit during the read operation onto the first bus, and whose output terminal is the same as the input terminal of the first luciver;
It is characterized by being housed on the same board as the driver.

Next, the present invention will be explained in detail with reference to all the drawings.

In FIG. 1 showing a block diagram of a first embodiment of the present invention, the present embodiment includes a second receiver 1o, a first driver 11, a second receiver 12 . ! :, 42 driver 13, check code generation circuit 14, syndrome generation circuit 15
, a decoding circuit 16, a correction circuit 17, two selection circuits 18 and 19, a read register IA, a read output register IB, and two write registers 1c and ID.
and a write output register IE.

The input terminal of the second receiver 100 and the output terminal of the first driver 11 are shared and connected to the system bus S. Further, the input terminal of the second receiver 12 and the output terminal of the second driver 13 are shared and connected to the memory path M.

FIG. 2 is a block diagram showing an example of the use of the first embodiment shown in FIG. 1 (check code generation and error correction circuit 20 in FIG. 2).

Memo! The J fell a m 23 operates between the memory bank 21 and the memory bank 22 and the processor 24 based on signals from the processor 24 (address signal, operation designation signal, activation signal, etc.) 26 and 27, the check code generation and error correction integrated circuit 20, the memory bus M, and the system bus S.

The receiver 25.28 and the driver 26.27 are used to compensate for signal attenuation on the memory bus M and system bus S.

First, during all write operations among write operations,
The memory controller 23 selects one of the memory bank 21 and the memory bank 22 according to the address signal from the processor 24, and the write 11 code from the processor 24 is sent to the receiver 28 for the selected memory bank. ．． The system node S, check code generation and error correction integrated circuit 20, writes via the memory bus M and driver 26. At this time, the check code generation and error correction integrated circuit 20 receives the write from the processor 24 A check code is generated based on the information code, and the generated check code and the above-mentioned write information code from the processor 24 are written to the same memory bank address.

In FIG. 1, the write information code from the processor 24 inputted from the system bus S is received by the receiver 10 in response to timing T1. In this case, all bits of the byte selection signal PS supplied to the selection circuit 18 are set to '1', and all bytes of the write information code from the processor 24 held by the receiver 10 are
They are transferred to the write register IC and the convolution register ID in response to timing T3 and timing T4, respectively. The write registers IC and 11) are configured to receive each write-in information code from the memory bank 21 and the memory bank 22 at timing T3 and timing T4, respectively.

The selection circuit 19 selects and outputs one of the write register IC and the write register I/register b in response to the bank selection signal BS. The write information code from the processor 24 that is selectively output from the selection circuit 19 is sent to the check code generation circuit 1.
4, along with the check code generated based on the write information code, the honor write output register IE is output at timing T5.
is input.

The contents held in the write output register IE (the write information code and check code from the processor 24) are sent from the second driver 13 to the memory bus M in response to timing T2. At the same time, the output of the second driver 13 is transmitted to the second receiver 1.
2, is input to the read register IA in response to timing T7, and is subjected to an error check in the syndrome generation circuit 15. This error check generates a check code from the bite information code from the processor 24.

This is performed by checking the consistency between this check code and the check code input from the reading 1tlL register IA.

As a result of the error check in the syndrome generation circuit 15, if there is no error in the write information code from the processor 24, the system operation continues, and it is possible to continue accessing the memory. If it is found that there is an error in the write information code from the processor 24, the syndrome generation circuit 15 sends the error signal E to the memory control unit 23.
output to stop the system operation.

The above explanation was focused on all write operations in which the byte selection signal PS is all "1n," but the byte selection signal PS
In the case of a partial write operation in which at least one pit of the byte selection signal PS is 0'', the selection circuit 18 receives the read information code from the memory bank for the byte corresponding to the "0" bit of the byte selection signal PS. This memory bank is designated by the bank designation signal B S If (and the read information code read therefrom is transmitted to the second receiver 12 .
Read register IA, syndrome generation circuit 15. The signal is input to the selection circuit 18 via the decoding circuit 16 and the correction circuit 17.

At this time, a test code is inputted from the memory bank together with the bladder evacuation information code to the syndrome generation circuit 15, and an error check is performed on the bladder ejection information code. According to the result of the error check, if the error is misused and the error is a correctable error, the decoding circuit 16 decodes the result of the error check and points it out to the error correction circuit 17. Then, the read information code corrected based on this indication is input to the selection circuit 18.

A part of the read information code input from the correction circuit 17 to the selection circuit 18 and a part of the write information code from the processor 24 input from the second receiver 12 become the write information code, and the above-mentioned entire write operation is performed. It will be treated in the same way as described.

Next, during a read operation, the memory control unit 23 controls the memory bank 2 by an address signal from the processor 24.
1 and the memory bank 22, and the information encoding power from the selected memory bank is transmitted to the receiver 25. Memory bus M, check code generation and error correction integrated circuit 2
0. The data is read out to the processor 24 via the system bus S and the driver 27. At this time, the check code is read from the address of the same memory bank from which the information code was read out, together with the information code, through the receiver 25 and the memory bus M to the check code generation and error correction integrated circuit 20. It is used for error checking of the information code, and if there is a correctable error, it is corrected and sent to the processor 24.

The second receiver 1
The data is accepted at timing T7, and then transferred to and held in the read register IA in response to timing T7.

The read information code and the read check code held in the read register IA are sent to the syndrome generation circuit 15, and the subsequent information code is corrected in the same manner as described for the correction circuit 17 during operation.

The corrected read information code is transferred from the correction circuit 17 to the read output register IB in response to timing T6,
Further, the signal is sent to the system bus S by the first driver 11 in response to timing T1.

The effect of the first embodiment is that even during a write operation, the second receiver 12. By operating the read register 721 and the syndrome generating circuit 15, it is possible to check for errors between the written information code and the check code generated based on the written information code without adding any special circuit. It is.

FIG. 3 shows a second embodiment of the invention, in which the second receiver 1
2, the first driver 31, the second receiver 32, and the second
A driver 33, a check code generation circuit 34, a syndrome generation circuit 35, a decoding circuit 36, a correction circuit 37,
Two selection circuits 38 and 39 and read register 3A
and two write registers 3C and 3D.

Write output register 3E outside the frame surrounded by dotted lines
, a read output register 3B, a third receiver 3G,
The fourth receiver 3F includes the check code generation and error correction integrated circuit of this embodiment, the system bus S, and the memory bus M.
It is externally attached between the The write output register 3E and the read output register 3B correspond to the write output register IE and the read output register IB in the first embodiment shown in FIG. 1, respectively, and the third receiver 3G and the fourth receiver 3F respectively correspond to the read output register These are added to form input busses from the system bus S and memory bus M, respectively, in conjunction with the external attachment of the register 3B and the write output register 3E.

Since the operation of the circuit is the same as that of the first embodiment shown in FIG. 1, the explanation will be omitted.

The first effect of the second embodiment is that the read output register 3
B, write output register 3E, and W This means that the operating margin can be improved.

The second effect of the second embodiment is similar to the effect of the first embodiment.

FIG. 4 is a block diagram showing a third embodiment of the present invention. This embodiment includes a second receiver 40, a first driver 41, a third receiver 42, a second driver 43, a check code generation circuit 44, a syndrome generation circuit 45, a decoding circuit 46, and a correction circuit 47. , selection circuit 48, output register 49, read register 4A, and write register 4
It consists of B.

The third embodiment is not adapted for use with two memory banks as shown in FIG. 2. In response to register byte selection signal RP, selection circuit 48
It operates to input at least part of the write register 4B and part of the read register 4A during a write operation, and to input the data to the read register 4A' during a read operation.

The decoding circuit 46 is configured to cause the byte controller to designate an error only for the byte designated by the code BC and report the error signal E to the memory controller.

Further, the output register 49 serves as both the read output register IB and the write output register IE in the first embodiment shown in FIG. 1, and operates in response to timing T8.

The first effect of the third embodiment is that during a partial write operation, error checking and error correction operations are performed on the read information code from the memory bank, and on the write information code from the processor and the read information code from the memory bank. Since the check code generation operation for the mixed information code is performed in parallel, the speed of the partial write operation is improved.

A second effect of the third embodiment is that the output register can be activated or deactivated.

The third effect of the third embodiment is similar to the effect of the first embodiment.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention. This embodiment includes a second receiver 50, a first driver 51, a second receiver 52, a second driver 53, a check code self-syndrome generation circuit 54, a decoding circuit 56, a correction circuit 57, and a selection circuit 58. , an output register 59, a read register 5A, and a write register 5B.

The fourth embodiment is the third embodiment shown in FIG.
Check code generation circuit 44 with many common parts in circuit configuration
and the syndrome generation circuit 45 are integrated as a horizontal code-syndrome generation circuit 54, and the read/write control signal RW
The difference is that they are used differently depending on the situation. That is, during a write operation, it functions as a check code generation circuit and outputs the generated check code to the output register 59. Also,
During read operation, it functions as a syndrome generation circuit,
The generated undromes are output to the decoding circuit 56.

The effect of the fourth embodiment is that the total number of circuit elements is reduced.

According to the present invention, by employing the above-described configuration, the efficiency of terminal use is increased, so that the number of terminals inside and outside the integrated circuit is small, making it suitable for large-scale integrated circuits and providing a test code that is convenient for mounting design. A generation and error correction integrated circuit can be provided.

[Brief explanation of the drawing]

FIGS. 1, 3, 4 and 5 respectively represent the first embodiment of the present invention. FIG. 2 shows an example of use of the first and second embodiments. 10.30, 40.50...Second receiver, 1
1,31°41.51...First driver, 12
, 32, 42. 52...Second receiver, 13, 3
3,43.53...Second driver, 3G...
...Third receiver, 3F... m4v receiver, 1
4, 34.44...Check code generation circuit, 15°35.45...Syndrome generation circuit, 54.
...Check code conflict syndrome generation circuit, 16,3
6,46゜56・・・Decoding circuit, 17.37,4
7.57... Correction circuit, 18, 19, 38, 3
9,48.58...Selection circuit, IA, 3A, 4
A, 5A...Read register, IB, 3B...
...Vesical output register, IC, ID, 3C, 3D
, 4B. 5B...Shoromi register, IE, 3E...
...Write v1 register, 49.59...Output register, 20...Check code generation and error correction integrated circuit, 21.22...Memory bank,
23...Memory control L24...Processor, 25.28...Receiver, 26.27.
...Driver, S...System bus, M
...Memory bus, Tl, T2. T3. T4. T
5. T6. T7. T8 ・・・・・・Timing, Ps
...Byte designation (g number, BS...bank designation signal, E...error signal, RP...
・Register/byte selection signal, BC: byte control signal, RW: read/write control signal.

Claims (2)

[Claims] (1) a first luciver that receives an information code on a first bus during a write operation; a check code generation circuit that generates a check code based on at least the write information code output from the first luciver during the write operation; a second driver that transmits the write information code and the check code on a second bus during an operation; and a second driver that receives the information code and the check code on the second bus during at least a read operation and has an input terminal. a second receiver shared with the output terminal of the second receiver;
an error correction circuit that performs error checking and error correction of the information code on the second bus based on the output of the receiver; and an error correction circuit that transmits the information code corrected in the error correction circuit during the read operation onto the first bus; A check code generation and error correction integrated circuit characterized in that a first driver whose output terminal is shared with the input terminal of the first luciver is housed in a metal substrate. (2) By causing the second receiver and the error correction circuit to function during the read operation and the write operation, the write information code and the check code generated based on the write information code are also checked. A check code generation and error correction integrated circuit as claimed in claim (1), wherein the check code generation and error correction integrated circuit is characterized in that it is an e% characteristic.