JPS5985164A - Time shift correcting circuit of digital signal - Google Patents

Abstract

PURPOSE:To correct the phase shift by writing a digital signal from a clock extracted from the digital signal transmitted in division and from an address obtained by counting the synchronizing signal, and reading out the signal by an address obtained by counting a reference clock. CONSTITUTION:An input series signal is converted into a parallel signal at a split circuit 6 and recorded on a magnetic tape 8. The reproduced signal is amplified by a reproducer amplifier 13, the time shift correction is attained at a skew jitter correcting circuit 14 and transmitted to a synthesis circuit 11. The skew jitter correcting circuit is provided respectively to each track corresponding to each parallel signal. The clock and the synchronizing signal are separated from a signal reproduced from the track and a write address of a storage circuit is formed by counting it. The readout address is formed from the reference clock and the signal is read out from the storage circuit. Thus, the phase shift and bit shift are corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is designed to reduce the phase shift and bit shift of the digital signal that occurs on the C-beam transmission path when a digital signal is divided into several parts and sent to the receiver (...). The present invention relates to a time lag correction circuit that performs correction.

When the digital signal t is divided into several parts and transmitted, received, and combined into the original signal, time shifts due to phase shifts and bit shifts occur.

The cause of this time lag will be explained with reference to FIG. 1 in the case where the transmission path is between the magnetic head and the entire circumference of the magnetic tape. The head gap 4 of each trunk of magnetic head B has a slight misalignment as shown in Fig. 1 due to manufacturing technology problems.Therefore, the recording magnetic head and the reproducing magnetic head in each trunk are slightly misaligned. A difference will occur in the gap distance. This is the cause of the static time lag. The causes of the @ time lag include those caused by the kA!1IJl system of the magnetic tape, and the deformation of the magnetic tape ( There are some causes such as one caused by the growth of one piece, etc.

BACKGROUND OF THE INVENTION Conventionally, as a circuit for completely correcting the above-mentioned time lag, the circuit shown in Section 2 is known. Referring to FIG. 2 below, an input serial signal is converted into a parallel signal by the dividing circuit 6 and transmitted to the static skew correction circuit 7. The static skew correction circuit 7 corrects the time deviation caused by the physical deviation of the hendogloss 2 of each track of the recording magnetic head 1, and completely eliminates the time deviation between each trunk recorded on the magnetic tape 8. It operates.

When reproducing a signal recorded in this manner, a time lag occurs in the reproduction output of each trunk due to physical misalignment of each trunk gap 4 of the above-mentioned magnetic head for reproduction, bending of the magnetic tape 8, etc.

The time lag caused by each trunk gap 4 is corrected by the E circuit 9, and then the dynamic skew caused by the bending of the magnetic tape 8 is corrected by the dynamic skew correction circuit. 10 and sent to the next synthesis circuit 11. The synthesis circuit 11 corrects the time lag7. :Converts a parallel signal to a serial signal and returns it to the original digital signal. The returned digital signal is sent to the next Syssocou correction circuit 12 to compensate for the periodic time lag caused by the magnetic tape drive system.
2, the original digital signal with no time lag is output.

The disadvantages of such conventional technology are that the static skew correction during recording must be adjusted to approximately the same amount as the physical deviation of each trunk gap of the recording magnetic head; It is necessary to adjust the amount of static skew to be approximately the same as the amount of physical deviation of each trunk gap of the head, and also to correct the static skew during recording and playback. Since the entire dynamic skew is corrected, there are many adjustment points and the correction circuit is complicated. Furthermore, since the adjustment amount changes over time, there is a drawback that circular adjustment must be performed periodically.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, the -1 circuit configuration has no adjustment points in the cylinder, and it is possible to perform jitter correction and interleaving as well as time lag correction.

Structure of the Invention Referring to FIG. 6 below, an embodiment of the time lag correction circuit according to the present invention will be explained in the case where all magnetic tapes and all media are used. An input serial signal is modulated by the dividing circuit 6 and converted into a parallel signal. and record it on the magnetic tape 8.

During reproduction, the recorded parallel signal is amplified by the reproduction amplifier 16 and sent to the skew correction circuit 14.
The signal is transmitted to the skew and Syssocou correction circuit 14, where the time lag is corrected, and then transmitted to the synthesis circuit 11. The converter circuit 11 converts the signal into the original serial signal, and outputs a digital signal without time lag.

FIG. 4 is a detailed diagram of the skew/jitter correction circuit 14, and shows a correction circuit for one track.

To explain below in FIG. 4, 15 is a reproduction amplifier 16.
16 is a demodulation circuit that demodulates the modulated digital signal; 17 is a demodulation circuit that completely separates the same signal from the demodulated digital signal; 18 is a storage circuit for storing all the digital signals, 19 is a synchronous separation circuit;
20 is a crystal oscillation circuit; 21 is a read address counter that counts the output signal of the crystal oscillation circuit; 22 is 1 for storing the digital signal in the storage circuit 18; Address system a< that specifies the address for reading or reading.
The + circuit 26 is a reset circuit which generates all pulses to reset the write address counter 19 and the read address counter 21 at a predetermined time.

Effects of the Invention The following explanation will be given with reference to the signal data form diagrams on the magnetic tape shown in FIGS.
5 and the demodulation circuit 16.

The clock regeneration circuit 15 extracts a clock signal containing skew and jitter components from the input signal, and the demodulation circuit 16 extracts a clock signal containing skew and jitter components from the input signal, and the demodulation circuit 16 reproduces the modulated signal sound based on the lock signal. > Demodulates and outputs to the next synchronization separation circuit 17, and transmits signal data to the primary circuit 18.

The synchronization separation circuit 17 separates only the post-adjusted 1 signal and the p synchronization signal based on the clock signal and outputs it to the next 1 address counter 19.

The write address counter 19 and the C output 1/counter 21 are predetermined by the recent circuit 23 and set to initial values of 1, Wl, R,, Ic,
The three write address counters 19 count and amplify the number of synchronization signals from the initial value W1 using the clock signal. On the other hand, the read address tank 21 changes the output signal of the crystal oscillation circuit 20 to the initial value I? , count up from □.

The above two count values are address system 1n41 lIJ circuit 2 as write address value and read address value respectively.
Dedicated to 2. The address open side 1 circuit 22 switches all write address values and escape address values and outputs them to the storage circuit 18 in response to a switching signal inputted from the crystal oscillation circuit 20.

From the above-mentioned series of operations, for example, trunk A in FIG.
The signal (from the part of the engineering synchronization signal 5YNc) is stored at the address of the storage circuit 18 corresponding to the address value indicated by the 1-inclusive address counter 19 for each bit of data, including skew and jitter components.

Next, data is read out one bit at a time from the address in the storage circuit 18 corresponding to the address value indicated by the read address counter 21 in response to a switching signal from the crystal oscillation circuit 20. Therefore, the output data is output as a signal that does not include skew and jitter components. Also, the difference between the write address value and the read address [direct (input 1 to 1
(It is 1□.

Next, I will explain the entire operation of writing and reading signals from the track A to the trunk 1, the circuit 18, and since it includes all the jitter and jitter at the time of input, each trunk common address is The address value indicated by the counter 19 is not necessarily the same, and the synchronization signal 5YN is applied to each trunk.
Contrasting with the position of e, 1 to 1 are sequentially written in the unique circuit 18. reduced.

At the time of reading, the input power is determined and after a time delay, the address value indicated by the read address counter 21 is exceeded. The signal is read out and output to the synthesis circuit 11.

Therefore, by setting the time to be longer than the difference in writing end time of the corresponding data in the determined time-full trunk and longer than the time that can absorb all the jitter, the output from the combining circuit 11 is made. The signal becomes the original digital signal without jitter components.

It is also known that interleaving, which is well known to prevent data loss caused by bursts, can be performed, and the relationship between the input signal to the 11 circuit 6 and the address value specified by the read address counter 21 is set to a predetermined relationship. This can be achieved by the time lag correction circuit according to the present invention.

Effects of the Invention As described above, the present invention includes a means for extracting a clock signal from an input digital signal (clock regeneration circuit 15) and a means for extracting a synchronization signal (the clock separation circuit 17),
A first counter (convolutional address counter 19) that counts the synchronization signal using the clock signal from the preset f value, and a first counter ('A
A second circuit that counts the clock signal (crystal oscillator circuit 20)
7 (read address counter 21), and the first counter and second counter 21 are read by the reference clock signal.
means for switching and outputting the output signal as an address signal (address control output circuit 22), and means for inputting or outputting the digital signal according to the address signal from the outputting means (circuit 18). Therefore, static skew due to misalignment of each gear of the recording magnetic head and each gap of the playback (IB) head, dynamic skew due to deformation such as elongation of a piece of magnetic tape, and the magnetic tape 1 drive system. Alternatively, jitter can be corrected without requiring IL adjustment as in the conventional method, and time fluctuations occurring on the transmission path can also be corrected with the same configuration.

Furthermore, by increasing the memory capacity of the memory circuit, it is possible to correct the time lag by one amount in accordance with the increase, so that data with higher density can be transmitted.

[Brief explanation of the drawing]

Figure 1 shows the positional deviation of the gears in each trunk of the recording magnetic head and the recording magnetic head, and Figure 2 shows the conventional time deviation correction when used as a magnetic tape transport medium. FIG. 6 is a diagram showing the configuration of the time lag correction according to the present invention. FIG. 4 is a configuration diagram showing partial details of the time lag correction in FIG. 6. FIG. 5 is a diagram showing the configuration of the time lag correction according to the present invention. It is a diagram of the data format L[ written on the magnetic tape during correction. ° Placement circuit, 19: Write completion address counter, 20: Crystal excavation circuit, 21: Read address counter, 22 Near address control circuit. Patent application Person Akai Kamiki Co., Ltd. Figure 3 Figure 4 Figure 5 Procedural amendment (voluntary) 2., 1981; 10th January Kazuo Wakasugi, Commissioner of the Japan Patent Office, 1. Time lag correction circuit for display digital signals of the case 3. Relationship with the case of the person making the amendment Patent Applicant's Representative ■ Waki 'E 4, Agent (1) Regarding the above application, regarding the "jitter" from page 4, line 18 to line 19 of the same page in the specification. "Correction and interleaving" is corrected as "jitter correction and deinterleaving j." ``It is a pre-sent circuit that generates a preset pulse at a predetermined time.'' should be amended to ``It is a pre-sent circuit that generates a pre-set pulse at a predetermined time.''
"Reset circuit 23" is corrected to "preset circuit 23j." (Regarding the application No. 41J1, "interleave" on page 9, line 9 of the specification is corrected to "T-interleave." Please correct the extravagance of Figure 4 in the attached sheet.゛

Claims (1)

[Claims] In a digital signal transmission method in which a digital signal is divided into 1-1 broadcast signals and synthesized, a means for extracting a clock signal from the divided digital signal and a means for extracting a synchronization signal are provided. a first counter that counts the synchronization signal from this value according to the clock signal;
a second counter for counting the reference clock signal from a predetermined value; and means for switching the output signals of the first counter and the second counter according to the reference clock signal and outputting them as an address signal. . A digital signal time shift correction circuit comprising means for writing or reading the divided digital signal in accordance with an address signal from the outputting means.