JPS5984590U - Display control circuit for line pattern - Google Patents

Display control circuit for line pattern

Info

Publication number
JPS5984590U
JPS5984590U JP14339383U JP14339383U JPS5984590U JP S5984590 U JPS5984590 U JP S5984590U JP 14339383 U JP14339383 U JP 14339383U JP 14339383 U JP14339383 U JP 14339383U JP S5984590 U JPS5984590 U JP S5984590U
Authority
JP
Japan
Prior art keywords
data
character
line
control circuit
display control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14339383U
Other languages
Japanese (ja)
Other versions
JPS6336359Y2 (en
Inventor
大場 利彦
竪月 忠夫
土田 圭司
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP14339383U priority Critical patent/JPS5984590U/en
Publication of JPS5984590U publication Critical patent/JPS5984590U/en
Application granted granted Critical
Publication of JPS6336359Y2 publication Critical patent/JPS6336359Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はCRT管面上の文字の区画を説明するための正
面図、第2図はドツトの集合で文字を表わした状態を示
す正面図、第3図はけい線データのビット構成を示す構
成図、第4図はけい線メモリへのけい線データの格納状
態を示す説明図、第5図は圧縮されたけい線データを伸
長するためのゲート回路の回路図である。  − 図中、BFはバッファメモリ、Od1〜OG4は゛オア
ゲート群、OR1〜0R32はオアゲートである。
Figure 1 is a front view for explaining the divisions of characters on the CRT screen, Figure 2 is a front view showing characters represented by a collection of dots, and Figure 3 is a diagram showing the bit structure of the line data. FIG. 4 is an explanatory diagram showing how the line data is stored in the line memory, and FIG. 5 is a circuit diagram of a gate circuit for decompressing the compressed line data. - In the figure, BF is a buffer memory, Od1 to OG4 are a group of OR gates, and OR1 to 0R32 are OR gates.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 陰極線管面上に表示せしめる文字図形データを一時格納
するパターンメモリと、個々の文字N−データを表示す
る単位表示領域のうち、けい線を示すためめ各ドツトを
所定数ごとに集合せしめて複数のグループに分割し、各
グループのデータをけい線データとして蓄積するけい線
メモリと、こ、 のけい線メモリより読み出したけい線
データを伸長するためにけい線データの各ビットごとに
所定数のオアゲートを有する伸長手段とを具え、該所定
数のオアゲートを同時に開くことにより圧縮されたけい
線データを伸長す颯とともに、前記パターンメモリから
読み出された文字図形データが該オアゲートに入力され
文字図形データの読み出しに同期してけい線データを復
元して陰極線管面上に文字図形とけい線を表示するよう
に構成したことを特徴とするけい線パターンの表示制御
回路。 −
A pattern memory temporarily stores the character/figure data to be displayed on the cathode ray tube surface, and a plurality of dots are gathered in predetermined numbers to indicate the marking lines in the unit display area for displaying individual character N-data. There is a line memory for dividing the data of each group into groups and storing the data of each group as line data. and a decompressing means having an or gate, which decompresses the compressed line data by simultaneously opening a predetermined number of or gates, and at the same time, the character/graphic data read from the pattern memory is input to the or gate to form a character/graphic data. 1. A display control circuit for a line pattern, characterized in that the line pattern display control circuit is configured to restore line data in synchronization with data readout and display character figures and lines on a cathode ray tube surface. −
JP14339383U 1983-09-16 1983-09-16 Display control circuit for line pattern Granted JPS5984590U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14339383U JPS5984590U (en) 1983-09-16 1983-09-16 Display control circuit for line pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14339383U JPS5984590U (en) 1983-09-16 1983-09-16 Display control circuit for line pattern

Publications (2)

Publication Number Publication Date
JPS5984590U true JPS5984590U (en) 1984-06-07
JPS6336359Y2 JPS6336359Y2 (en) 1988-09-27

Family

ID=30320083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14339383U Granted JPS5984590U (en) 1983-09-16 1983-09-16 Display control circuit for line pattern

Country Status (1)

Country Link
JP (1) JPS5984590U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017135339A1 (en) * 2016-02-02 2017-08-10 ニューフレイ リミテッド ライアビリティ カンパニー Clip, clamp assembly, and mounting structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017135339A1 (en) * 2016-02-02 2017-08-10 ニューフレイ リミテッド ライアビリティ カンパニー Clip, clamp assembly, and mounting structure

Also Published As

Publication number Publication date
JPS6336359Y2 (en) 1988-09-27

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