JPS598424A - Frequency adjusting device - Google Patents

Frequency adjusting device

Info

Publication number
JPS598424A
JPS598424A JP57117198A JP11719882A JPS598424A JP S598424 A JPS598424 A JP S598424A JP 57117198 A JP57117198 A JP 57117198A JP 11719882 A JP11719882 A JP 11719882A JP S598424 A JPS598424 A JP S598424A
Authority
JP
Japan
Prior art keywords
signal
frequency
circuit
input signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57117198A
Other languages
Japanese (ja)
Inventor
Yasuaki Hirai
平井 康昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57117198A priority Critical patent/JPS598424A/en
Publication of JPS598424A publication Critical patent/JPS598424A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Abstract

PURPOSE:To adjust easily an input signal to a prescribed frequency with high accuracy, by using also a microcomputer without using a frequency counter. CONSTITUTION:A beat waveform B is obtained by inputting an input signal A to an amplifier circuit 2 with a limit of gain and mixing the signal at a reference signal generating circuit 1. A signal waveform C is obtained by passing this waveform B through a reference frequency eliminating circuit 5. The input signal A is changed into a signal D having f0 of frequency and a maximum output level by passing the signal waveform C through an LPF6, where f0 is the frequency to be adjusted for the input signal A and the frequency of the circuit 1. The signal D is converted into a digital signal at an AD converter 7 and given to a CPU9 through an input/output circuit 8. The input signal passes through a phase detecting circuit 4 to recognize whether the frequency of the input signal A is larger or smaller than the f0 and it is discriminated whether the output is H or L level and the result is given to the circuit 8. Thus, the frequency adjustment with high accuracy is attained with the comparison of the basic frequency.

Description

【発明の詳細な説明】 本発明は例えば受信機のステレオ復調回路で使用されて
いる電圧制御発振器の周波数調整等を行う場合に適した
周波数調整装置に関し、特に、入力信号を、調整しよう
とする基準信号と混合することによシ、高速で、しかも
正確に基準周波数に調整できるようにしたものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency adjustment device suitable for adjusting the frequency of a voltage controlled oscillator used, for example, in a stereo demodulation circuit of a receiver, and in particular, the present invention relates to a frequency adjustment device suitable for adjusting the frequency of a voltage controlled oscillator used in a stereo demodulation circuit of a receiver. By mixing it with a reference signal, it is possible to adjust to the reference frequency quickly and accurately.

従来よりステレオ受信機等の復調回路における電圧制御
発振器の周波数を調整する場合に、測定ポイントからの
信号を周波数カウンターにょシ数値を読み取りながら基
準周波数に調整している。
Conventionally, when adjusting the frequency of a voltage controlled oscillator in a demodulation circuit of a stereo receiver or the like, the signal from a measurement point is adjusted to a reference frequency while reading the value of a frequency counter.

ところが、このような方法では精度よく調整しようとす
れば調整作業に時間がかかり、高速調整が期待てき々い
という問題があった。低周波においても、このような問
題を解決するために、ゲート時間が短く、しかも桁表示
が多い高精度の高価な周波数カウンターが必要になる。
However, with this method, there is a problem in that the adjustment process takes time to achieve accurate adjustment, and the expectation of high-speed adjustment is tedious. Even at low frequencies, in order to solve this problem, a highly accurate and expensive frequency counter with a short gate time and a large number of digits is required.

本発明は、そのような問題を解決し、周波数カウンター
を使わなくても、マイクロコンピュータとの並用により
、入力信号を決められた周波数に容易に調整することが
可能な高精度の周波数調整装置を提供するものである。
The present invention solves such problems by providing a high-precision frequency adjustment device that can easily adjust an input signal to a predetermined frequency by using a microcomputer without using a frequency counter. This is what we provide.

以下、本発明の実施例について第1図〜第3図とともに
説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 3.

第1図において、1は入力信号の調整しようとする周波
数と同じ周波数の信号を基準信号とじて発生する高精度
の基準信号発生回路、2は入力信号人のレベルを一定に
するための利得制限増幅回路である。上記基準周波数発
生回路1と利得制限増幅回路2の出力信号を混合回路3
に入力して混合し、基準周波数除去回路5にで基準信号
のみを除去する。6は入力信号と基準信号との周波数の
差の信号を、周波数により出力レベルが変化するように
した低域フィルター、7は中央演算処理装置(以下、単
にCPUと云う)9に入力可能にするために低域フィル
ター6の出力信号をディジタル信号に変換するAD(ア
ナログ−ディジタル)コンバータ、4は入力信号Aすな
わち利得制限増幅回路2の出力信号と基準信号発生器1
の出力信号の周波数の値がどちらが大きいかを精度よく
検知するための位相検出回路、8はADコンバータ7の
出力および位相検出回路4の出力が入力される入出力回
路、10は上記CPU9と入出力回路8を結合するパス
ラインである。
In Figure 1, 1 is a high-precision reference signal generation circuit that generates a signal with the same frequency as the frequency of the input signal to be adjusted as a reference signal, and 2 is a gain limiter to keep the level of the input signal constant. It is an amplifier circuit. A mixing circuit 3 mixes the output signals of the reference frequency generating circuit 1 and the gain limiting amplifier circuit 2.
The reference frequency removing circuit 5 removes only the reference signal. 6 is a low-pass filter whose output level changes depending on the frequency, and 7 is a central processing unit (hereinafter simply referred to as CPU) that allows input of the signal of the difference in frequency between the input signal and the reference signal to 9. 4 is an AD (analog-digital) converter that converts the output signal of the low-pass filter 6 into a digital signal, and 4 is an input signal A, that is, the output signal of the gain limiting amplifier circuit 2, and a reference signal generator 1.
8 is an input/output circuit to which the output of the AD converter 7 and the output of the phase detection circuit 4 are input; 10 is an input/output circuit connected to the CPU 9; This is a pass line that connects the output circuit 8.

」二記構成において、第2図(A)に示すような被調整
用のステレオ受信機における電圧制御発振器の信号人を
利得制限増幅回路2に入力信号として入力し、水晶発振
器からなる基準信号発生回路1と混合することによって
第2図(B)に示すようなビート波形Bが得られる。こ
のビート波形Bから、基準周波数除去回路6を通すこと
により第2図(C)に示す信号波形Cが得られる。ここ
で、入力信号人の調整しようとする周波数および基準信
号発生回路1の周波数をfoとすれば、信号波形Cを低
域フィルター6通すことによって第3図の特性により入
力信号Aは、foで出力レベルが最大となる信号りにか
わる。この信号りは次段のADコンバータアでディシイ
タル信号に変換され、入出力回路8を通してCPU9へ
送られる。また、入力信号人の周波数が基準周波数f。
In the second configuration, the signal of the voltage controlled oscillator in the stereo receiver to be adjusted as shown in FIG. By mixing with circuit 1, a beat waveform B as shown in FIG. 2(B) is obtained. From this beat waveform B, a signal waveform C shown in FIG. 2(C) is obtained by passing it through the reference frequency removal circuit 6. Here, if the frequency to be adjusted by the input signal person and the frequency of the reference signal generation circuit 1 are fo, then by passing the signal waveform C through the low-pass filter 6, the input signal A will be fo by the characteristics shown in FIG. The signal changes to the one with the maximum output level. This signal is converted into a digital signal by the AD converter in the next stage, and sent to the CPU 9 through the input/output circuit 8. Also, the frequency of the input signal is the reference frequency f.

より大きいか、小さいかを知るために、位相検出回路4
を通し、その出力がHレベルか、bレベルかで判断し、
入出力回路8へ送る。
In order to know whether it is larger or smaller, the phase detection circuit 4
, judge whether the output is H level or B level,
Send it to the input/output circuit 8.

以上のように本発明は基準周波数との比較により高速で
高精度の周波数調整ができるようにしたものであり、ス
テレオ受信機の復調回路の周波数調整等に実施した場合
には、その調整作業を簡単に自動化することができ、調
整時間を大幅に短縮できるという優れた効果75’!!
’rられる。
As described above, the present invention enables high-speed and highly accurate frequency adjustment by comparing with a reference frequency, and when implemented for frequency adjustment of a demodulation circuit of a stereo receiver, etc., the adjustment work can be performed easily. It can be easily automated and the adjustment time can be greatly shortened, which is an excellent effect75'! !
'r will be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す要部ブロック図、第2
図(A) 、 (B) 、 (C)は第1図における各
部の信号波形し1、第3図にV本発明で使用する低域フ
ィルグーの周波数特性の一例を示す図である。 1 ・・ノ、(Iv信弓発生回路、2・・・利r)制限
増幅回路、3・・・・・混合回路、4 ・・・位石I検
11汁11路、6・・・・)、(71,11周θl数除
去回路、6 ・・・・低域フィルター、7・−・・・A
 D Iンバーク、8・・・・・入出力回路、9・・、
・CPUL。 代即人の氏名 弁用)1.中 1と 敏 男 ほか1名
第1図
FIG. 1 is a block diagram of main parts showing one embodiment of the present invention, and FIG.
Figures (A), (B), and (C) show signal waveforms at various parts in Figure 1, and Figure 3 shows an example of the frequency characteristics of the low-pass filter used in the present invention. 1...ノ, (Iv Shinkyu generation circuit, 2...R) limiting amplification circuit, 3...Mixing circuit, 4...Seki Iken 11 soup 11 path, 6... ), (71, 11 round θl number removal circuit, 6...low-pass filter, 7...A
DI inverter, 8...input/output circuit, 9...,
・CPUL. Name of representative (Benyo) 1. Figure 1: 1st year junior high school student, Toshio and 1 other person

Claims (1)

【特許請求の範囲】[Claims] 入力信号の調整すべき周波数と同じ周波数の信回路の出
力信号から基準周波数を除去する基準周波数除去回路と
、前記基準信号と入力信号の位相を検出する位相検出回
路と、前記基準周波数除去回路の出力信号から、その信
号の最大点を検出する低域フィルターと、その低域フィ
ルターの出力と前記位相検出回路の出力により、人力信
号の調整点を検出する信号処理回路を具備してなること
を特徴とする周波数調整装置。
a reference frequency removal circuit that removes a reference frequency from the output signal of the signal circuit having the same frequency as the frequency to be adjusted of the input signal; a phase detection circuit that detects the phase of the reference signal and the input signal; The present invention includes a low-pass filter that detects the maximum point of the signal from the output signal, and a signal processing circuit that detects the adjustment point of the human input signal using the output of the low-pass filter and the output of the phase detection circuit. Characteristic frequency adjustment device.
JP57117198A 1982-07-06 1982-07-06 Frequency adjusting device Pending JPS598424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57117198A JPS598424A (en) 1982-07-06 1982-07-06 Frequency adjusting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57117198A JPS598424A (en) 1982-07-06 1982-07-06 Frequency adjusting device

Publications (1)

Publication Number Publication Date
JPS598424A true JPS598424A (en) 1984-01-17

Family

ID=14705817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57117198A Pending JPS598424A (en) 1982-07-06 1982-07-06 Frequency adjusting device

Country Status (1)

Country Link
JP (1) JPS598424A (en)

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