JPS598384A - Silicon wiring substrate - Google Patents

Silicon wiring substrate

Info

Publication number
JPS598384A
JPS598384A JP57117024A JP11702482A JPS598384A JP S598384 A JPS598384 A JP S598384A JP 57117024 A JP57117024 A JP 57117024A JP 11702482 A JP11702482 A JP 11702482A JP S598384 A JPS598384 A JP S598384A
Authority
JP
Japan
Prior art keywords
silicon
substrate
layer
row
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57117024A
Other languages
Japanese (ja)
Inventor
Koichi Fujiwara
幸一 藤原
Shigeyuki Tsurumi
重行 鶴見
Yoshiaki Takeuchi
善明 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57117024A priority Critical patent/JPS598384A/en
Publication of JPS598384A publication Critical patent/JPS598384A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the silicon wiring substrate on which a high density mounting of low temperature device elements can be performed by a method wherein both a row of pins and a row of sockets for microconnector are provided on the same silicon substrate. CONSTITUTION:A row of microscopic holes are formed on silicon single crystal substrates 8a and 8b having the face 100 respectively by performing a selective etching, and a microsocket 10 is formed by adhering said two substrates in such a manner that the center of each row of microscopic hole will be coincided with each other. Then, after a niobic film has been formed on the substrate by performing a sputtering method, a required niobic wiring 12 is formed by performing an etching. Then, a micropin 9 is soldered using an indium alloy. The wiring substrate thus constituted is laminated in such a manner that the row of pins and the row of sockets are connected to each other.

Description

【発明の詳細な説明】 本発明は、ジョセフソンコンピュータ等の低温で使用さ
れる電子デバイスの実装に適したシリコン配線基板に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a silicon wiring board suitable for mounting electronic devices used at low temperatures, such as Josephson computers.

従来の配線基板は、それに実装される電子デバイスが常
温付近で使用されるものであったため、半導体や金属に
比べて熱膨張係数の大きい各種有機系プリント基板が使
用されていた。そのためジョセフソン素子など低温動作
の電子デバイスを従来の有機系プリント配線基板に実装
して低温で使おうとしても、シリコンデバイス・テップ
と配線基板間の熱膨張係数の不整合によシ、はんだ接続
部が破壊して実用にならなかった。この改善策としてセ
ラミック配線基板や金属基板配線板が使用されているが
、これでも厳密には熱膨張係数がシリコンデバイス・チ
ップと一致しないため、より一層信頼性の高い配線基板
が望まれていた。
Conventional wiring boards have been used with electronic devices mounted on them at around room temperature, so various organic printed boards have been used that have a higher coefficient of thermal expansion than semiconductors or metals. Therefore, even if you try to use a low-temperature electronic device such as a Josephson element mounted on a conventional organic printed wiring board, there will be problems due to a mismatch in the coefficient of thermal expansion between the silicon device tip and the wiring board, resulting in solder connections. The parts were destroyed and it was not put into practical use. Ceramic wiring boards and metal wiring boards have been used as a solution to this problem, but even these have thermal expansion coefficients that do not strictly match those of silicon devices/chips, so a wiring board with even higher reliability has been desired. .

この要望に答えた従来技術として、ジョセフソン素子実
装用のシリコン配線基板が知らnている。このシリコン
配線基板は、ジョセフソン素子の搭載されている基板を
はじめとして実装基板材料が全てシリコンでできており
、第1図のような構成となっている。第1図において、
1はジョセフソン素子、2と3と4はシリコン配線基板
、5はマイクロコネクタ用ビン(以下、マイクロビンと
称す)、6はマイクロコネクタ用ソケット(以下、マイ
クロソケットと称す)7を有するシリコン基板である。
As a conventional technique that meets this demand, a silicon wiring board for mounting Josephson elements is known. In this silicon wiring board, all mounting board materials including the board on which the Josephson element is mounted are made of silicon, and the structure is as shown in FIG. 1. In Figure 1,
1 is a Josephson element, 2, 3, and 4 are silicon wiring boards, 5 is a micro connector bin (hereinafter referred to as a micro bin), and 6 is a silicon substrate having a micro connector socket (hereinafter referred to as a micro socket) 7. It is.

シリコン配線 ゛基板3と4にはプラチナ(Pt)より
なるマイクロビン5だけがはんだ付けされ、他のシリコ
ン配線基板2はそれ自身マイクロビンは有さす前記のシ
リコン基板3に垂直にはんだ付けされている。そして2
枚のシリコン配線基板3,4は、各々のマイクロビン5
をシリコン基板6のマイクロソケット7に挿着すること
によシ、相互に接続されるようになっている。
Silicon wiring ゛Only the microbins 5 made of platinum (Pt) are soldered to the substrates 3 and 4, and the other silicon wiring substrate 2 is soldered perpendicularly to the silicon substrate 3, which itself has microbins. There is. And 2
The silicon wiring boards 3 and 4 are connected to each microbin 5.
are connected to each other by inserting them into the micro sockets 7 of the silicon substrate 6.

しかし第1図のような公知のシリコン配線基板では、マ
イクロソケット7は単に、マイクロビン5だけが搭載さ
れたシリコン配線基板3゜4相互を接続する機能を果す
だけであるため、シリコン配線基板相互を密着して高密
度に積層するといった素子及び基板の三次元的実装が不
可能であった。更に、ジョセフソン素子1の付いたシリ
コン配線基板2をシリコン配線基板3に垂直に取付けて
いるため、シリコンの機械的強度の餉さが影響して機械
的及び熱的衝撃に非常に弱く、シリコン配線基板の長所
が十分引き出されていなかった。
However, in the known silicon wiring board as shown in FIG. Three-dimensional mounting of elements and substrates, such as closely stacking elements and substrates at high density, has not been possible. Furthermore, since the silicon wiring board 2 with the Josephson element 1 is attached perpendicularly to the silicon wiring board 3, silicon is extremely susceptible to mechanical and thermal shocks due to the lack of mechanical strength of silicon. The strengths of the wiring board were not fully brought out.

本発明は上記従来技術の欠点を解決し、低温デバイス素
子を高密度に積層でき、しかも電気的及び機械的特性に
優れた超高速コンピュータ用の新規なシリコン配線基板
′fc提供することを目的とする。
It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide a new silicon wiring board 'fc for ultra-high-speed computers that allows low-temperature device elements to be laminated at high density and has excellent electrical and mechanical properties. do.

この目的は同一のシリコン基板にマイクロコネクタ用ピ
ン列とソケット列とを共に備えることによって達成でき
る。この場合ビン列はPt等のマイクロビンを用いても
良く、あるいはシリコン単結晶基板上にシリコンウィス
カを成長させてこれを利用すれば超高密度のマイクロコ
ネクタが実現する。以下第2図〜第4図により本発明の
詳細な説明する。
This objective can be achieved by providing both a micro connector pin row and a socket row on the same silicon substrate. In this case, microbins made of Pt or the like may be used as the bin array, or by growing silicon whiskers on a silicon single crystal substrate and using this, an ultra-high density microconnector can be realized. The present invention will be explained in detail below with reference to FIGS. 2 to 4.

第2図は本発明の第1の実施例を示し、8は(100)
面のシリコン単結晶基板、9けptよりなるマイクロビ
ン、10は水銀が充填されたマイクロソケット、11は
冷媒流通のために設けられた穴である。マイクロビン9
及びマイクロソケット10は各々シリコン単結晶基板8
上の配線導体工2と接続されており、必要に応じてジョ
セフソン素子(図示せず)に接続される。
FIG. 2 shows the first embodiment of the present invention, where 8 is (100)
A silicon single-crystal substrate with a flat surface, a microbottle made of 9 digits, 10 a microsocket filled with mercury, and 11 a hole provided for coolant circulation. Microbin 9
and the micro socket 10 are each made of a silicon single crystal substrate 8.
It is connected to the upper wiring conductor 2, and if necessary, to a Josephson element (not shown).

なお、マイクロビン9とマイクロソケット10は低温時
水銀の固体化で接続嗜固定される。第2図の実施例は次
の方法で作製した。まず、シリコンの(100)簡単結
晶基板に公知の結晶面の選択エツチング法によシ徽細孔
列を作り、かかる2枚のシリコン基板8a、8bt−各
微細孔の中心が一致するように、低温用接着剤で向い合
せに張り合わせてマイクロソケット10を作製した。シ
リコン基板を張り合せた理由は、各シリコン基板の微細
孔は第4図の如く断面が台形になり易いため、1枚だけ
だと水銀溜めの機能を果し難いからである。次に、上記
のシリコン単結晶基板にスパッタ法によりNb にオブ
)膜を形成したのちエツチングにより所要のNb配線を
作製し、その後、マイクロソケット10の微細孔周囲及
びマイクロビンのはんだ付は予定位置にはんだとの密着
性改善のためPd (パラジウム)膜を蒸着した。しか
るのち、高さ200μm、外径150μmのPtよりな
るマイクロビン9をIn(インジウム)系合金によって
はんだ付けすることにより、本実施例のシリコン配線基
板8を得た。
The micro bottle 9 and the micro socket 10 are connected and fixed by solidification of mercury at low temperatures. The example shown in FIG. 2 was manufactured by the following method. First, a row of pores is created in a (100) simple crystal substrate of silicon by a known selective etching method for crystal planes, and the centers of the pores of the two silicon substrates 8a and 8b coincide with each other. A micro socket 10 was produced by attaching them face to face with a low-temperature adhesive. The reason why the silicon substrates were pasted together is that the fine pores in each silicon substrate tend to have a trapezoidal cross section as shown in FIG. 4, so if only one silicon substrate was used, it would be difficult to function as a mercury reservoir. Next, a Nb film is formed on the silicon single crystal substrate by sputtering, and then the required Nb wiring is formed by etching.Then, the surroundings of the microhole of the microsocket 10 and the microbin are soldered at the planned positions. A Pd (palladium) film was deposited to improve adhesion with solder. Thereafter, a micro-bin 9 made of Pt having a height of 200 μm and an outer diameter of 150 μm was soldered with an In (indium) alloy to obtain the silicon wiring board 8 of this example.

第3図は本発明の第2の実施例’cMし、3層構造とな
っている。13aと13bは(111)面のシリコン単
結晶基板、13Cは(iio)面のシリコン単結晶基板
、14は(111)面に成長させたシリコンウィスカを
利用したマイクロビン、15は低融点合金を充填したマ
イクロソケットである。第3図の実施例は次の方法で作
製した。まず、直径2インチ、板厚0.251111の
各シリコン(111)簡単結晶基板13a、13bにマ
イクロソケット用の50μmφの微細孔をエツチングに
より作9、次いでマイクロピン列の予定位置だけ残して
基板表面をSin、膜で被覆した。次にマイクロビンの
位置にA11(*)を蒸着し、VLS法で直径2Qpm
、高さ約300pmのシリコンウィスカを当該基板上に
成長させてから、炭酸ガスレーザによりシリコンウィス
カの高さを250μmに調整した。しかるのちイオンブ
レーティング法によりシリコンウィスカのピン及び当該
基板の表面にAt(アルミニウム)膜を形成し、ドライ
エツチングによって所要のAt配線を作製したのち、マ
イクロソケット用の微細孔の周囲に低融点はんだとのぬ
れ性向上のためにCr (クローム)膜これに次いでC
u    ’(銅)膜を蒸着した。一方、直径2インチ
、板厚0.25mのシリコン(110)簡単結晶基板1
3Cに前記のシリコン(111)簡単結晶基板13a。
FIG. 3 shows a second embodiment of the present invention, which has a three-layer structure. 13a and 13b are (111) plane silicon single crystal substrates, 13C is an (IIO) plane silicon single crystal substrate, 14 is a microbin using silicon whiskers grown in the (111) plane, and 15 is a low melting point alloy. It is a filled micro socket. The example shown in FIG. 3 was produced by the following method. First, a fine hole of 50 μmφ for a micro socket was made by etching9 on each silicon (111) simple crystal substrate 13a, 13b with a diameter of 2 inches and a plate thickness of 0.251111, and then only the planned position of the micro pin row was left on the substrate surface. was coated with a Sin film. Next, A11 (*) was evaporated at the position of the microbin, and the diameter was 2Qpm using the VLS method.
After growing silicon whiskers with a height of about 300 pm on the substrate, the height of the silicon whiskers was adjusted to 250 μm using a carbon dioxide laser. After that, an At (aluminum) film is formed on the silicon whisker pins and the surface of the substrate using the ion blasting method, and the required At wiring is created by dry etching, and then a low melting point solder is applied around the microhole for the micro socket. Next, a Cr (chromium) film was added to improve the wettability with C.
A u′ (copper) film was deposited. On the other hand, a silicon (110) simple crystal substrate 1 with a diameter of 2 inches and a thickness of 0.25 m
3C is the silicon (111) simple crystal substrate 13a.

13bの微細孔と中心位置が一致するように、−辺10
0μmと大きな矩形の微細孔をエツチングで作製し、か
くして得たシリコン(110)簡単結晶基板13cの両
側に前記のシリコン(111)簡単結晶基板13a、1
3bを張り付けることKより第2の実施例のシリコン配
線基板13を得た。
-side 10 so that the center position coincides with the microhole 13b.
A large rectangular micropore with a size of 0 μm is created by etching, and the silicon (111) simple crystal substrates 13a, 1 are placed on both sides of the thus obtained silicon (110) simple crystal substrate 13c.
A silicon wiring board 13 of the second embodiment was obtained by pasting 3b.

なお、第2の実施例でシリコン(111)面差板とシリ
コン(110)面差板とを使い分けした理由は次の通シ
である。第1にVLS法ではシリコン(111)面の(
111)方向のみにシリコンウィスカが成長するからで
ある。第2に、シリコン(110)面は選択エツチング
速度がシリコン結晶中で最も大きく、反対にシリコン(
111)面は最も小さいため、これらを組合せて穴径を
変えることにより簡単に低融点合金溜めを作製できるか
らである。同様な理由により (110)面のシリコン
単結晶基板の代りに(100)面のシリコン単結晶基板
全使用することができる。
The reason why the silicon (111) plane plate and the silicon (110) plane plate were used separately in the second embodiment is as follows. First, in the VLS method, the silicon (111) surface (
This is because silicon whiskers grow only in the 111) direction. Second, the silicon (110) plane has the highest selective etching rate among silicon crystals;
Since the 111) surface is the smallest, a low melting point alloy reservoir can be easily created by combining these surfaces and changing the hole diameter. For the same reason, a (100) plane silicon single crystal substrate can be used instead of a (110) plane silicon single crystal substrate.

第4図は第3の実施例を示し、2層構造である。16a
はシリコン(111)簡単結晶基板、16bはシリコン
(110)簡単結晶基板、17は(111)面に成長さ
せたシリコンウィスカを利用したマイクロビン、18は
低融点合金が充填されたマイク關ソケットである。この
実施例のシリコン配線基板16は、シリコン(110)
簡単結晶基板16bの微細孔が台形断面であること、並
びに(111)面のシリコン単結晶基板16aが(11
0’)面のシリコン単結晶基板16bの片9AKだけ接
着されていることを除き、前記第2の実施例と同一方法
で作製しである。
FIG. 4 shows a third embodiment, which has a two-layer structure. 16a
16b is a silicon (111) simple crystal substrate, 16b is a silicon (110) simple crystal substrate, 17 is a microbin using silicon whiskers grown on the (111) plane, and 18 is a microphone socket filled with a low melting point alloy. be. The silicon wiring board 16 of this embodiment is made of silicon (110).
The micropores of the simple crystal substrate 16b have a trapezoidal cross section, and the silicon single crystal substrate 16a of the (111) plane has a (11
It was manufactured in the same manner as in the second embodiment, except that only the piece 9AK of the silicon single crystal substrate 16b of the 0') plane was bonded.

以上各種の実施例をあげて説明したように、本発明のシ
リコン配線基板8,13.16は同一基板上にマイクロ
ピン列とマイクロソケット列を共に備えているから、ピ
ン列とソケット列の位置関係が逆な2種類のものを組合
せることにより、シリコン配線基板どうしを密着して簡
単に積層できることとなり、よってシリコン基板の脆さ
を克服し且つ高密度で機械的強度に優れ、低温デバイス
実装に極めて貢献することができる。なお、シリコン配
線基板を積層しても、基板中央部に穴11をあけておく
ことによシ、冷却媒体が自由に流通するから素子の冷却
効□率を何ら低下させることがない。更に、マイクロピ
ン14,17としてシリコン単結晶基板13a 。
As explained above with reference to various embodiments, the silicon wiring boards 8, 13, and 16 of the present invention have both micro pin rows and micro socket rows on the same board, so the positions of the pin rows and socket rows are By combining two types of materials with opposite relationships, it is possible to easily stack silicon wiring boards in close contact with each other, which overcomes the fragility of silicon substrates, has high density and excellent mechanical strength, and is suitable for low-temperature device mounting. can make a significant contribution to Note that even if silicon wiring boards are stacked, the cooling medium will freely flow through the holes 11 in the center of the boards, so that the cooling efficiency of the elements will not be reduced in any way. Furthermore, a silicon single crystal substrate 13a is used as micro pins 14 and 17.

13b、16aに成長させたシリコンウィスカを利用す
れば、ピンの直径をサブミクロンまで細くできるので超
高密度のマイクロコネクタが実現する。なお、シリコン
ウィスカを利用したマイクロピンはシリコン配線基板に
限らず、%ケーブル等のマイクロコネクタとしても適用
することができる。
By using the silicon whiskers grown in 13b and 16a, the diameter of the pins can be reduced to submicrons, thereby realizing an ultra-high-density microconnector. Note that micro pins using silicon whiskers can be applied not only to silicon wiring boards but also as micro connectors for cables and the like.

以上詳細に説明したように、本発明は、特に高密度実装
が要求される将来形低温デバイスを用いた超高速コンピ
ュータの超小杉化に寄与する。
As described in detail above, the present invention contributes to the miniaturization of ultra-high-speed computers using future low-temperature devices that require particularly high-density packaging.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のシリコン配線基板を用いた実装形態を示
す断面図、第2図は本発明の第1の実施例を示す斜視図
、第3図は第2の実施例を示す断面図、第4図は第3の
実施例を示す断面図である。 図 面 中、 8.13及びlljシリコン配線基板、8a及び8bt
iシリコン(100)簡単結晶基板、 13a、13b及び16aはシリコy (111)簡単
結晶基板、 13c及び16bはシリコン(110)簡単結晶基板、 9はptによるマイクロビン、 14及び17はシリコンウィスカによるマイクロピン、 10.15及び18はマイクロソケット、11は冷媒流
通用穴、 12は配線導体である。 特許出願人 日本電信電話公社 代   理   人 弁理士光石士部 (他1名) 第1図 第2図
FIG. 1 is a sectional view showing a mounting form using a conventional silicon wiring board, FIG. 2 is a perspective view showing a first embodiment of the present invention, and FIG. 3 is a sectional view showing a second embodiment. FIG. 4 is a sectional view showing the third embodiment. In the drawing, 8.13 and llj silicon wiring board, 8a and 8bt
i Silicon (100) simple crystal substrate, 13a, 13b and 16a are silicon (111) simple crystal substrates, 13c and 16b are silicon (110) simple crystal substrates, 9 is a microbin made of PT, 14 and 17 are made of silicon whiskers Micro pins, 10, 15 and 18 are micro sockets, 11 is a refrigerant flow hole, and 12 is a wiring conductor. Patent applicant Nippon Telegraph and Telephone Public Corporation representative Patent attorney Shibe Mitsuishi (and 1 other person) Figure 1 Figure 2

Claims (5)

【特許請求の範囲】[Claims] (1)  同一シリコン基板にマイクロコネクタ用ピン
列とマイクロコネクタ用微細孔列とを有し、これらピン
列と微細孔列とが夫々当該シリコン基板上の配線導体に
接続されているシリコン配線基板。
(1) A silicon wiring board that has a micro connector pin row and a micro connector microhole row on the same silicon substrate, and each of these pin rows and the microhole row is connected to a wiring conductor on the silicon substrate.
(2)上記マイクロコネクタ用ピンがシリコンの(11
1)簡単結晶基板上に成長したシリコンウィスカの表面
を導体で被覆してなるピンであることを特徴とする特許
請求の範囲第1項記載のシリコン配線基板。
(2) The above micro connector pins are made of silicone (11
1) The silicon wiring board according to claim 1, wherein the pin is formed by covering the surface of a silicon whisker grown on a simple crystal substrate with a conductor.
(3)上記シリコン基板が(111)面シリコン単結晶
の第1層基板と(110)面又は(100)面シリコン
牟結晶の第2層基板とが張り合わされてなる基板であり
、上記マイクロコネクタ用ビンは第1層基板上に成長し
たシリコンウィスカの表面を導体で被覆してなるビンで
あり、上記マイクロコネクタ用微細孔は第1層基板の微
細孔とこの微細孔よシ大径で中心が合わされた第2層基
板の微細孔とからなることを特徴とする特許請求の範囲
第1項記載のシリコン配線基板。
(3) The silicon substrate is a substrate formed by laminating a first layer substrate of a (111) plane silicon single crystal and a second layer substrate of a (110) plane or (100) plane silicon crystal, and the micro connector The vial is a vial made by covering the surface of silicon whiskers grown on the first layer substrate with a conductor. 2. The silicon wiring board according to claim 1, wherein the silicon wiring board is made up of microholes in the second layer board that are combined with each other.
(4)上記シリコン基板が(111)面シリコン単結晶
の第1層基板及び第3層基板とこれら両基板間に張シ合
わされた( 110 )面又はα00)面シリコン単結
晶の第2層基板とからなり、上記マイクロコネクタ用ビ
ン鉱第1層及び第3層基板の各々の上に成長したシリコ
ンウィスカの表面を導体で被覆してなるピンであり、上
記マイクロコネクタ用微細孔は第1層及び第3層基板の
夫々中心を合わされた微細孔とこれら微細孔よシ大径で
中心が合わされた第2層基板の微細孔とからなることを
特徴とする特許請求の範囲第1項記載のシリコン配線基
板。
(4) The silicon substrate is a first layer substrate and a third layer substrate made of a (111) plane silicon single crystal, and a second layer substrate made of a (110) plane or α00) plane silicon single crystal which is bonded between these two substrates. The pin is made by covering the surface of silicon whiskers grown on each of the first layer and third layer substrates for the micro connector with a conductor, and the micro holes for the micro connector are formed on the first layer and the third layer substrate. and a fine hole in the third layer substrate whose centers are aligned with each other, and a fine hole in the second layer substrate which has a diameter larger than these fine holes and whose centers are aligned with each other. Silicon wiring board.
(5)上記シリコン基板はそのほぼ中央に冷媒流通用の
空隙部を有することを特徴とする特許請求の範囲第1項
又は第2項又は第3項又は第4項記載のシリコン配線基
板。
(5) The silicon wiring board according to claim 1, 2, 3, or 4, wherein the silicon substrate has a gap for coolant circulation approximately in the center thereof.
JP57117024A 1982-07-07 1982-07-07 Silicon wiring substrate Pending JPS598384A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57117024A JPS598384A (en) 1982-07-07 1982-07-07 Silicon wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57117024A JPS598384A (en) 1982-07-07 1982-07-07 Silicon wiring substrate

Publications (1)

Publication Number Publication Date
JPS598384A true JPS598384A (en) 1984-01-17

Family

ID=14701550

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57117024A Pending JPS598384A (en) 1982-07-07 1982-07-07 Silicon wiring substrate

Country Status (1)

Country Link
JP (1) JPS598384A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000058204A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Narrow-pitch connector, pitch converter, micromachine, piezoelectric actuator, electrostatic actuator, ink-jet head, ink-jet printer, liquid crystal device, and electronic apparatus
WO2000058205A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink-jet head, ink-jet printer, micromachine, liquid crystal panel, and electronic apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000058204A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Narrow-pitch connector, pitch converter, micromachine, piezoelectric actuator, electrostatic actuator, ink-jet head, ink-jet printer, liquid crystal device, and electronic apparatus
WO2000058205A1 (en) * 1999-03-31 2000-10-05 Seiko Epson Corporation Narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink-jet head, ink-jet printer, micromachine, liquid crystal panel, and electronic apparatus
US6577370B1 (en) 1999-03-31 2003-06-10 Seiko Epson Corporation Narrow-pitch connector, pitch converter, micromachine, piezoelectric actuator, electrostatic actuator, ink-jet head, ink-jet printer, liquid crystal device, and electronic apparatus
US6601947B1 (en) 1999-03-31 2003-08-05 Seiko Epson Corporation Narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink-jet head, ink-jet printer, micromachine, liquid crystal panel, and electronic apparatus
CN1298612C (en) * 1999-03-31 2007-02-07 精工爱普生株式会社 Narrow-pitch connector, electrostatic actuator, piezoelectric actuator, ink-jet head, ink-jet printer, micromachine, liquid crystal panel, and electronic apparatus

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