JPS598367A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To prevent disconnection of gate lead and data lead due to a flaw caused by dust or pattern by partly correcting the wirings before the etching of pattern. CONSTITUTION:After depositing a polycrystalline silicon film 12 which becomes a gate wiring material, phosphor is thermally diffused on the principal surface of substrate which has completed the pre-treatment. Dust attached to the surface can be removed by washing etc. but dust or flaking attached before or during formation of a silicon film 12 enters the film and is perfectly fixed. In this case, such dust can no longer be removed. After the resist 6 is applied on the substrate for the gate wiring, the laser beam is selectively irradiated to the surrounding 7 of defective part 8 which has been found previously and the resist of such part is hardened. 9 is the position of expected gate lead. Thereafter, normal patterning is carried out and a gate wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix substrate comprising at least polycrystalline silicon or amorphous silicon as a main component on a transparent substrate such as soda glass, borosilicate glass, or quartz plate; This invention relates to defect correction of data lines and gate lines formed in a Ku matrix shape.

In recent years, there has been a remarkable development of computer-related equipment in the so-called information society, and along with this, flat displays have been actively developed as display devices to replace the conventional 0RTK. In particular, flat displays using liquid crystals are widely used in clock calculators, home appliances, and automobile panels due to their low power consumption, low voltage, and easy-to-read light-receiving type.

(2) Currently, a method of driving a liquid crystal using an active matrix of thin film transistors is being considered as a method that is attracting attention as an inexpensive flat display to replace the CRT.

This is a display panel for displaying images in which thin film transistor circuits for switching are formed in a matrix on a transparent substrate, and liquid crystal is sealed between this substrate and another transparent glass plate.

The structure of a conventionally reported general thin film silicon transistor is as shown in FIG.
For silicon, after forming a thin film 2 of amorphous silicon or the like, photoetching is performed to remove the remaining thin film silicon, leaving only the transistor formation area. Next, oxide@3 is formed on the front bar thin film silicon surface by thermal oxidation or OVD method, and on the oxidation preventive film 1, thin film silicon that will become the gate line is deposited (wiring is formed by photoetching. Gate line formation One approach is to directly deposit a thin film of silicon containing impurities, and a method has been devised to lower interconnect resistance by thermally diffusing impurities during the thin film deposition process.

Next, ion implantation is performed using the gate line as a mask to form a source/drain portion, and then an insulating film 4 is deposited on the main surface of the substrate.

Next, contact holes are formed by photoetching, and then metal interconnections 5 that will become data lines are formed.

As mentioned above, the manufacturing process of active matrix substrates using thin films includes many steps such as film deposition, photo-etching, and diffusion ion implantation, so that dust or flaking generated during manufacturing may cause π scratches, etc. The quality and yield of the board will be greatly affected.

Particularly in the case of a display, a disconnection of a gate line or data line caused by a front P defect is displayed as a Vc1g defect on the screen, and becomes an unusable part as a defective tunnel. In other words, how to improve panel manufacturing yieldζ
There are only two ways to do this: completely eliminate the occurrence of defects during manufacturing, or take steps to correct the wiring.

However, it is impossible to completely eliminate defects during mass production, and naturally the latter method of correction becomes more important.

The present invention provides a means for preventing disconnections of gate lines and data lines caused by dust or pattern scratches generated during manufacturing, and eliminates line defects due to disconnections, improving panel yield and reducing costs. This is something that contributes greatly to dog hearing.

Next, details of the present invention will be explained based on examples.　　.

Example-1 Panel Formation Vci- In order to form wiring, two wiring forming steps are required: forming a gate line and forming a data line, but both of them are [a step of forming an electrode film and a step of photo-etching the ME film]. Therefore, the basic Vr may conflict with the same method. Therefore, in this embodiment, detailed VC explanations will be given regarding the method of forming the gate line and the means for correcting it.

As shown in Fig. f'R2, after depositing a polycrystalline silicon film 12 as a gate bonding material on the main surface of the substrate where the previous process has been completed, phosphorus is thermally diffused.6 Debris adhering to the surface is removed by cleaning etc. Although it is possible, dust, flakes, and kings attached before or during the formation of the polycrystalline silicon film are
As shown in the figure, it has entered the membrane and is completely fixed, making it impossible to remove.

Therefore, if a kneading defect occurs on the gate line, most of the defects will lead to disconnection. So the second
As shown in the figure, after applying a resist 6 for gate wiring on the substrate, a laser beam is selectively applied to the area 7 around the defective area 8 that has been discovered in advance, as shown in Figure 3, to harden the resist at that location. urge 9 is the expected state of the gate line.

After that, regular patterning is performed to form gate wiring. Note that if adjacent wirings are short-circuited using the above method, it is easy to correct the short-circuit using a laser beam.

It goes without saying that this method can also be applied to data line correction in exactly the same manner.

Example-2 In Example-I, a method was adopted in which all defective locations were corrected in advance immediately after resist formation, but in this example, inspection was performed during gate line patterning (state patterning). This provides a means to correct only those defects that are directly caused by. As shown in Figure 4,
That is, after applying the resist again after completing the image, patterning is performed using the same means as in Example 1, avoiding only the defective areas, and then clear imaging is performed again. 10 is an initial gate line pattern, and 11 is a heat-cured resist portion. Although this method has the disadvantage of adding a photo-etched culm, it is reliable and can prevent complete I/C disconnection without affecting other lines.

As shown above, the present invention prevents wire breakage caused by dust or pattern scratches that occur during the manufacturing process by partially correcting the wiring before etching the pattern, thereby improving yield. ζ and others greatly contribute to reducing panel costs and improving image quality.

11 In the embodiment, a method of curing the resist using a laser beam was used as a method for correcting defects, but as an alternative method, the creator of Method 1' used a method of exposure using an electron beam or a method using X-rays. However, as long as defect correction is possible as a result, no matter which method is used, it does not deviate from the purpose of the present invention.

[Brief explanation of the drawing]

FIG. 1 shows the ff'f1 plane structure of a thin film silicon transistor formed on a transparent substrate using a conventional manufacturing method. FIG. 2 shows a cross-sectional structure of a thin film transistor in the manufacturing process for the purpose of implementing the present invention. FIG. 3 is a schematic plan view of a substrate in the middle of manufacturing according to the present invention. The fourth decoy is a schematic plan view of a substrate during manufacturing of the present invention. 1... Transparent substrate 2... Thin film silicon 6... Oxide film 4... Insulating film 5... Metal wiring 6... ...Resist 7...Thermoset resist portion 8...Defect portion 9...Gate line preparation position 10...Gate line 11...・Thermoset resist 12...Polycrystalline silicon film or more Applicant: Suwa Seikosha Co., Ltd.

Claims (1)

[Claims] 1. An active matrix substrate comprising a matrix of data lines and gate lines, wherein some of the data lines and gate lines are formed avoiding defective areas on the main surface of the substrate.