JPS598349A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPS598349A
JPS598349A JP11752182A JP11752182A JPS598349A JP S598349 A JPS598349 A JP S598349A JP 11752182 A JP11752182 A JP 11752182A JP 11752182 A JP11752182 A JP 11752182A JP S598349 A JPS598349 A JP S598349A
Authority
JP
Japan
Prior art keywords
film
silicon nitride
nitride film
silicon
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11752182A
Other languages
Japanese (ja)
Inventor
Kuniyuki Hamano
浜野 邦幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11752182A priority Critical patent/JPS598349A/en
Publication of JPS598349A publication Critical patent/JPS598349A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To realize element isolation without bird beak by leaving a second silicon nitride film under the penthouse consisting of a first silicon nitride film and then oxidating it. CONSTITUTION:An SiO2 film 202 and an Si3N4 film 203 are formed on an Si substrate 201 and a window is opened thereon. At this time, a penthouse part is formed on the Si3N4 film by over-etching the SiO2 film 202. A second Si3N4 film 204 is formed on the entire surface of substrate by the plasma vapor growth method. Thereafter, a part 205 of the second Si3N4 film is left only at the area under the penthouse part of the first Si3N4 film 203 by etching the entire part of second Si3N4 film through the etching method having directivity. Then, a field oxide film 206 is formed under the ordinary steam ambient. Thereby, generation of bird beak can be prevented.

Description

【発明の詳細な説明】 本発明eよ半導体装置の製造方法Vこ関し特に半導体基
板内の集子間全分離する所論素子間分離法に関する〇 集積回路装置に於いては、半導体基板内に組み込まれ友
能動素子間全電気的に独立に保つために素子間に分離領
域を設ける必敦がある。例えばシリコン基板を用いたM
OS型集積回路装Wに於いては約1μの厚さのシリコン
酸化膜を能動素子間に設けておく事で、素子間分離を達
成している〇従来、この厚いシリコン酸化11!j!に
素子間に選択的に形成する為にはシリコン基板上VC選
択的にシリコン窒化膜を残し、そのシリコン窒化膜をマ
スクとしてシリコン基板全酸化し素子間に厚いがr開フ
ィールド酸化膜を形成していた。この際、厚いフィール
ド酸化膜を形成するためには1000°C前後の高温度
で長時間の熱酸化が必要とされるためシリコン窒化膜を
シリコン基板上に直接被着してしまうとシリコンとシリ
コン窒化膜の熱膨張係数の違い等に起因してシリコン基
板内に歪が入り、後で形成される素子の特性を劣化させ
る。この現象ヲ避けるために一般的にシリコン基板とシ
リコン窒化膜の間に数百へ〜1000A程の薄いシリコ
ン酸化膜を介在させて歪を緩和させる方法がとられる。
DETAILED DESCRIPTION OF THE INVENTION The present invention e relates to a method of manufacturing a semiconductor device, and in particular relates to an element isolation method for completely isolating the elements in a semiconductor substrate. In order to keep all the active elements electrically independent, it is necessary to provide isolation regions between the elements. For example, M using a silicon substrate
In the OS type integrated circuit device W, isolation between the active elements is achieved by providing a silicon oxide film with a thickness of about 1μ between the active elements. Conventionally, this thick silicon oxide film 11! j! In order to selectively form VC between elements, a silicon nitride film is selectively left on the silicon substrate, and the silicon nitride film is used as a mask to completely oxidize the silicon substrate, forming a thick but open field oxide film between the elements. was. At this time, in order to form a thick field oxide film, thermal oxidation is required at a high temperature of around 1000°C for a long time, so if the silicon nitride film is directly deposited on the silicon substrate, the silicon Due to differences in thermal expansion coefficients of the nitride films, strain is introduced into the silicon substrate, deteriorating the characteristics of elements to be formed later. In order to avoid this phenomenon, a method is generally used in which a thin silicon oxide film of several hundred to 1000 Å is interposed between the silicon substrate and the silicon nitride film to alleviate the strain.

この方法に於いては確かに熱酸化時の歪を少くし・素子
特性の劣化を檎く少くする蓼が可能であるが他方、熱酸
化時に酸化因子である酸素や水酸基が、介在させた薄い
シリコン酸化膜中を拡散してゆき、垢子間分離のフィー
ルド酸化膜のエッヂがシリコン窒化膜の下側に入り込む
所謂バーズビークの問題が生じる。このバーズビークが
発生するとその巾だけフィールド歌化膜の巾が広くなり
、素子を形成する領域が狭くなシ集#1度の向上の大き
な障害となっていた。
This method certainly makes it possible to reduce distortion during thermal oxidation and to minimize the deterioration of device characteristics. As the particles diffuse through the silicon oxide film, a so-called bird's beak problem arises in which the edge of the field oxide film for isolation between particles gets under the silicon nitride film. When this bird's beak occurs, the width of the field conversion film becomes wider by the width thereof, which has been a major obstacle to improving the #1 degree in which the area in which the element is formed is narrow.

従来このバーズビークの発生を抑える為に、一度薄いシ
リコン酸化膜シリコン窒化膜を選択的に形成し之故に全
面にわたりシリコン窒化膜を形成し、更にリアクティブ
イオンエツチング等で指向性のあるドライエッチ法で全
面エッチを行い、最初に形成されていた薄いシリコン酸
化膜とシリコン窒化膜の端の部分にIsいては新しく形
成さ九たシリコン窒化膜段差の為1′i:厚くなシ至面
エッチ時に残り、この残ったシリコン窒化膜によりバー
ズビークの発生を抑うようという方法がある。
Conventionally, in order to suppress the occurrence of bird's beaks, a thin silicon oxide film or silicon nitride film was first selectively formed, and therefore a silicon nitride film was formed over the entire surface, and then a directional dry etching method such as reactive ion etching was used. The entire surface is etched, and at the end of the thin silicon oxide film and silicon nitride film that were originally formed, there is a newly formed silicon nitride film step. There is a method of suppressing the occurrence of bird's beak using this remaining silicon nitride film.

しかしながらこの従来の方法では、全面エッチ的の条件
設定が非常に難しく再現性よくバーズビークを抑えるの
が非常VC難しいという困難がありtn 従って、本発明の目的は上記の問題点を除去したバーズ
ビークの発生のない素子間分離方法を提供する事である
However, in this conventional method, it is very difficult to set the conditions for etching the entire surface, and it is extremely difficult to suppress bird's beak with good reproducibility.Therefore, the object of the present invention is to eliminate the above-mentioned problems in the generation of bird's beak. The object of the present invention is to provide a method for isolating elements without any problems.

本発明は選択的に形成される薄いシリコン酸化膜とシリ
コン窒化膜に於いてシリコン窒化膜をひさし状態に下側
の薄いシリコン酸化膜より外部に張り出たぜ、次に成長
されるシリコン窒化膜をプラズマ気相成長や減圧気相成
長で行う事により、選択的に形成されたシリコン窒化膜
のひさしの下側に再現性より第2のシリコン窒化膜を残
す事が可能となるという知見に基〈。        
      1本発明の方法によれば、第2のシリコン
窒化膜は%第1のシリコン窒化膜のひさしの下にもぐり
込ンだ第2のシリコン窒化膜は全面シリコン窒化膜工、
チング時にオーバーエッチされても肌1のシリコン窒化
膜の下側に入り込んでいるために確実に残り再現性よく
、選択的に形成された薄いシリコン酸化膜及び第1のシ
リコン窒化膜の端に形成されるので、バーズビークの発
生も再現性よく抑えられるという大きな利点が生じる。
In the present invention, in the thin silicon oxide film and silicon nitride film that are selectively formed, the silicon nitride film extends outward from the lower thin silicon oxide film in a canopy state, and the next silicon nitride film is grown. Based on the knowledge that by performing plasma vapor phase epitaxy or low pressure vapor phase epitaxy, it is possible to reproducibly leave a second silicon nitride film under the eaves of the selectively formed silicon nitride film. <.
1. According to the method of the present invention, the second silicon nitride film crawls under the eaves of the first silicon nitride film.
Even if over-etched during etching, the thin silicon oxide film and the edge of the first silicon nitride film are formed selectively, remaining reliably because they penetrate under the silicon nitride film of skin 1 and with good reproducibility. Therefore, there is a great advantage that the occurrence of bird's beak can be suppressed with good reproducibility.

次に本発明をよりよく理屏するために図面を用いて説明
しよう゛。
Next, in order to better understand the present invention, the present invention will be explained using drawings.

第1図(a) 、 (b)は従来の選択酸化法と呼ばれ
る素子間分離法を説明する為の断面図である◎先づ第1
1図(a)VC示される様にシリコン基板101上に薄
いシリコン酸化膜102とシリコン窒化膜101形成す
る。次に第1図(b)に示す如く、該シリコン酸化膜1
01、シリコン窒化膜102’にマスクとしてシリコン
基板を1000℃前後の高温で、通常はスチーム窒囲気
中に於いて長時間酸化し大 1μのフィールドシリコン
酸化膜101形成する0この従来の方法に於いてはフィ
ールド酸化膜104の酸化因子である水酸築や酸素がシ
リコン酸化膜102とシリコン窒化膜103の端IW1
05からシリコン酸化膜102の内部に横方向に拡散す
るために、フィールド酸化膜104は前記シリコン酸化
膜102、シリコン窒化膜103の端105から横方向
にり、だけ拡がりこの分だけシリコン窒化膜103で被
われた部分のl槓が小さくなり、素子はこのシリコン窒
化膜103Vc被われた部分に形成されるから結果的に
集積度が向上しなくなるという大きな問題が生じ、特に
この問題は集積回路の設はルールが微細ICなるに従い
非常に重要な問題となって米た。
Figures 1(a) and 1(b) are cross-sectional views for explaining a conventional device isolation method called selective oxidation method.
As shown in FIG. 1(a) VC, a thin silicon oxide film 102 and a silicon nitride film 101 are formed on a silicon substrate 101. Next, as shown in FIG. 1(b), the silicon oxide film 1
01. Using the silicon nitride film 102' as a mask, the silicon substrate is oxidized for a long time at a high temperature of around 1000° C., usually in a steam nitrogen atmosphere, to form a field silicon oxide film 101 with a thickness of 1 μm.0 In this conventional method, In this case, hydroxide and oxygen, which are oxidizing factors of the field oxide film 104, cause the edge IW1 of the silicon oxide film 102 and the silicon nitride film 103 to
05 into the silicon oxide film 102, the field oxide film 104 spreads laterally from the edge 105 of the silicon oxide film 102 and the silicon nitride film 103, and the field oxide film 104 spreads by this amount into the silicon nitride film 103. A big problem arises in that the area covered by the silicon nitride film 103Vc becomes smaller and the element is formed in the area covered by the silicon nitride film 103Vc, resulting in no improvement in the degree of integration. As the rules for setting up ICs become more and more minute, it has become an extremely important issue.

第2図(a)〜(d)は本発明の素子間分離法を説明す
るための断面図である。先づ第2図(a)に示す如く、
シリコン基板201の上に選択的に薄いシリコン酸化膜
202及び第1のシリコン窒化膜203tl−形成する
。この際シリコン酸化膜202は、シリコン窒化膜20
3をマスクとしてエツチング除去するがこのシリコン酸
化膜202を少しオーバーエッチする事により、シリコ
ン窒化膜203の端はシリコン酸化膜202の端を後退
させてシリコン窒化膜203全オーバーハングにする。
FIGS. 2(a) to 2(d) are cross-sectional views for explaining the device isolation method of the present invention. First, as shown in Figure 2(a),
A thin silicon oxide film 202 and a first silicon nitride film 203tl- are selectively formed on a silicon substrate 201. At this time, the silicon oxide film 202 is replaced by the silicon nitride film 20.
3 as a mask, and by slightly over-etching the silicon oxide film 202, the edge of the silicon nitride film 203 is set back so that the entire silicon nitride film 203 overhangs.

典型的にはシリコン酸化膜202が100OA、  シ
リコン輩1ヒ膜203力i15UUAとすると、このオ
ーバーハングの部分の長さは0.2μ前後でよい。この
0.2μの加工性は弗酸を含むエッチング液によるシリ
コン敵化膜のエッチがよく知られた技術であり、拘現注
のよいものでるる。
Typically, if the silicon oxide film 202 is 100 OA and the silicon oxide film 203 is 15 UUA, the length of this overhang portion may be around 0.2 μ. This 0.2 μm workability is achieved by etching a silicone film using an etching solution containing hydrofluoric acid, which is a well-known technique, and is a result of good precision.

しかる後に、第2図(b)K示すようにプラズマ気相成
長、もしくU減圧気相成長法によって、シリコン基板全
面に第2のシリコン窒化膜204を形成する。この第2
のシリコン窒化膜204は減圧気相は成長かもしくはプ
ラズマ気相成長で行うと、第1のシリコン窒化膜の下側
にもよくまわり込む。欠Vc第2図(c)K示す如く、
リアクティブイオンエッチ等の指向性をもったエツチン
グ方法で第2のシリコン窒化膜204を全面エッチする
と、飛来するエツチングガスにさらされる頭載のW、2
のシリコン窒化膜204がエツチング除去される櫟な条
件に設定すると、第1のシリコン窒化膜203のオーバ
ーハングの下の部分のみに第2のシリコン窒化膜204
の一部205が残される口この第のシリコン磁化膜20
4の下のみIc第2のシリコン窒化膜の一部205を残
す事はこの部分は第1のシリコン窒化膜204がエツチ
ングのマスクとなっているので非常に容易に行え、第2
のシリコン窒化膜204のうち不用は部分のみをエツチ
ングするのに充分な酌量をかけても安定に再現性よくシ
リコン窒化膜205は残される。その後第2図の(d)
の様に1000℃前後の温度で通常スチーム雰囲気中に
於いて1μ程度の厚さのフィールド酸化膜206に形成
する。この時、フィールド酸化膜206と薄いシリコン
酸化M2O2の間には第2のシリコン窒化膜の一部20
5が存在しているため、上記フィールド酸化膜206形
成の為の酸化中に酸化因子はシリコン酸化膜202中に
拡散してゆかず従って、フィールド酸化膜206は端は
シリコン窒化膜205で止まり、バーズビークは殆んど
生じない。
Thereafter, as shown in FIG. 2(b)K, a second silicon nitride film 204 is formed on the entire surface of the silicon substrate by plasma vapor deposition or U reduced pressure vapor deposition. This second
When the silicon nitride film 204 is grown by low-pressure vapor phase growth or plasma vapor phase growth, it wraps well under the first silicon nitride film. As shown in Figure 2 (c) K,
When the entire surface of the second silicon nitride film 204 is etched using a directional etching method such as reactive ion etching, the overhead W, 2 exposed to the flying etching gas is etched.
When conditions are set such that the silicon nitride film 204 is etched away, the second silicon nitride film 204 is etched only under the overhang of the first silicon nitride film 203.
A portion 205 of the first silicon magnetized film 20 is left behind.
It is very easy to leave a part 205 of the second silicon nitride film under 4 because the first silicon nitride film 204 serves as an etching mask.
Even if sufficient consideration is given to etching only the unnecessary portion of the silicon nitride film 204, the silicon nitride film 205 is left stably and with good reproducibility. Then (d) in Figure 2
A field oxide film 206 having a thickness of about 1 μm is formed at a temperature of about 1000° C. in a normal steam atmosphere. At this time, a portion 20 of the second silicon nitride film is placed between the field oxide film 206 and the thin silicon oxide M2O2.
5 exists, the oxidizing factor does not diffuse into the silicon oxide film 202 during the oxidation for forming the field oxide film 206, and therefore the field oxide film 206 stops at the silicon nitride film 205 at the end. Bird's beak rarely occurs.

不発明の素子間分離法に依ればバーズビークが殆んど生
じない為に集積度の大巾な向上が図れるという利点があ
る。更に本発明の方法によれば、シリコン窒化膜205
Vi、シリコン窒化膜203のひさし部分に入り込んで
いる之め、リアクティブエツチング法等の方向性のめる
エツチング法でシリコン窒化膜204を全面エッチする
場合に多少のオーバーエッチをしても再現性よく残シ、
試料間のバラツキが非常に少いという大きな利点も併せ
もつものである。
The uninvented element isolation method has the advantage that the degree of integration can be greatly improved because bird's beak hardly occurs. Furthermore, according to the method of the present invention, the silicon nitride film 205
Since Vi has entered the eaves of the silicon nitride film 203, even if the silicon nitride film 204 is etched over the entire surface using a directional etching method such as a reactive etching method, it will not remain with good reproducibility. C,
It also has the great advantage of very little variation between samples.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a) 、 (b)は従来の半導体装置の製造方
法を工程順に説明するための断面図、第2図(a)〜(
よ)は本発明の半導体装置、製造法を説明するための断
面図、である。 尚、図に於いて、101.201・・・・・・シリコン
基板、102,104,202,206・・・・・・酸
化膜、103.203,204,205はシリコン窒化
膜、105はシリコン窒化膜の端部、である。 (3) 〜 /θ5 (α) キー 図
FIGS. 1(a) and 1(b) are cross-sectional views for explaining a conventional semiconductor device manufacturing method step by step, and FIGS.
1) is a cross-sectional view for explaining the semiconductor device and manufacturing method of the present invention. In the figure, 101.201... silicon substrate, 102, 104, 202, 206... oxide film, 103.203, 204, 205 silicon nitride film, 105 silicon This is the edge of the nitride film. (3) ~ /θ5 (α) Key diagram

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上にシリコン酸化膜全形成する工程と、該
シリコン酸化膜上1c第1のシリコン窒化膜を形成する
工程と、該第1のシリコン窒化膜と該シリコン酸化風と
を同じパターンとなる庫にエツチングする工程と、更に
該シリコン酸化膜をオーバーにエツチングする工程と、
次に第2のシリコン窒化膜を成長する工程と、方向性の
あるエツチング法により該第2のシリコン窒化膜を全面
エツチングする工程と、該エツチング工程後に熱酸化に
よって選択的にシリコン基板を酸化する工程と?含む事
を特徴と゛する半導体装置の製造方法0
A step of forming the entire silicon oxide film on the silicon substrate, a step of forming a first silicon nitride film on the silicon oxide film, and a step of forming the first silicon nitride film and the silicon oxide film in the same pattern. a step of etching the silicon oxide film overly;
Next, a step of growing a second silicon nitride film, a step of etching the entire second silicon nitride film by a directional etching method, and selectively oxidizing the silicon substrate by thermal oxidation after the etching step. With the process? Method 0 of manufacturing a semiconductor device characterized by including
JP11752182A 1982-07-06 1982-07-06 Fabrication of semiconductor device Pending JPS598349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11752182A JPS598349A (en) 1982-07-06 1982-07-06 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11752182A JPS598349A (en) 1982-07-06 1982-07-06 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPS598349A true JPS598349A (en) 1984-01-17

Family

ID=14713827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11752182A Pending JPS598349A (en) 1982-07-06 1982-07-06 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPS598349A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6415946A (en) * 1987-07-10 1989-01-19 Hitachi Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6415946A (en) * 1987-07-10 1989-01-19 Hitachi Ltd Manufacture of semiconductor device

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