JPS5981139U - Receiving machine - Google Patents

Receiving machine

Info

Publication number
JPS5981139U
JPS5981139U JP17585782U JP17585782U JPS5981139U JP S5981139 U JPS5981139 U JP S5981139U JP 17585782 U JP17585782 U JP 17585782U JP 17585782 U JP17585782 U JP 17585782U JP S5981139 U JPS5981139 U JP S5981139U
Authority
JP
Japan
Prior art keywords
frequency
fine adjustment
division ratio
frequency division
display section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17585782U
Other languages
Japanese (ja)
Inventor
福場 俊弘
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP17585782U priority Critical patent/JPS5981139U/en
Publication of JPS5981139U publication Critical patent/JPS5981139U/en
Pending legal-status Critical Current

Links

Landscapes

  • Circuits Of Receivers In General (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は、この考案の受信機の1実施例のフロック結線区
である。 7・・・PLLシンセサイザ回路、8・・・制御部、8
′・・・微調端子、11・・・副表示部、12・・・第
1スイツチ。
The drawing shows a flock connection section of one embodiment of the receiver of this invention. 7... PLL synthesizer circuit, 8... Control section, 8
'...Fine adjustment terminal, 11...Sub display section, 12...First switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] PLLシンセサイザ回路により、該回路の分周器の基本
分周比に基つく放送周波数を同調受信し、前記シンセサ
イサ回路から出力により主表示部に受信周波数を表示す
る受信機において、微調端子への微調指令信号の入力に
より前記分周器の分周比を前記基本分周比から所定の微
小量たけ変化させる制御部と、前記微調指令信号を出力
する指令手段と、前記分周比の変化量に基つく受信周波
数の変動量を表示する副表示部とを設けた受信機。
In a receiver in which a PLL synthesizer circuit tunes and receives a broadcast frequency based on a basic frequency division ratio of a frequency divider of the circuit, and the received frequency is displayed on a main display section by output from the synthesizer circuit, fine adjustment to a fine adjustment terminal is provided. a control unit that changes the frequency division ratio of the frequency divider by a predetermined minute amount from the basic frequency division ratio by inputting a command signal; a command means that outputs the fine adjustment command signal; A receiver equipped with a sub-display section that displays the amount of variation in the received frequency.
JP17585782U 1982-11-20 1982-11-20 Receiving machine Pending JPS5981139U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17585782U JPS5981139U (en) 1982-11-20 1982-11-20 Receiving machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17585782U JPS5981139U (en) 1982-11-20 1982-11-20 Receiving machine

Publications (1)

Publication Number Publication Date
JPS5981139U true JPS5981139U (en) 1984-06-01

Family

ID=30382481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17585782U Pending JPS5981139U (en) 1982-11-20 1982-11-20 Receiving machine

Country Status (1)

Country Link
JP (1) JPS5981139U (en)

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