JPS5981042U - 試験用パツドを有する半導体集積回路装置 - Google Patents
試験用パツドを有する半導体集積回路装置Info
- Publication number
- JPS5981042U JPS5981042U JP1982176801U JP17680182U JPS5981042U JP S5981042 U JPS5981042 U JP S5981042U JP 1982176801 U JP1982176801 U JP 1982176801U JP 17680182 U JP17680182 U JP 17680182U JP S5981042 U JPS5981042 U JP S5981042U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- circuit device
- test pad
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図は本考案の一実施例の斜視図、第2図は第1図の
X−Xの断面図、である。 なお図において、1・・・・・・パッケージ、2・・・
・・・半導体集積回路チップ、3・・・・・・チップパ
ッド、4・・・・・・ホンディングワイヤ、5・・・・
・・パンケージパッド、6・・・・・・パッケージパタ
ーン、7・・・・・・試験専用パッド、8・・・・・・
パッケージ端子。
X−Xの断面図、である。 なお図において、1・・・・・・パッケージ、2・・・
・・・半導体集積回路チップ、3・・・・・・チップパ
ッド、4・・・・・・ホンディングワイヤ、5・・・・
・・パンケージパッド、6・・・・・・パッケージパタ
ーン、7・・・・・・試験専用パッド、8・・・・・・
パッケージ端子。
Claims (1)
- プリント基板と接続するプリント基板接続用端子と該プ
リント基板と接続しない少くとも2個以上の試験用バン
ドを有することを特徴とする半導体集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982176801U JPS5981042U (ja) | 1982-11-22 | 1982-11-22 | 試験用パツドを有する半導体集積回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1982176801U JPS5981042U (ja) | 1982-11-22 | 1982-11-22 | 試験用パツドを有する半導体集積回路装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5981042U true JPS5981042U (ja) | 1984-05-31 |
Family
ID=30384287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1982176801U Pending JPS5981042U (ja) | 1982-11-22 | 1982-11-22 | 試験用パツドを有する半導体集積回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5981042U (ja) |
-
1982
- 1982-11-22 JP JP1982176801U patent/JPS5981042U/ja active Pending
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