JPS5981042U - 試験用パツドを有する半導体集積回路装置 - Google Patents

試験用パツドを有する半導体集積回路装置

Info

Publication number
JPS5981042U
JPS5981042U JP1982176801U JP17680182U JPS5981042U JP S5981042 U JPS5981042 U JP S5981042U JP 1982176801 U JP1982176801 U JP 1982176801U JP 17680182 U JP17680182 U JP 17680182U JP S5981042 U JPS5981042 U JP S5981042U
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
circuit device
test pad
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982176801U
Other languages
English (en)
Inventor
原田　健三
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1982176801U priority Critical patent/JPS5981042U/ja
Publication of JPS5981042U publication Critical patent/JPS5981042U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の一実施例の斜視図、第２図は第１図の
Ｘ−Ｘの断面図、である。 なお図において、１・・・・・・パッケージ、２・・・
・・・半導体集積回路チップ、３・・・・・・チップパ
ッド、４・・・・・・ホンディングワイヤ、５・・・・
・・パンケージパッド、６・・・・・・パッケージパタ
ーン、７・・・・・・試験専用パッド、８・・・・・・
パッケージ端子。

Claims (1)

    【実用新案登録請求の範囲】
  1. プリント基板と接続するプリント基板接続用端子と該プ
    リント基板と接続しない少くとも２個以上の試験用バン
    ドを有することを特徴とする半導体集積回路装置。
JP1982176801U 1982-11-22 1982-11-22 試験用パツドを有する半導体集積回路装置 Pending JPS5981042U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982176801U JPS5981042U (ja) 1982-11-22 1982-11-22 試験用パツドを有する半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982176801U JPS5981042U (ja) 1982-11-22 1982-11-22 試験用パツドを有する半導体集積回路装置

Publications (1)

Publication Number Publication Date
JPS5981042U true JPS5981042U (ja) 1984-05-31

Family

ID=30384287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982176801U Pending JPS5981042U (ja) 1982-11-22 1982-11-22 試験用パツドを有する半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS5981042U (ja)

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