JPS5980024A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS5980024A
JPS5980024A JP57191103A JP19110382A JPS5980024A JP S5980024 A JPS5980024 A JP S5980024A JP 57191103 A JP57191103 A JP 57191103A JP 19110382 A JP19110382 A JP 19110382A JP S5980024 A JPS5980024 A JP S5980024A
Authority
JP
Japan
Prior art keywords
impedance
circuit
signal
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57191103A
Other languages
Japanese (ja)
Inventor
Toshio Tabata
敏雄 田畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP57191103A priority Critical patent/JPS5980024A/en
Publication of JPS5980024A publication Critical patent/JPS5980024A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/601Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors using transformer coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To transmit simply an output with high efficiency, by providing switch elements which can be switched alternately at the coil end of the input side and obtaining an impedance matched output signal. CONSTITUTION:When an L-level signal is supplied from a logical circuit 2, a transistor TRTr2 and a TRTr3 are turned on and off respectively. In this case, a current i1 flows and the impedance Z1 of a signal source is also set equal to the impedance Z0 of an input circuit of a transformer T when viwed from the load side. Thus the impedance matching is secured. While, the TRTr2 and TRTr3 are turned off and on respectively when an H-level signal is supplied from the side of the circuit 2. Under such conditions, a current i2 flows and the impedance Z2 of the signal source is set equal to Z0 when viwed from the load side. Thus the impedance matching is ensured.

Description

【発明の詳細な説明】 本発明は、信号出力回路におけるインターフェース回路
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface circuit in a signal output circuit.

通常のスイッチング動作によりロジック回路からの信号
で出力・信号を出すインターフニー2回路は、第1図に
みられるような構成になっている。
The Interfuni 2 circuit, which outputs and outputs signals from the logic circuit through normal switching operations, has a configuration as shown in FIG.

すなわち、トランジスタTrtに対してベース電圧が加
わらない時にはくこ回路では、インバータIV1に1ル
ーベル信号が加わった状態の時)、出力インピーダンス
は7oで、電流 ioが出力信号として与えられるが、
トランジスタTrtに対してベース電圧が加わる時には
(この回路では、インバータIV1にLレベル信号が加
わった状態の時)、出力インピーダンスは、はぼ0Ωと
なり、次段の制御系との間にインピーダンスの不整合が
生じる。
That is, in the Kuko circuit when no base voltage is applied to the transistor Trt (when a 1 rubel signal is applied to the inverter IV1), the output impedance is 7o and the current io is given as an output signal.
When the base voltage is applied to the transistor Trt (in this circuit, when an L level signal is applied to the inverter IV1), the output impedance becomes approximately 0Ω, and there is no impedance difference between it and the next stage control system. Alignment occurs.

一方、ロジック回路の出力信号を伝迄線路に接続する場
合や、出力信号中の特定の周波数成分のみを取り出すた
めにフィルタを接続する場合、インターフェース回路で
インピーダンス不整合が生じるのは具合が悪いし、別に
複雑な回路構成を必要とする。
On the other hand, when connecting the output signal of a logic circuit to a transmission line, or when connecting a filter to extract only a specific frequency component from the output signal, it is inconvenient for impedance mismatch to occur in the interface circuit. , which requires a particularly complex circuit configuration.

本発明は、上記事情にもとづいてなされたもので、スイ
ッチング回路の出力を、所定のインピーダンス特性を有
する回路に接続する場合、そのインピーダンス回路を、
比較的簡単な構成で提供とようとするものである。
The present invention was made based on the above circumstances, and when the output of a switching circuit is connected to a circuit having a predetermined impedance characteristic, the impedance circuit is
It is intended to be provided with a relatively simple configuration.

この目的のため、本発明は、トランスの入[]側コイル
に中間タップを設けて所定のインピーダンス特性を有す
る入力回路を接続すると共に、上記入力側コイル端にそ
れぞれ交互切換えされるスイッチ素子を設けて、インピ
ーダンス整合させつつ出力(5号を与えるJζうにして
いる。
For this purpose, the present invention provides an intermediate tap on the input coil of the transformer to connect an input circuit having a predetermined impedance characteristic, and also provides switch elements that are alternately switched at the ends of the input coil. Then, the output (Jζ giving No. 5) is made while matching the impedance.

以上、本発明の一実施例を第2図ないし第4図を参照し
て具体的に説明する。ここでは、トランス1の入力側コ
イルC1に中間タップtを設(プ、これには所定のイン
ピーダンスZOを有する入力回路1が接続しである。ま
た、上記入力側コイルC1の端に(,1、それぞれ交互
切換えされるスイツヂ水子、例えば1ヘランジスタTr
z、Tr3が接続してあり、ロジック回路2からの信号
は、インバータIV2 、IVs、IV4によって反転
されて、上記トランジスタ下r2+ 王1゛3に対して
1@レレベ信号を交代的に与えるようになっている。
An embodiment of the present invention will now be described in detail with reference to FIGS. 2 to 4. Here, an intermediate tap t is provided on the input side coil C1 of the transformer 1, to which the input circuit 1 having a predetermined impedance ZO is connected. , respectively switched alternately, e.g. 1 helangister Tr.
The signals from the logic circuit 2 are inverted by the inverters IV2, IVs, and IV4, so that a 1 level signal is alternately given to the transistors 1 and 3. It has become.

また、トランス゛「の出力側コイルC2には負荷が接続
される。
Further, a load is connected to the output side coil C2 of the transformer.

なお上記トランスTは、この実施例では1:1のI!I
!想1〜ランスとして考える。
In this embodiment, the transformer T has a 1:1 ratio of I! I
! Thought 1: Think as Lance.

このような構成では、ロジック回路2からLレベル信号
が入力される時、トランジスタTrzはオン状態に、ト
ランジスタTrsはオフ状態となる。この時には、第3
図のように、電流11が流れ、負荷側からみた信号源の
インピーダンス71も7oになり、インピーダンス整合
が取れる。
In such a configuration, when an L level signal is input from the logic circuit 2, the transistor Trz is turned on and the transistor Trs is turned off. At this time, the third
As shown in the figure, a current 11 flows, and the impedance 71 of the signal source seen from the load side also becomes 7o, achieving impedance matching.

一方、ロジック回路2から1」レベル信号が入力される
時、トランジスタTrzはオフ状態に、トランジスタT
r3はオン状態となる。この時には、第4図のように、
電流 12が流れ、負荷側からみた信号源のインピーダ
ンス7tGZoにイ【す、インピーダンス整合が取れる
On the other hand, when a 1'' level signal is input from the logic circuit 2, the transistor Trz is turned off, and the transistor T
r3 is turned on. At this time, as shown in Figure 4,
A current 12 flows, and impedance matching is achieved by matching the impedance 7tGZo of the signal source as seen from the load side.

このように、本発明によれば、スイッチグ動作を行なう
ロジック回路からの出力信号で制御されるインターフェ
ース回路において、所定のインピーダンス特性を有する
回路に対してインピーダンス整合させつつ出力信号を得
ることができ、出力を高効率で伝達でき、その構成も簡
単であり、ぞの結果、ロジック回路出力信号を伝送線路
に接続する時や、出力信号中の特定周波数成分のみを取
り出すためにフィルタを接続する時、非常に有効な手段
となる。
As described above, according to the present invention, in an interface circuit controlled by an output signal from a logic circuit that performs a switching operation, it is possible to obtain an output signal while matching the impedance to a circuit having a predetermined impedance characteristic. The output can be transmitted with high efficiency, and its configuration is simple.As a result, when connecting a logic circuit output signal to a transmission line, or when connecting a filter to extract only a specific frequency component from an output signal, This is a very effective tool.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のインターフェース回路の一例を示づ回路
図、第2図は本発明の一実施例を示す回路図、第3図お
よび第4図は作動状況を説明するための回路部分図であ
る。 1−・・・トランス、 C1・・・−次側コイル、 C2・・・二次側コイル、 Zo・・・インピーダンス、 1・・・入力回路、 Tr’2 、Tr s・・・トランジスタ、IVz 、
IVs *  IV4 ”・インバータ、2・・・ロジ
ック回路。 特許出願人    パイオニア株式会社代理人 弁理士
  小 橋 信 浮
Fig. 1 is a circuit diagram showing an example of a conventional interface circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 and 4 are partial circuit diagrams for explaining operating conditions. be. 1-...Transformer, C1...-Next coil, C2...Secondary side coil, Zo...Impedance, 1...Input circuit, Tr'2, Tr s...Transistor, IVz ,
IVs * IV4 ”・Inverter, 2...Logic circuit. Patent applicant Nobuuki Kobashi, agent of Pioneer Corporation, patent attorney

Claims (1)

【特許請求の範囲】[Claims] 1ヘランスの入口側コイルに中間タップを設けて所定の
インピーダンス特性を有ザる入力回路を接続づると共に
、上記入力側コイル端にそれぞれ交互切換えされるスイ
ッチ素子を設けたことを特徴とするインターフェース回
路。
1. An interface circuit characterized in that an intermediate tap is provided on the inlet side coil of the Herance to connect an input circuit having a predetermined impedance characteristic, and switch elements that are alternately switched are provided at the ends of the input side coils. .
JP57191103A 1982-10-30 1982-10-30 Interface circuit Pending JPS5980024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57191103A JPS5980024A (en) 1982-10-30 1982-10-30 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57191103A JPS5980024A (en) 1982-10-30 1982-10-30 Interface circuit

Publications (1)

Publication Number Publication Date
JPS5980024A true JPS5980024A (en) 1984-05-09

Family

ID=16268901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57191103A Pending JPS5980024A (en) 1982-10-30 1982-10-30 Interface circuit

Country Status (1)

Country Link
JP (1) JPS5980024A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0263212A (en) * 1988-05-24 1990-03-02 Nec Corp Line driver circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246655B2 (en) * 1972-11-29 1977-11-26
JPS538859B2 (en) * 1974-09-27 1978-04-01

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246655B2 (en) * 1972-11-29 1977-11-26
JPS538859B2 (en) * 1974-09-27 1978-04-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0263212A (en) * 1988-05-24 1990-03-02 Nec Corp Line driver circuit

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