JPS597985B2 - Access control method for data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an access control method for a data processing device, particularly a data processing system including a microprocessor unit, which expands the address space that can be accessed using Matsupa, and also provides a system for controlling the access to the expanded address space. The hardware fixed area is enlarged and divided into two parts, and it is determined whether or not the hardware fixed area is being accessed based on the address information determined via the Matsupa. The present invention relates to an access control method for a data processing device that accesses a storage device.

In the central processing unit including the microprocessor unit, the bits of address information are predetermined.
For example, if the bit width is 16 bits, only 64 KB of main memory can be accessed.

I can't. One known method for expanding the address space that can be accessed in such a system is to use address extension bits. This method uses Matsupa, as will be described later with reference to FIG. In the case of the method using the mapper, a mapping register is provided in the mapper. By selecting one of the mapping registers, the mapping register is selected.
The contents written in the register are extracted, and the address position to be accessed is determined based on the contents. On the other hand, the address space is generally organized into one address system, which consists of a storage area on the main memory device, a part of the CPU's internal registers, an input/output control register, and a hardware fixed area that includes the program switch area. They are organized into one address system.

When expanding the address space using the mapper, it is desirable to also expand the hardware fixed area, particularly the input/output control register area.

Conventionally, the hardware fixed area has been defined as the first area of the address space, but when expanding the above hardware fixed area, attempting to expand the above first area would require major changes to the existing address system. This is not desirable. The present invention aims to solve the above-mentioned problems, and makes it possible to set the expanded hardware fixed area in a semi-fixed state, for example, in the terminal area of the expanded address space, and to set the expanded hardware fixed area in a semi-fixed state, for example, in the terminal area of the expanded address space, and to The purpose is to properly coordinate expansion processing. To this end, the access control method of the data processing device of the present invention includes a central processing unit including a microprocessor unit, and controls access control to the main memory. In a data processing system that determines and accesses address information via Matsupa,
The address space including the storage area of the main storage device is divided into the storage area and at least a hardware/fixed area, and the hardware fixed area is distributed into a head area and an end area of the address space. a first configuration information storage unit that stores information regarding the end area, a second configuration information storage unit that stores information regarding the head/first area, and at least one of the address information determined via the mapper. first and second comparison units that respectively compare the information obtained from the information stored in the first and second configuration information storage units, and select mapping information from the comparison results of the first comparison unit. and a selection section that is enabled in accordance with a signal, so that when the address information determined via the mapper specifies the hardware fixed area, the access is made separately from the access to the main storage device. It is characterized by

This will be explained below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of a data processing system to which the present invention is applied;
FIG. 3 is an explanatory diagram illustrating address information determination processing by Matsupa, FIG. 3 is an explanatory diagram illustrating an expanded address space used in the present invention, and FIG. 4 shows the configuration of an embodiment of the present invention.

In FIG. 1, 1 is a central processing unit, 2 is a central processing unit,
3 is a memory access control unit, 4 is a memory bus with a bus width of, for example, 32 bits, 5 is an input/output bus, 6 is a common bus with a bus width of, for example, 16 bits, r is a high-speed direct memory access bus, for example, having a bus width of 32 bits, 8 is a main memory, 9-0, 9-1, . . . are channels, 10-0, 10-, respectively. 1, 10-2, . . . are input/output control devices, 11-0, 11-1, 11-2, .
represent input/output devices, respectively.

Further, the central processing section 2 is controlled by a microprocessor unit, 12 is a system control section, 13 is a writable control memory, 14 is a control memory in which a microprogram is stored, 15 is an arithmetic section/register section, 16
1r represents an operation panel section, 1r a various function section, 18 a floating point arithmetic section provided as an option, and 19 a decimal arithmetic section provided as an option. Furthermore, in the memory access control unit 3, 20 is a common bus control unit, 21 is a high-speed direct memory access bus control unit, and 22
23 is a selection/distribution circuit section, 23 is a first mapper used for accessing the main storage device 8 from the central processing section 2, and 24 is a second mapper for direct memory access. Reference numeral 25 represents a memory bus control section. The central processing unit 2 is
It is equipped with a microprocessor unit and processes are carried out by a microprogram stored in a control memory 14.

In the case shown in the figure, this operation is performed by the fact that the writable control memory 13 is provided and the calculation unit 18,
19, there is no difference from the conventionally known one. In the case of a processing system having a microprocessor unit, the bit width of the address information is predetermined as is well known.

Therefore, for example, if address information is defined as 16 bits, the storage capacity that can be held as the main memory device 8 is 6 bits.
Number 4K is suppressed to the ground. Therefore, when using the main storage device 8 with a larger storage capacity, the address space that can be accessed can be expanded by using mappers 23 and 24 as shown in the figure, as will be described later with reference to FIG. will be carried out. 1 In the case shown in FIG. 1, the main storage device 8 is accessed using the mappers 23 and 24. When the central processing unit 2 accesses, the Matsupa 23 is used to access the direct memory.
When the main storage device 8 is accessed by access, the Matsu 1P 24 is used. This makes it possible to perform address information determination processing in parallel in the event that there is a conflict between accesses between the two parties.
Countermeasures are taken, such as making the spaces accessed different depending on the type of access. 2 FIG. 2 explains the address information determination process by Matsupa and the prerequisite problem of the present invention.

In FIG. 2, numerals 8 and 23 correspond to those in FIG. 1, and 26
is an address register (or address information), 2r is an extended address bit register (or extended address information bit), and 28-0, 28-1, ...28-7 are mapping register tables, respectively. ,29-0,29
-1, ..., 29-31 are mapping registers, 30 is a mapping register table selection decoder, 31 is a mapping register selection decoder, 3
2 is a mapping address register whose contents are used to access the main memory 8; 33-0;
, 33-1..., 33-7 are respectively address spaces (T
7-segment block).
5. As mentioned above, particularly in the case of a data processing device including a microprocessor unit, the bit width of address information is predetermined, for example, to 16 bits. For this reason, when attempting to access an address space exceeding 64K addresses, the mappers 23 and 24 expand the accessible address space. Address determination processing by the mapper is performed as follows. That is, (
1) For example, the access address information is set in a 16-bit address register 26, and an extended address bit register 27 is prepared.

). ) Corresponding to the number of bits in the extended address bit register 27, for example, in the case of 3 bits, eight mapping register tables 28-0, 28-1, . . .
... 28-7 are prepared. 03) Mapping registers 29-0, 29-1, . . . , 29-
31 selections, 32 mapping registers 29-0, 29-1, . . . are added to each of the mapping register tables 28-0, 28-1, .
, 29-31 are prepared.

4) Each register 29-0, 29-1, ... in the mapping register table 28-0, each register 29-0, 2 in the mapping register table 28-1
9-1, . . . respectively store, for example, 13-bit address information AD and other information.

5) Given 16 bits of access address information, only 64KB of address space can be accessed.

For this purpose, for example, 3 bits are added by the extended address O bit register 2r, so that an extended address space of 512 KB can be accessed. In order to prevent the address space of 512 KB from being fixed by the contents of the register 21, a mapping register 29 is used, and the contents of the mapping register 29, that is, the address information AD, are used. , any 512KB address space can be selected.

(6) For example, as the contents of register 21, IOOQl
Suppose that ``00000++Chi...Shu'' is given as the content of the address register 26 while .

In this case, the contents of register 21. Mapping register table 28-0 is selected by A, and mapping register table 29-0 is selected by B of register 26.
is selected. (7) As a result, the address information AD stored in the mapping register 29-0 is set to the upper part of the register 32, while the contents A of the register 26
Dl is set in the lower part of register 32, and the total, e.g.
Expanded to 4-bit address information.

Then, the main storage device 8 is accessed using the expanded address information. (8) In the case shown in FIG. 2, the number of mapping registers 29 is given by a total of 32×8, so if the contents of the mapping register 29 are not changed, the accessible address space is 51 in total.
It will be 2KB.

However, by rewriting the contents of the mapping register 29, if 13-bit address information is stored in the register 29, a maximum of 16 MB of address space can be accessed. By using Matsupa as described above, it becomes possible to expand the address space that can be accessed.

However, along with such expansion of the address space, it is desirable to expand the so-called hardware fixed area, particularly the input/output control register area, as described at the beginning of this specification. 2. FIG. 3 shows an explanatory diagram for explaining the expanded address space used in the present invention, and the symbols 33-0 to 33-γ in the figure correspond to those in FIG. 2, respectively. Further, 34A, 34B, and 34C represent hardware fixed areas, respectively. z Conventionally, the hardware fixed area 34 is composed of (1) a CPU register area, (11) a human output control register area, and ii) a program switch area. The CPU register area is located at address 0000 (
hexadecimal) to 003F. The input/output control register is also 4032B from address 0040 (hexadecimal) to 0FFF (hexadecimal), and the program
The switch area is allocated 116B from addresses 1000 (hexadecimal) to 1073 (hexadecimal) (in hexadecimal) of the elbow 0 segment block 33-0. However, in the case of address expansion as described above, if you try to expand the hardware fixed area, especially the input/output control register area, the existing address system described above will be destroyed. This is not desirable.

For this reason, in one embodiment of the present invention, an expanded hardware fixed area is prepared in the terminal area of the expanded address space, as shown as the hardware fixed area 34C shown in FIG. The area 34C can be specified, for example, in units of 4 KB up to a maximum of 60 KB by hardware settings (semi-fixed). FIG. 4 shows the configuration of an embodiment of the present invention.

The symbols 23, 26, 21, 30, 31, and 32 in the figure are the second
Corresponding to the figure, 35 and 36 are dog configuration information storage units, 3r,
38 is a comparison circuit, 39 is a bit inversion, 40 is an inversion bit, 41 is an AND circuit, and 42 is an OR circuit. The configuration information storage unit 35 has the address 100 shown in FIG.
The highest 4 bits corresponding to 0 (hexadecimal) “0001 (
1000 (16
This is used as the criterion for determining whether or not the

On the other hand, the size of the hardware fixed area 34C shown in FIG. 3 is set in the configuration information storage section 36. For example, 8K
If it has a size of B, it is set to ``0010 (binary)'' because it is 2 units with 4 KB as 1 unit. The binary number "0010" is bit-inverted by the bit inversion 39, and becomes [1101] as shown in the illustrated inversion bit 40.
(binary).” Then, the address information (contents of the register 32) generated via the Matsupa 23 is stored in the area 34C.
The criterion is whether or not it is within the range. Note that the inverted bit "1101 (binary)" is the most significant 4 bits [1
101”. That is, FFFF (hexadecimal) -
It corresponds to 1000 (hexadecimal).

Generally, the illustrated bit inversion 39 and the inversion bit 40 are omitted, and "00" is written directly to the configuration information storage section 36 itself.
It can be thought of as setting ``1101'' which is the result of bit inversion of ``10''. As explained with reference to Figure 2,
The contents of extended address bit register 2T is the value [7].
If you show . Mapping register table 28-
7 is selected.

When the table 28-7 is selected, if it is determined that the address space (I7 segment block) 33-1 shown in FIG. 2 is to be accessed, the comparison circuit 38
The condition for outputting a logic "1" and turning on the AND circuit 41 is that the contents of the register 32 indicate an address within the area 34C shown in FIG. Further, the condition for the comparison circuit 37 to output a logic "1" is that the contents of the register 32 indicate an address within the area 34A shown in FIG. Therefore, access to the main storage device 8 is prohibited on condition that the OR circuit 42 is turned on. Furthermore, depending on the contents of the extended address bit register 27, the mapping register table 2 shown in FIG.
If selecting 8-1 and accessing address space (7-segment block) 33-r do not necessarily have the same meaning, based on the contents of register 32, It is sufficient to determine that the address space (7-segment block) 33-T has been accessed.

As explained above, according to the present invention, it is possible to allocate a hardware fixed area in an expanded address space without changing the existing address system.

And Matsuno expands the address space. This makes it possible to coordinate correctly with the market. Furthermore, the configuration information storage section 36 only needs to have 4 bits of information at most.

[Brief explanation of the drawing]

Fig. 1 shows the configuration of an embodiment of a data processing system to which the present invention is applied, Fig. 2 is an explanatory diagram illustrating address information determination processing by Matsupa, and Fig. 3 shows an extended address used in the present invention. FIG. 4, an explanatory diagram for explaining the space, shows the configuration of an embodiment of the present invention. In the figure, 1 is the central processing unit, 2 is the central processing unit, 8 is the main memory, 23, 24 are matsupa, 28-0, 28-1, etc.
... is mapping register table, 29-0,2
9-1, ... are mapping registers, 33-0,
33-1, . . . are address spaces (segment blocks), 34 is a hardware fixed area, and 35 and 36 are configuration information storage units, respectively.

Claims (1)

[Scope of Claims] 1. A data processing system that includes a central processing unit including a microprocessor unit and that determines address information via a mapper when accessing a main memory, The address space including the storage area of the device is divided into the storage area and at least a hardware fixed area, and the hardware fixed area is distributed into a head area and an end area of the address space, and A first configuration information storage unit that stores information regarding the area, a second configuration information storage unit that stores information regarding the head-initial area, and at least part of the address information determined via the Matsupa and the first and second comparison sections that compare the information obtained from the storage information of the first and second configuration information storage sections, respectively, and the comparison results of the first comparison section according to a predetermined mapping information selection signal. and a selection section for enabling.
An access control method for a data processing device, characterized in that when the address information determined via the mapper specifies the hardware fixed area, the access is performed separately from the access to the main storage device. 2. An access control system for a data processing device according to claim 1, wherein the hardware fixed area configured in the terminal area is variable in size in units of predetermined size. .