JPS5979776A - Thermal head - Google Patents

Thermal head

Info

Publication number
JPS5979776A
JPS5979776A JP19010682A JP19010682A JPS5979776A JP S5979776 A JPS5979776 A JP S5979776A JP 19010682 A JP19010682 A JP 19010682A JP 19010682 A JP19010682 A JP 19010682A JP S5979776 A JPS5979776 A JP S5979776A
Authority
JP
Japan
Prior art keywords
electrodes
row
thermal head
integrated circuit
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19010682A
Other languages
Japanese (ja)
Inventor
Shozo Takeno
武野 尚三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19010682A priority Critical patent/JPS5979776A/en
Publication of JPS5979776A publication Critical patent/JPS5979776A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/335Structure of thermal heads

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To enable to easily manufacture a thermal head, by a method wherein belt form insulating films are provided on small common electrodes and on individual electrodes between a row of heating resistors and integrated circuit chips in the direction of the row of the heating resistors, and large common electrodes are provided thereon. CONSTITUTION:The row of heating resistors 13 is provided at a substantially central part of an aluminum substrate 11 covered by a glaze layer 12, and 64- element IC chips 14 are provided alternately on opposite sides of the row. Both ends of each of the row of heating resistors 13 are connected to individual electrodes 16a, 16b consisting of the first lead layer 15, the electrodes 16a are connected in common to the IC chips 14, while the electrodes 16b are connected in common to the small common electrodes 17 on a group basis, and belt form insulating films 18a, 18b parallel with the row of heating resistors 13 are provided on the individual electrodes 16a and the small common electrodes 17. On this assembly, the large common electrodes 19a, 19b consisting of the second lead layer are provided, whereby the small common electrodes 17 are connected in common. Accordingly, the thermal head can be easily manufactured, and the size thereof is reduced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、ダイレクトドライブ法のザーマルヘッドに
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a direct drive thermal head.

〔発明の技術的背景−とその問題点〕[Technical background of the invention and its problems]

サーマル記録の高速化を達成する手段として、発熱抵抗
体に対し、駆動回路を1対1に設け、それぞれの発熱抵
抗体を個別に駆動するダイレクトドライブ法がある。駆
動回路およびそれの制御回路はLSI化され、発熱抵抗
体が配設された基板上の電極に実装されるのが一般的で
ある。
As a means of achieving high-speed thermal recording, there is a direct drive method in which drive circuits are provided one-to-one for each heat-generating resistor and each heat-generating resistor is driven individually. The drive circuit and its control circuit are generally integrated into an LSI and mounted on an electrode on a substrate on which a heating resistor is provided.

しかし高密度ザーマルヘッドになると、発熱抵抗体と同
数の駆動回路および制御回路を1対1に対応して設ける
ことがスペースの上で困難と4る。
However, when it comes to high-density thermal heads, it is difficult to provide the same number of drive circuits and control circuits as heating resistors in one-to-one correspondence due to space limitations.

例えば発熱抵抗体が12本/mmの密度で213門の長
さをカバーするよう2,560本並んでいる場合、駆動
回路および制御回路を内蔵するロジックLSIは、1チ
、2プに64素子が収容されているとして40チツゾが
必要となる。低消費電力と高速性が要求される制御回路
は高密度にすることができるが、高耐圧、高電流が要求
される駆動回路を有するだめにロジックLSIのチップ
ザイズはそれほど小さく出来ず、64素子内蔵のもので
53朔角程度である。12本/rnTnの発熱抵抗体列
は64本で約5.3泪の長さとなるので、ロジックLS
Iはチップを1列に並べれば事足りるように思われるが
、現状では12本/爺というような高密度の配線技術が
無いので、このようなレイアウトはとれない。ロジック
端子、’f[i’、源、アース端子を含めて1チツプ当
た980個程鹿の端子はチップの411に配置され、発
熱抵抗体と直列に接続される端子は上、左、右の3辺に
、コントロール端子は下辺に配置される。従って左、右
両辺に接続するリードを基板に形成するスペースが必要
となる。すなわち発熱抵抗体列長とほぼ同じ寸法にLS
I実装部を納めるとすると、必ず多層配線(少なくとも
2層配線)が必要となる。しかしながら、この多層配線
の形成は、LS4デツプ間のスペースがとれない関係も
あって、技術的に難しく、歩留りよく安価に達成するこ
とは困難であった。
For example, if 2,560 heating resistors are lined up to cover the length of 213 gates at a density of 12 resistors/mm, a logic LSI with built-in drive circuits and control circuits will have 64 elements on 1 chip and 2 chips. Assuming that it is accommodated, 40 chituzo will be required. Control circuits that require low power consumption and high speed can be made highly dense, but the chip size of logic LSIs cannot be made that small because they have drive circuits that require high voltage and high current. The built-in one is about 53 square degrees. The length of the heating resistor array of 12/rnTn is 64, which is approximately 5.3mm, so the logic LS
It would seem that arranging the chips in one row would be sufficient for I, but at present there is no high-density wiring technology such as 12 wires per row, so such a layout is not possible. Approximately 980 terminals per chip, including the logic terminal, 'f[i', source, and ground terminals, are placed at 411 of the chip, and the terminals connected in series with the heating resistor are on the top, left, and right. The control terminals are placed on the bottom side. Therefore, space is required to form leads connected to both the left and right sides on the board. In other words, the LS is approximately the same as the length of the heating resistor row.
If an I-mounting section is to be accommodated, multilayer wiring (at least two layers of wiring) is definitely required. However, the formation of this multilayer wiring is technically difficult due to the lack of space between the LS4 depths, and it has been difficult to achieve this at a high yield and at low cost.

上記の困難を改良するものとして、!1ヲ開昭56−1
06878号公報に記載されたサーマルヘッドがある。
As an improvement over the above difficulties! 1. Opened in 1977-1.
There is a thermal head described in Japanese Patent No. 06878.

これは第1図に示すように、発熱抵抗体列1を基板のほ
ぼ中央に配設し、それを例えば8本ずつからなる複数の
グループに分割しグループ毎に交互に発熱抵抗体列1の
両側に振分けて駆動回路2および制御回路3を配設した
ものである。駆動回路2および制御回路3はグループ単
位でまとめられて集猜回路チップ(以下ICチップとい
う)4となる。+5a。
As shown in Fig. 1, the heat generating resistor row 1 is arranged approximately in the center of the board, and it is divided into a plurality of groups each consisting of, for example, 8 resistors, and each group is alternately placed in the heat generating resistor row 1. A drive circuit 2 and a control circuit 3 are arranged on both sides. The drive circuit 2 and the control circuit 3 are grouped together to form a concentrator circuit chip (hereinafter referred to as an IC chip) 4. +5a.

6bは発熱抵抗体列1のICチップ4側と反対側の端部
を共通に接続する共通i15、極、7は駆動電源である
Reference numeral 6b indicates a common electrode 15, which commonly connects the ends of the heating resistor array 1 opposite to the IC chip 4 side, and 7 indicates a drive power source.

このようにすると、発熱抵抗体列1の両側のスペースを
有効に利用でき、実装上有利となる。
In this way, the space on both sides of the heating resistor row 1 can be used effectively, which is advantageous in terms of mounting.

しかし力から、このような配置をとった場合、共jID
電J:’$、 6 a 、 6 bをどのようにして基
板外にうnき出すかが問題となる。一つには個別電極5
 a 、 、5 bを基板の端部近くまで延長させ、そ
の延同部に共通電弾6a、6bを設ける方法がり5えら
れるが、個別電極5 a、 、 5 bは大箱1流が流
れる関係上、薄膜では線幅を数mm 8度と広くとる必
要があり、これではICチップ4を発熱抵抗体列10両
側にそれぞれ一列に並べると、ICチップ4の相互間に
個別電極5a、5bを通すことは物理的に困難となる。
However, due to power, if we take this arrangement, the common jID
The problem is how to get the electrons J:'$, 6a, and 6b out of the board. One is the individual electrode 5
There are several methods of extending a, 5b to near the edge of the board and providing common electric bullets 6a, 6b in the same extended portion, but the individual electrodes 5a, 5b have a large box current. For this reason, in a thin film, it is necessary to have a wide line width of several mm and 8 degrees, and in this case, when the IC chips 4 are arranged in a row on both sides of the heating resistor row 10, individual electrodes 5a and 5b are formed between the IC chips 4. It is physically difficult to pass through.

他の方法としてフライングワイアリードを用いることが
考えられるが、リードの他の要素との接触による変形、
破損が起り易く、信頼性に問題がある。
Another method is to use a flying wire lead, but the lead may deform due to contact with other elements.
It is easily damaged and has reliability problems.

〔発明の目的〕[Purpose of the invention]

この発明の目的は、発熱抵抗体列と、1駆動回路お・よ
び制御回路を同一基板−ヒに配設したグイレクトドライ
ブ形ザーマルヘッドであって、製造が容易でコンパクト
に且つ安価に実現可能なす゛−マルヘッ1°を提供する
ことである。
An object of the present invention is to provide a direct drive type thermal head in which a heating resistor array, a drive circuit, and a control circuit are arranged on the same substrate, which is easy to manufacture, compact, and inexpensive. The goal is to provide a 1° Maruhek.

〔発明の概要〕[Summary of the invention]

この発明は基板上のほぼ中央部に発熱抵抗体列を配設し
、その両側に発熱抵抗体を個別に駆動する駆動回路およ
びその制御回路を所定のグループ単位でまとめた集積回
路チップを交互に振分けて配置してなるサーマルヘッド
において、前記発熱抵抗体列の前記集積回路チップに接
続される側と反対側の端部をグループ単位で共通接続す
る小共通電極を発熱抵抗体列と集積回路チップ配設位置
との間に形成し、これらの小共通電極上および発熱抵抗
体列と集積回路チップとを個別に接続する個別電極上に
発熱抵抗体配列方向に沿って帯状の絶縁j[αを形成し
、この絶縁膜上にバイアホールを通して発熱抵抗体列に
対し同一の側にある小共通電極どうしを接続する大共通
電極を形成したことを特徴とする。
In this invention, a row of heating resistors is disposed approximately in the center of a substrate, and on both sides of the array, integrated circuit chips in which drive circuits for individually driving the heating resistors and their control circuits are arranged in predetermined groups are arranged alternately. In a thermal head that is arranged in a divided manner, a small common electrode that commonly connects the ends of the heat generating resistor row opposite to the side connected to the integrated circuit chip in groups is connected to the heat generating resistor row and the integrated circuit chip. A band-shaped insulation j [α A large common electrode is formed on the insulating film to connect small common electrodes on the same side with respect to the heating resistor array through via holes.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、発熱抵抗体列の集積回路チップに接
続される側の端部の共通接続を、発熱抵抗体列と集積回
路チップ配設位置との間で行なうだめ、個別電極を集積
回路チップ相互間を通過さ)Fる必要がない。従って集
積回路チップを発熱抵抗体列の両側にそれぞれ一列に、
大きな間隔をあけることなく並べることが可能となり、
リーーマルヘッドの小型化を図ることができる。
According to this invention, in order to make a common connection between the ends of the heat generating resistor array connected to the integrated circuit chip between the heat generating resistor array and the integrated circuit chip arrangement position, the individual electrodes are connected to the integrated circuit chip. There is no need to pass between chips. Therefore, the integrated circuit chips are arranged in a row on both sides of the heating resistor row.
It is now possible to arrange them without leaving large gaps,
It is possible to downsize the legal head.

−まか9、グノト一ノ毎に発熱抵抗体の一端を小共通市
、 )、rTHjでJIH通接<、7+:するので小共
通電極に広いスペースを当てることができ、その面積を
大きくとることが可能であり、これらの間を接続する大
共通正極は)ii状の単純な構造で良く、また小共通電
極とのバイアポール接続も粗い・やターンで良いので製
造が容易であり、信頼性も向上する。
- Maka 9, one end of the heating resistor for each gnoto is connected to the small common electrode, ), JIH connection <, 7+: at rTHj, so a wide space can be devoted to the small common electrode, and its area can be increased. The large common positive electrode connecting between these electrodes can have a simple structure in the form of ii), and the via pole connection with the small common electrode can also be made with a rough or slightly turned structure, making it easy to manufacture and reliable. Sexuality also improves.

さらに発熱抵抗体から集積回路チップに到る個別?1.
、極と大共通電極との絶縁をとる絶縁膜も単純な’!j
’+’状の幅広のものでよく、発熱抵抗体列をはさんで
2不平行に形成すればよいので、この絶縁膜はスクリー
ン印刷法により容易に形成可能である。この場合、上記
絶縁膜としてポリイミド樹脂を用いればガラス等を用い
る場合に比し熱プロセスが低温ですみ基板のそり等の発
生を避けることができる。寸たS i02膜の付着に比
し広面積にピンホールの無い絶縁膜を得ることができる
。ポリイミド樹脂の絶縁膜は、スクリーン印刷で設けた
場合、スピン塗布とホトエツチングで設けた場合でも良
好なテーパー形状のバイアホールを形成できるので、ス
テップカバレッジは良好で信頼性に優れたものとなる。
Furthermore, individual products ranging from heating resistors to integrated circuit chips? 1.
, the insulating film that insulates the poles and the large common electrode is also simple'! j
This insulating film can be easily formed by screen printing, since it can be a wide '+'-shaped insulating film and can be formed in two nonparallel ways with the heating resistor array sandwiched therebetween. In this case, if polyimide resin is used as the insulating film, the thermal process can be performed at a lower temperature than when glass or the like is used, and the occurrence of warping of the substrate can be avoided. A pinhole-free insulating film can be obtained over a wider area than when a small Si02 film is deposited. Even when the polyimide resin insulating film is provided by screen printing, spin coating, and photoetching, it is possible to form a via hole with a good tapered shape, resulting in good step coverage and excellent reliability.

以上から、本発明によれば広い面積にわたり無欠陥のサ
ーマルヘッドが発熱抵抗体列の密度に対して約1/2の
密度のリード配線で実現できるので、従来に比べ小形か
つ安価で信頼性に優れたサーマルヘッドが得られる。
From the above, according to the present invention, a defect-free thermal head over a wide area can be realized with lead wiring density that is approximately 1/2 of the density of the heating resistor array, so it is smaller, cheaper, and more reliable than the conventional one. An excellent thermal head can be obtained.

〔発明の実施例〕[Embodiments of the invention]

第2図(a)はこの発明の一実施例に係るサーマルヘッ
ドの平面図、(b)は(a)のA −A’矢視断面図で
ある。図において、11は表面にグレーズ層12が被着
されたアルミナ等の絶縁基板であり、その#1は中央部
に発熱抵抗体列13が形成され、その両側に後述する各
種電極および集積回路チップ(以下ICチップという)
14が配設されている。ICチップ14は発熱抵抗体を
個別に駆動する駆動回路およびその制御回路を例えば6
4素子ずつからなる所定のグループ単位でまとめだもの
で、発熱抵抗体列13の両側に交互に振分けらJ+−で
配置されている。
FIG. 2(a) is a plan view of a thermal head according to an embodiment of the present invention, and FIG. 2(b) is a sectional view taken along the line A-A' in FIG. 2(a). In the figure, numeral 11 is an insulating substrate made of alumina or the like with a glaze layer 12 adhered to its surface, and #1 has a heating resistor row 13 formed in the center, and on both sides various electrodes and integrated circuit chips, which will be described later. (hereinafter referred to as IC chip)
14 are arranged. The IC chip 14 has a drive circuit for individually driving the heating resistor and its control circuit, for example, 6.
They are grouped into predetermined groups each consisting of four elements, and are arranged alternately on both sides of the heating resistor row 13 in J+-.

発熱抵抗体列13の各々の両端は第1リード層15から
なる個別電極16a、16bに接続さjt−%一方の個
別電極16aはICチップ014に接続され、他方の個
別’f[極16bはグループ単位で小共通電極17によ
って共通接続されている。発熱抵抗体列13とICチッ
プ14との間の個別電極16aおよび小共通電極17上
に、発熱抵抗体列13と平行に帯状の絶縁膜18a。
Both ends of each of the heating resistor rows 13 are connected to individual electrodes 16a and 16b made of the first lead layer 15. One individual electrode 16a is connected to the IC chip 014, and the other individual 'f [pole 16b is Each group is commonly connected by a small common electrode 17. A strip-shaped insulating film 18a is provided on the individual electrodes 16a and the small common electrodes 17 between the heating resistor row 13 and the IC chip 14 in parallel with the heating resistor row 13.

18bが形成されている。そして絶縁膜18a。18b is formed. and an insulating film 18a.

18b上に第2のリード層からなる大共通正極19a、
19bが形成され、この大共通電極19m、19bによ
って小共通電極17を共通接続している。
a large common positive electrode 19a consisting of a second lead layer on 18b;
19b is formed, and the small common electrodes 17 are commonly connected by the large common electrodes 19m and 19b.

次に、このようにして構成されるり=−マルヘッドの製
造プロセスの一例を第3図(a) (b)を参照して説
明する。まず熱的に設計された厚さを有する保温層を表
面に刺着した熱的良導体からなる平板状基板、例えばグ
レーズドアルミナ基板11が用意される。これはホーロ
引金属板であっても良い。このグレーズドアルミナ基板
1ノ上に、発熱抵抗体列゛13となる抵抗膜例えばTa
−8102スパツタリング膜を付着し、次いで第1リー
ド層15として例えばCr/Au/Crを!〔空蒸着等
の手段により積層細論する。これはCr/Atのような
Auを使わない安価なメタル第1り成をとることもでき
る。第2図(b)は第1リード層15が後者のCr層J
5JLとAt層15bの2層膜の場合を示している。次
に第1リード層15を第3図(a)の如きパターンでホ
トエツチングする。このパターンは64木を1グルーグ
として、発熱抵抗体列13の一端を個別+11、極16
bを介して小共通電極1.7で結び、他端は駆動回路お
よび制御回路を収容したICチップ14に2jhびく個
別’i、I、極16aが64本走っているパターンを1
単付として、1グループ毎に父互に反転しながら繰り返
えして同一ピッチで複数グループ並べたパターンからな
る。尚1グル一プ128本の場合もあり得る。
Next, an example of the manufacturing process of the rim head constructed in this manner will be described with reference to FIGS. 3(a) and 3(b). First, a flat substrate made of a thermally good conductor, for example, the glazed alumina substrate 11, on which a heat insulating layer having a thermally designed thickness is stuck is prepared. This may be a hollow metal plate. On this glazed alumina substrate 1, a resistive film, for example, a Ta
-8102 sputtering film is deposited, and then the first lead layer 15 is made of, for example, Cr/Au/Cr! [Details of lamination by means such as empty evaporation. This can also be made of an inexpensive metal first material such as Cr/At that does not use Au. FIG. 2(b) shows that the first lead layer 15 is the latter Cr layer J.
A case of a two-layer film of 5JL and At layer 15b is shown. Next, the first lead layer 15 is photo-etched in a pattern as shown in FIG. 3(a). This pattern has 64 trees as one group, and one end of the heating resistor row 13 is individually +11, pole 16.
A pattern in which 64 individual 'i', I, poles 16a running 2jh apart are connected to the small common electrode 1.7 through the small common electrode 1.7, and the other end is connected to the IC chip 14 containing the drive circuit and the control circuit.
As a single attachment, it consists of a pattern in which multiple groups are arranged at the same pitch by repeating each group while reversing each other. It is also possible that one group has 128 pieces.

次に児・板11の中央部刊近に発熱抵抗体列13が来る
J:うにしながら発熱抵抗体長さ分の2−I+、1リ−
l゛層15をポトエ′ッチッグによシ除去して4it;
 U+、 IF、!を霧出させ、発熱抵抗体列13を形
JJi、’する。次に発熱抵抗体列13を耐摩耗保護膜
(図示ぜず)により被梼する。これは感熱紙の圧ス゛ロ
ア1: ffl’lによる摩耗を防ぎ、発熱抵抗体の寿
命に艮くする目自勺のもので、Ta205、Sin、 
SiN等がス・やツクリングにより刺着される。次に、
+iiJ熱性高分子膜、例えばポリイミドフェスを塗イ
6 布したのち熱硬4ぜた11%を絶縁膜18 a 、18
bとして第1リードf@ 15上の一部分のみに刺着す
る。絶縁膜IFIa、18bは第3図(a)に示すよう
に発熱抵抗体列13をはさんで同方向に並ぶ(1ν状の
単純な形状なので、プリント印刷法による′i′、1″
布が可能である。他の例どしてスビイコートあるい(こ
l、ローラコ−1・法により全面に刊漸したのら、ホト
レジストをマスクにしたケミカルエツチングあるいし:
j、ドライエツチングを行なっても良い。いずれの場合
も絶縁1ト一\18a。
Next, a row of heating resistors 13 is placed near the center of the board 11.J: 2-I+ for the length of the heating resistors, 1 lead-
Remove the layer 15 by pot etching for 4 times;
U+, IF,! The heating resistor array 13 is formed into a shape JJi,'. Next, the heating resistor array 13 is covered with a wear-resistant protective film (not shown). This is intended to prevent wear caused by pressure roller 1: ffl'l of thermal paper and significantly shorten the lifespan of the heating resistor.
SiN or the like is attached by suction or tsukling. next,
+iiJ Apply a thermosetting polymer film, for example, a polyimide face 6 After coating, apply 11% of thermoset 4 as an insulating film 18 a, 18
As b, it is attached only to a part of the first lead f@15. The insulating films IFIa and 18b are arranged in the same direction across the heating resistor array 13 as shown in FIG.
Cloth is possible. Other examples include chemical etching using photoresist as a mask after coating the entire surface using Subi-coat or Roller-coat 1 method:
j. Dry etching may be performed. In either case, insulation 1 to 1\18a.

18bは良好なチー/F形状がイ:↑られるので、次の
第2リード層の付着時に、第1リード層15とのバイア
ホール接続t」、容易に達成される0縮合反応をおこし
、完全にポリイミド(6目11)にするため、窒素界囲
気において350℃、L H加熱する。この温度はガラ
ス絶縁に閉する8 50 ℃に比べ十分低く、歩留りニ
1.向上する。次に第2リード層を真空蒸着等の手段に
より付着する。
Since 18b has a good Q/F shape, when the next second lead layer is attached, the via hole connection with the first lead layer 15 is easily achieved, causing a complete condensation reaction. In order to make polyimide (6 meshes 11), it is heated at 350° C. with LH in a nitrogen atmosphere. This temperature is sufficiently lower than the 850°C that is required for glass insulation, and the yield is 21. improves. A second lead layer is then deposited by means such as vacuum deposition.

第2リード層は’l”i/AuあるいはAt等の薄膜か
らなる。この第2リード層を1()3図(1))のよう
にホトエツチングすると、分割したグループの奇数番目
の小共通電極同志を結ぶ大共通電極19aと、イ出数番
目の小共通電極同志を結ぶ大共通電極19bが形成され
る。これらの大共通電極19n、19bは絶縁膜18g
、18bによりその下を通る個別(Hi、椅16 a 
+ 16 bとは絶縁を保たれている。大共通電極19
a、19bの基板J1外へのとり出し6′よ、1ト極1
9a、19bを発熱抵抗体列13と平行に走らゼだのち
、基4M、 11の端部からその寸まの方向へとり出し
ても良いし、そこから信置方向に導き他のロジック端子
等−と同じ側からとり出しても良い。(1本に止どめら
れるのでスペースは小さい)。
The second lead layer is made of a thin film such as 'l''i/Au or At. When this second lead layer is photoetched as shown in Figure 1()3(1)), the odd-numbered small common electrodes of the divided groups are A large common electrode 19a that connects the two small common electrodes and a large common electrode 19b that connects the numbered small common electrodes are formed.These large common electrodes 19n and 19b are connected to the insulating film 18g.
, 18b, the individual (Hi, chair 16 a
+16b is kept insulated from the other side. Large common electrode 19
a, take out 19b to the outside of the board J1 6', 1 to pole 1
9a and 19b run parallel to the heating resistor row 13, and then they can be taken out from the ends of the bases 4M and 11 in the same direction, or they can be guided from there in the direction of the wire and connected to other logic terminals, etc. You can take it out from the same side as -. (The space is small because it can be stopped at just one).

次に第2図(a) (b)に示し/こように第1リード
層のダ・fポンプ゛イングパッt’ N! J二にIc
チチン14肴−装尾一し、イ固男1 ’rJ¥ 4d区
16thおよびロジックi7i!A子2o%+Hにワイ
ヤデンブ゛イングにより接続する。
Next, as shown in FIGS. 2(a) and 2(b), the first lead layer is exposed to the pumping pad t'N! J second Ic
Chichin 14 appetizers - Soo Ichishi, Igao 1 'rJ¥ 4d ward 16th and logic i7i! Connect to A terminal 2o% + H by wire debugging.

【図面の簡単な説明】[Brief explanation of the drawing]

5> 1図は従来のサーマルヘッドの構成図、第2図(
FL) (b目」この発明の一実施例に係るサーマルヘ
ッドの平面図お・よびA −A’矢祝断面図、第3図(
a)(h)はその膜端プロセスを説明するだめの千1■
図である。 11・・・基板、13・・・発熱抵抗体列、14・・・
ICチップ、1611. 、16 b・・・個別型棒、
17・・・小共通電極、IFIt+、lRb−・・絶縁
膜、19a。 19b・・・大共通電極。 出願人代理人  弁理士 鈴 江 武 彦m 1 口 今 第2図 伸 第2図 (b) 第3図 (a)
5> Figure 1 is a configuration diagram of a conventional thermal head, Figure 2 (
FL) (b) A plan view of a thermal head according to an embodiment of the present invention and a sectional view taken along the line A-A', FIG.
a) (h) is an explanation of the membrane edge process.
It is a diagram. DESCRIPTION OF SYMBOLS 11... Board, 13... Heating resistor row, 14...
IC chip, 1611. , 16 b...individual type rod,
17... Small common electrode, IFIt+, lRb-... Insulating film, 19a. 19b...Large common electrode. Applicant's agent Patent attorney Takehiko Suzue 1 Kuchima Figure 2 Shin Figure 2 (b) Figure 3 (a)

Claims (2)

【特許請求の範囲】[Claims] (1)基板上のほぼ中央部に発熱抵抗体列を配設し、そ
の両側に発熱抵抗体を個別に駆動する駆Sh回路および
その制御回路を所定のグループ単位で寸とめた集積回路
チップを交互に振分けて配置r1: してなるザーマル
ヘッドにおいて、前記発熱抵抗体列の前記集積回路チッ
プに接続される側と反対側の端部をグループ中−位で共
通接続する小共通t1を極を発熱抵抗体列と集積回路チ
ップ配設位11゛)”との間に形成し、これらの小共通
電極上お」:ひ発熱抵抗体列ど集積回路チップとを個別
に接続する個別電極上に発熱抵抗体配列方向に?1)っ
て帯状の絶縁膜を形成し、この絶縁膜」二にバイアホー
ルを通して発熱抵抗体列に対し同一の側にある小共通電
極どうしを接続する大共通市極を形成したことを特徴と
するザーマルヘッド。
(1) An integrated circuit chip in which a row of heat generating resistors is arranged approximately in the center of the substrate, and drive Sh circuits and control circuits for driving the heat generating resistors individually are arranged in predetermined groups on both sides. Alternately distributed arrangement r1: In a thermal head made of A small common electrode is formed between the resistor array and the integrated circuit chip arrangement position (11)", and heat is generated on the individual electrodes that individually connect the heat generating resistor array and the integrated circuit chip. In the direction of resistor arrangement? 1) A band-shaped insulating film is formed, and a large common electrode is formed in this insulating film to connect the small common electrodes on the same side with respect to the heating resistor array through via holes. Thermal head.
(2)絶脈般は、ポリイミドワニスを塗布硬化させたも
のであることを特徴とする特許範囲第1項記載のザーマ
ルヘソド。
(2) The thermal hesode according to item 1 of the patent scope, characterized in that the coating is made by coating and curing polyimide varnish.
JP19010682A 1982-10-29 1982-10-29 Thermal head Pending JPS5979776A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19010682A JPS5979776A (en) 1982-10-29 1982-10-29 Thermal head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19010682A JPS5979776A (en) 1982-10-29 1982-10-29 Thermal head

Publications (1)

Publication Number Publication Date
JPS5979776A true JPS5979776A (en) 1984-05-09

Family

ID=16252471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19010682A Pending JPS5979776A (en) 1982-10-29 1982-10-29 Thermal head

Country Status (1)

Country Link
JP (1) JPS5979776A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331143A (en) * 1976-09-03 1978-03-24 Matsushita Electric Ind Co Ltd Thermal recording head
JPS57105367A (en) * 1980-12-24 1982-06-30 Ricoh Co Ltd Thermal head

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5331143A (en) * 1976-09-03 1978-03-24 Matsushita Electric Ind Co Ltd Thermal recording head
JPS57105367A (en) * 1980-12-24 1982-06-30 Ricoh Co Ltd Thermal head

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