JPS5979491A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain a high degree of integration and a high-speed operation for a semiconductor IC device by providing the 1st vertical ROM array which is precharged and discharged in the 1st and 2nd timing cycles respectively and the 2nd vertical ROM array which is discharged and precharged in said 1st and 2nd timing cycles respectively. CONSTITUTION:When a timing signal phip is set at an ''L'', a memory array ROM 1 is precharged. Then a timing signal phipd of a decoder DCR1 is set at the ''L'' in the first half cycle of the ''L'' of the signal phip to perform a precharging. A circuit FF1 fetches an address signal AD by the signal phipd. When the signal phip is set at an ''H'', the ROM1 is discharged to read out the storage information of the FF1. This read-out signal is sampled by a timing signal phis. So is with a memory array ROM2. Therefore the read-out signals are successively obtained synchronously with sampling timing signals phis and phis' in terms of an output OUT. Then the reading is apparently performed for each half cycle of the timing signal.

Description

[Detailed description of the invention] This invention 11, left ((type ROM (read only)
Concerning the ``1''-conductor collector circuit device including the following.

Conventionally, 1. MOSFF as a key element,
T (lf3 edge gate type field effect 1-transistor) is connected in series (K1 (type)) to form a rear array Jr (K
t# Q2 ROkl is known. 1-Memory information is written 2) in the MOS FrE as the memory 4a each time it is formed into a disolete type or an enhancement type depending on the settings in the manufacturing mask.

Vertical ROM read operation ``(Yo, the serial MOS I'' including that output I)
Precharge is performed on ゛, and then ゛ is serially connected to the MOS.
The output node is R'I-1-1 through F E 'r.
・It is done by the movement of Tainaminok whether or not it will be attacked.
Ru.

Therefore, as the M capacity increases, the number of Ni OS F Fi 'r'' in the P'r column form increases,
- Since the time required for recharging, discharging, and I.-- is lt, < i, the read operation becomes slow.

Therefore, by dividing the memory array, it may be possible to divide the number of serial MOS FETs to shorten the precharge and discharge times. However, in this case, along with the division, a wasteful blank space is created between the nozzle arrays, and the number of peripheral circuits increases, resulting in the problem of increasing the size of the semiconductor. arise.

The first object of this invention is to integrate each device with Itffi type ROM type metal 0M conductor integration, which can realize high integration and high speed operation.

111 objects of the invention will become clear from the following description and drawings.

This invention will be explained below with reference to R'P 2111 along with examples.

FIG. 1 shows a block diagram of an embodiment of an i9 vertical ROM to which the present invention is applied.

These three examples of vertical ROMs are used, but are not particularly limited, to construct a known LA (programmable logic array).

In the same figure, the ROM array includes ROMI and ROM
It is divided into two parts like 2. These memory arrays I'?
OM1. Although not particularly limited, ROM2 is configured to be a precharge MOSFET using a p-chi tunnel Mo5FET.
ET is configured, and the O5FET between n channels serves as a storage MOSFET and a dissipation MOS
OS F E 1' is configured and these MOS F
There is a case in which ET is connected to 1 in series (vertical type) to form one column. , vertical RO like two
Since the specific circuit configuration of M is publicly known, l'! A detailed circuit explanation will be omitted. Real array ROM in Gorera no No
1. The decoder circuit DCR1,
l') CR2 is provided. Then, in order to supply the address signal ΔD in response to the Guinaminok operation, a knob circuit 1'+knob circuit F that takes in the address signal ΔD is provided.
F1. l”F2 is provided.

Also, ``Second Memory Ytz IROM'', RO
The readout output signal from M2 is the sampling signal φS.

The output of φS” is zumbling amplified by the amplifier circuit Δ1.Δ2 and the output of 1η is 0 [
Supplied to J'r.

In this example, the reading 7. In other words, in order to perform the precharge operation and the case operation IjS well, the memory arrays ROM I and ROM 2 are complementary to each other. A timing signal 41 is supplied to one memory array ROM 1 to control the precharge and discharge operations.
The other Noes'/Ray ROM 2 has Impark IV.
A timing signal φp which is inverted by ζ is supplied.

In this way, in order to supply 411 input signals corresponding to the t1 timing signals φp5 and φp, the decoder IJCRl is provided with the input and r mink signals for the t1 timing signal φp5 to φp. Saeψρd is supplied, and de:J
-Da I) C[? 2 is supplied with a timing signal φpd'.

The timing signals φpd and φDd” are
2nd Furinogufu l:+7-1bu path FF1. L7゛ζ)) is used as the operation timing signal of FF2.

・This ';'j: The operation of the hiF example circuit is shown in the timing diagram of Figure 2. ! 3 It becomes clear.

;t 4 When φp is 11 bells, the memory r1 (ROM1 is precharged. Therefore,
Sea's j'l' l/Sudeni! - Decoder that forms a decoder 1) CRI evening/timing signal φpdl;
7 levels and the bridge's operating force was reduced.

With this evening/timing signal φpd, Furinobuso! l knob times +ts +rF1 takes in one address signal ΔI. Then, when the evening signal (shi~φd) is high l/・-le (,1 na-, zo, -), the memory array RO
MI's de(suf-ya-ji) was started, and the above-mentioned Furinobuso I-1 Nog times 1? A F T' I was taken in, but the address signal (♂C) was read out. This read signal number, 1.1-recorded, is linked by the timing signal φ5, which is generated at a predetermined interval of the high-level signal 11' of φp. Output.

On the other hand, the above timing signal φp&)l just turns A J1 station φl
'J makes a big move '1': Suj' 1
．．・1') N0N12 is the memory array I1G OF mentioned above.
/+ + and (, 11 It operates by reverse timing log cutting. -4', f straw, Juki timing f timing belief φp makes no'l:υ''/. ′
When C is present, the timing signal -φ■) becomes high level, and the No. 8 rear L... , Rime 1: Su)' When the I/I 1-in OMI is being set up, the evening/f timing signal φp is at the 11 level and the
,, 71. ,! i) IJ-2'L, IRO
M 20) 7' Lidjiage fiwa-l'C Ibi.

Guinaminoku movement like this (met, ′(, its de:
1-da l) The timing signal φ11cI' of CR2 and the rimbling timing signal are φS' as 1-da l)
l no yo 1 i! It is set with the JL series.

Shibuka, "c': Output Ot, J When viewed from T, Zumbling 3' f Sng (+'+ BegφS, φ
In synchronization with S′, afl r? j out believe 1
η, apparent ”-timing (r'j ”'3φpi
-p) can be read every half cycle of line).

This '-t': h; shout 5 ri ni 17 (l, Taiki 1.
Even when increasing the capacity, the memory 'j' L/I is reduced to the minimum 2
Since it can be suppressed to division, it is possible to realize a high-density blue circuit, and also to achieve
”, it is also possible to increase the speed of the convexity.

G-ta-! If the memory array is configured using CMOS times]?, 3 as shown in the figure below, the memory array will not consume DC current, resulting in lower power consumption.-1-
It will be beneficial.

This invention is not limited to the n;1 embodiment.

If the memory array divided into two is made into a tree, 9 [blank]
For example, 1 timing is 1774 laps! It is possible to further increase the speed by using two memory arrays, IQ-J'→ra・υ and ψNi.

In addition, for this purpose, the tying system for peripheral circuits (;
be.

This invention is based on the above P1. L for eight? Y′)tQ−JruΔ
N D, L, I, ○R array, various decoding J + times 1
It can be widely used such as 1X+.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the vertical type RSN1 to which the present invention is applied, and FIG. .

Claims (1)

[Claims] Precharging is performed in the timing period of 1, fr; A second battery in which discharge is performed during the Nori/timing cycle and precharge is performed during the second evening/timing cycle.
It is characterized by containing an XIy type ROM array f.
'-717 body 11-J♂ ([cell 1? & device. 2,"1 note 1? OM array and its peripheral circuit are 0M0
Q! Is it the bottom of the groove by 8 times 118? ? Sign 611.1 '1lli? Is the semiconductor described in item 1 the scope of the request? One repair/device at a time. 3. Claim 1 or WS characterized in that the L storage OM array constitutes a PTA.
21. Semiconductor integrated circuit device as described in item 21.