JPS5975718A - Transistor switching circuit - Google Patents

Transistor switching circuit

Info

Publication number
JPS5975718A
JPS5975718A JP18604782A JP18604782A JPS5975718A JP S5975718 A JPS5975718 A JP S5975718A JP 18604782 A JP18604782 A JP 18604782A JP 18604782 A JP18604782 A JP 18604782A JP S5975718 A JPS5975718 A JP S5975718A
Authority
JP
Japan
Prior art keywords
transistor
resistance
sat
collector
hfe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18604782A
Other languages
Japanese (ja)
Inventor
Tadao Sukai
須貝 忠雄
Masaki Shikatani
鹿谷 正木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stanley Electric Co Ltd
Original Assignee
Stanley Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stanley Electric Co Ltd filed Critical Stanley Electric Co Ltd
Priority to JP18604782A priority Critical patent/JPS5975718A/en
Publication of JPS5975718A publication Critical patent/JPS5975718A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce loss during saturation and to prevent an element from breaking down owing to abnormal heating by connecting a resistance with a desired value to the collector of a TR bipolar TR connected to an MOSTR field effect TR on Darlington basis. CONSTITUTION:The resistance Rc (with a resistance value Rc) is added between the collector electrode Co of the transistor (TR) Q2 and the drain electrode D of the MOSTRQ1. Thus, the resistance Rc having the value close to Ron/hfe where Ron is the ON resistance of the MOSTRQ1 and hfe is the current amplification factor of the TRQ2 is inserted as shown in a figure to supply a base current IB proportional to a collector current IC, and the TRQ2 is saturated sufficiently to obtain a small saturation voltage VCE(sat). The loss during saturation is VCE(sat).Ic, so it is preferable that the saturation voltage VCE(sat) is extremely small.

Description

【発明の詳細な説明】 この発明は、モス電界効果トランジスタ(以下MO8)
ランジスタと云う)とバイポーラトランジスタ(以下ト
ランジスタと云う)のダーリントン接続において、スイ
ッチングモードで使用する場合の異常発熱を防止したト
ランジスタスイッチング回路に関する。
DETAILED DESCRIPTION OF THE INVENTION This invention relates to a MOS field effect transistor (hereinafter referred to as MO8).
This invention relates to a transistor switching circuit that prevents abnormal heat generation when used in switching mode in a Darlington connection of a transistor (hereinafter referred to as a transistor) and a bipolar transistor (hereinafter referred to as a transistor).

従来のこの種の回路は第1図に示すように、MO8I−
ランジスタQ、とトランジスタQ、のダーリントン接続
において、MOS)ランジスタQ。
The conventional circuit of this type is MO8I- as shown in Figure 1.
In the Darlington connection of transistor Q and transistor Q, MOS) transistor Q.

のゲートGとトランジスタQ2のエミッタの間にバイア
スを力え、トランジスタQ、のコレクタ側端子Cとエミ
ッタ側端子E間に駆動電圧を加えてスイッチング動作を
させている。
A bias is applied between the gate G of the transistor Q2 and the emitter of the transistor Q2, and a driving voltage is applied between the collector side terminal C and the emitter side terminal E of the transistor Q, thereby performing a switching operation.

このような従来の回路では、スイッチ特性、駆動電力の
点でよいが、トランジスタQ2のコレクターエミッタ間
飽和電圧VCB (sat )は、コレクタ電流Icが
増大すれば同様に増大して飽和時の損−失P□H−Vc
E(sat’) x i cは犬となり異常発熱の原因
となる欠点があった。
Although such a conventional circuit has good switching characteristics and drive power, the collector-emitter saturation voltage VCB (sat) of the transistor Q2 increases as the collector current Ic increases, resulting in loss at saturation. Missing P□H-Vc
E(sat') x i c had the disadvantage of becoming a dog and causing abnormal fever.

すなわち、第1図の等価回路を示す第2図によってその
理由を説明する。ここでMOS)ランジスタ(11の各
チャンネル間の接合容剛は無視して考える。
That is, the reason will be explained with reference to FIG. 2 showing the equivalent circuit of FIG. 1. Here, the junction stiffness between each channel of the MOS transistor (11) is ignored.

第2図において、トランジスタQ2のコレクターエミッ
タ間の飽和電圧をVcE(sat)と1〜て、Ron・
・・・・・・・・MOS)ランジスタのドレイン−ソー
ス間負荷(ON)時の抵抗 Ic・・・・・・・・・トランジスタのコレクタ電流V
IIE・・・・・・・・トランジスタのペース・エミッ
タ間電圧 hfe・・・・・・・・・トランジスタの電流増幅率I
Iu  ・・・・・・・・・トランジスタのベース電流
とすれば、 VCE(sat)=1(、on4B−)−VBE−・・
・−−−−−−・tl)1 B = IC/h f e
       ・= −−−12)が成立し、 +11
 、 +21式よりVCE (sat )= )もon
 ・ :(二!−+ VBE −−−+3)hfe が成立する。
In FIG. 2, let the collector-emitter saturation voltage of transistor Q2 be VcE (sat) and 1 to Ron.
・・・・・・・・・MOS)Resistance Ic when transistor drain-source load (ON)・・・・・・Collector current V of transistor
IIE・・・・・・Transistor pace-emitter voltage hfe・・・・・・Transistor current amplification factor I
Iu......If it is the base current of the transistor, then VCE(sat)=1(,on4B-)-VBE-...
・------・tl) 1 B = IC/h f e
・= −−−12) is established, +11
, From formula +21, VCE (sat)= ) is also on
・ :(2!-+VBE ---+3)hfe holds true.

(3)式はトランジスタQ2の飽和電圧VCE(Sat
)がコレクタ電流Icが増大すれば同様に増大すること
を示している。従って、飽和時の損失P□nは、VcE
 (sat )・Icであるから、これに比例してスイ
ッチング回路が発熱する。
Equation (3) is the saturation voltage VCE (Sat
) indicates that if the collector current Ic increases, it similarly increases. Therefore, the loss P□n at saturation is VcE
(sat)·Ic, the switching circuit generates heat in proportion to this.

この発熱の原因である飽和時の損失Ponを少しでも小
さくする方法として、電流増幅率hfeを大きくするこ
とが考えられるが、根本的な解決方法ではない。
Increasing the current amplification factor hfe may be considered as a way to reduce the loss Pon at saturation, which is the cause of this heat generation, as much as possible, but this is not a fundamental solution.

この発明は、叙上の問題点に着目してなされたもので、
MOS)ランジスタとトランジスタのダーリントン接続
において、トランジスタのコレクタに所望の値の抵抗を
接続することによって、スイッチング回路の飽和時の損
失を小さくシ、極力発熱を押え、この種スイッチング回
路の良好なスイッチング特性、低駆動電力等の性質を損
うことなく異状発熱によるスイッチング回路の素子の破
壊全防止したトランジスタ・スイッチング回路を提供す
ること全目的とする。
This invention was made by focusing on the problems mentioned above.
In the Darlington connection between a transistor and a transistor (MOS), by connecting a resistor of the desired value to the collector of the transistor, the loss at saturation of the switching circuit is minimized, heat generation is suppressed as much as possible, and good switching characteristics of this type of switching circuit are achieved. The object of the present invention is to provide a transistor switching circuit which completely prevents destruction of switching circuit elements due to abnormal heat generation without impairing properties such as low driving power.

以下、この発明の実施例忙第3図以下に基いて説明する
Embodiments of the present invention will be described below with reference to FIG. 3 and subsequent figures.

上述の各式(11、(21、(31より、飽和電圧VC
E(sat)を下げるためには、コレクタ電流に比例し
たペース電流LB−j’なわち、Ib=IC/hfeな
る状態が常に維持されなければならない。つまり、(3
)式におけるMOSトランジスタのドレイン−ソース間
ON抵抗ROnの影醤が無くなる様に回路を構成すれば
よい。
From each of the above equations (11, (21, (31), the saturation voltage VC
In order to lower E(sat), a pace current LB-j' proportional to the collector current, that is, a state where Ib=IC/hfe must be maintained at all times. In other words, (3
) The circuit may be configured so that the influence of the drain-source ON resistance ROn of the MOS transistor in the equation is eliminated.

第3図において、第1図と同一機能で同一物については
説明を一部省略する。
In FIG. 3, descriptions of parts that have the same functions and are the same as those in FIG. 1 will be omitted.

第3図の回路と、第1図の回路との基本的な違いはトラ
ンジスタQ2のコレクタ電極coとMOSトランジスタ
Q、のドレイン電極しの間に抵抗Rc(抵抗値も同符号
で示す)を附加したものである。
The basic difference between the circuit in Figure 3 and the circuit in Figure 1 is that a resistor Rc (resistance value is also indicated by the same symbol) is added between the collector electrode co of the transistor Q2 and the drain electrode of the MOS transistor Q. This is what I did.

第3図の回路の等師回路は第4図によって示され1作用
を、数式を参照して説明すると、第4図では、(4)式
乃至(111式が成立する。
The isostatic circuit of the circuit shown in FIG. 3 is shown in FIG. 4, and its operation will be explained with reference to mathematical formulas. In FIG. 4, formulas (4) to (111) hold true.

Ic 1B=葭      ・・・・・・・・・・・・・・・
・・・・・・・・・(4)113= Vc−Vnn  
   、、、 、、、 、、、 、、、 、、、 、、
、 、、、 、、、(5)1もon Vc= lもC・I C−)VeB(sat)    
 −−−−+6)(6)式を(5)式に代入して IB=□□□呂枯旧旬川づ肌 ・用・・・・(7)(4
)式ケ(7)式に代入して整理すれば■8ic  (R
C−Ic+VcB(sat) )−VT3E−肩τ−。
Ic 1B=Yoshi ・・・・・・・・・・・・・・・
・・・・・・・・・(4)113=Vc−Vnn
, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,
, , , , , (5) 1 is also on Vc= l is also C・I C-)VeB(sat)
−−−−+6) Substituting equation (6) into equation (5), IB=
) equation (7) and organize it, we get ■8ic (R
C-Ic+VcB(sat))-VT3E-shoulder τ-.

。       −+8) Rc−Ic+VcE(sat ) = ・4“υ1′+
yBE1fe 0n−IC ILC−IC==+(VBE−VCE(sat) )こ
こで、(VBE −VcFi(sat )% 0とずれ
ばac、・I C、L’on φI C hfe Ron 従って、RCL、11fe        ・・・・・
・・・・・・・(9)(9)式の結果を(7)式に代入
すれば。
. -+8) Rc-Ic+VcE(sat) = ・4"υ1'+
yBE1fe 0n-IC ILC-IC==+(VBE-VCE(sat)) Here, (VBE-VcFi(sat)%) If deviated from 0, ac, ・I C, L'on φI C hfe Ron Therefore, RCL, 11fe...
......(9) Substituting the result of equation (9) into equation (7).

■、:■もon/hfe −1c+vcE(sat  
−VBE 、、、o。
■, :■ is also on/hfe -1c+vcE(sat
-VBE,,,o.

Ron VCI;’、 (5at)−VnE=oとすれば、00
式は■、t<、on−遣一 ”Ron−hfe 従って  、B−Ic−・・・・・・・・・・・・・・
・(lI+fe (9)式で示される値の抵抗Rci)ランジスタQ。
Ron VCI;', (5at)-VnE=o, then 00
The formula is ■, t<, on-Kenichi”Ron-hfe Therefore, B-Ic-・・・・・・・・・・・・・・・
・(lI+fe Resistance Rci with a value shown by equation (9)) A transistor Q.

のコレクタCoとMOSトランジスタQ、のドレインD
の間に挿入することにより、ペース電a I Eはコレ
クタ電流ICに比例しだ値のものが供給されることにな
り、トランジスタQ2は十分飽和し。
collector Co and drain D of MOS transistor Q.
By inserting the pace electrode between them, a pace electrode aIE having a value proportional to the collector current IC is supplied, and the transistor Q2 is sufficiently saturated.

小さな飽和電圧Vc+v (sat )が得られること
になる。
A small saturation voltage Vc+v (sat) will be obtained.

そこで、第4図における飽和時の損失POnはPon=
VCB(sat)−ICで必るがら飽和電圧VCE(s
aが極力小さいことが望ましいが、第3図の回路(等価
回路第4図)では小さくできる。例えばMOSトランジ
スタQ、のON抵抗F(onを1Ωとし、トランジスタ
Q2の電流増幅率hfeを20とすれば、挿入する抵抗
)<Cの抵抗値RcはRc=lもon/hfe=IQ/
2O−=0.0.5Ωとなり、抵抗値が小さいだめ抵抗
Rcでの発熱は小さく押えられる。しかし抵抗Rcが大
きくなるとこの発熱は大きくなってしまう。
Therefore, the loss POn at saturation in Fig. 4 is Pon=
VCB (sat) - IC necessarily has a saturation voltage VCE (s
Although it is desirable that a be as small as possible, it can be made small in the circuit shown in FIG. 3 (equivalent circuit shown in FIG. 4). For example, the ON resistance F of the MOS transistor Q (if ON is 1Ω and the current amplification factor hfe of the transistor Q2 is 20, the resistance to be inserted) < the resistance value Rc of C is Rc=l is also on/hfe=IQ/
2O-=0.0.5Ω, and the heat generated by the resistor Rc, which has a small resistance value, can be suppressed to a small level. However, as the resistance Rc increases, this heat generation increases.

そこで、この場合にこの発熱を防止するには、トランジ
スタの電流増幅率hfeを太きくするため、第5図に示
す他の実施例のように第3図におけるトランジスタQ2
の代シにダーリントン接続されたトランジスタ(コ3と
トランジスタQ4と’i1、個のトランジスタと考え、
この場合の抵抗RCは B C:=  1(′o n hfe、 X hfe2   °−°−= °aδ但 
hfe 、はトランジスタQ3の電流増幅率>    
 h fe・fd″2″′″pQ、(7)“l増幅率で
ある。
Therefore, in order to prevent this heat generation in this case, in order to increase the current amplification factor hfe of the transistor, the transistor Q2 in FIG.
Transistors (co3, transistors Q4 and 'i1, which are Darlington connected to
The resistance RC in this case is B C:= 1('o n hfe, X hfe2 °−°−= °aδ
hfe is the current amplification factor of transistor Q3>
h fe·fd″2″″pQ, (7) “l amplification factor.

02式によって抵抗ReO値は極めて小さくなり、抵抗
Heによる電力損失を減少することができる。
By formula 02, the resistance ReO value becomes extremely small, and the power loss due to the resistance He can be reduced.

第3図の回路での実際の例を下記に示すと、Ic=15
A 、 VcB(5at)= 1.5V 、 hfe=
20 (MIN)を用い、MOSトランジスタQI と
してIもon=lj3Ω(MAX)  抵抗Re=0.
20の条件において、抵抗Hcの有無にょp、次の様な
効果が得られた。
An actual example of the circuit shown in Figure 3 is shown below: Ic=15
A, VcB(5at)=1.5V, hfe=
20 (MIN), and as a MOS transistor QI, I is also on=lj3Ω(MAX), and resistance Re=0.
Under 20 conditions, the following effects were obtained depending on the presence or absence of resistance Hc.

但し IC=12Aの場合 上記のように、0,2Ωの抵わEをトランジスタQ2の
コレクタに接続してもスイッチング特性にはほとんど影
響がないことが確認された。
However, when IC=12A, as mentioned above, it was confirmed that connecting the 0.2Ω resistor E to the collector of the transistor Q2 has almost no effect on the switching characteristics.

すなわち、従来のMO8トランジスタとバイポーラトラ
ンジスタとのダーリントン接続したスイッチング回路は
、トランジスタの電句蓄積効果(ストレージタイム)が
なく、駆動電力は極めて小さくで良いので、大電力トラ
ンジスタを駆動する場合等に有効な手段であるが、異常
発熱を起しやすいという欠点があったのをスイッチング
特性を低下させることなくこの欠点を除去することがで
きる。
In other words, the conventional Darlington-connected switching circuit of an MO8 transistor and a bipolar transistor has no transistor storage effect (storage time) and requires very little driving power, so it is effective when driving high-power transistors. Although this method has the disadvantage of being prone to abnormal heat generation, it is possible to eliminate this disadvantage without degrading the switching characteristics.

以」二述べたように、この発明によれば、モス電界効果
トランジスタとダーリントン接続されたバイポーラトラ
ンジスタのコレクタ側に適性な抵抗を挿入することによ
って、スイッチング回路の飽和時の損失を極力小さくシ
、シかもスイッチング特性を損なわないように構成しだ
から、スイッチング特性がよく、かつ異常発熱を防止し
たスイッチング回路が得られ、放電加工機用電源、モー
タコントロール、スイッチングレギュレータ用のスイッ
チング回路として信頼性のある好適なものが得られる。
As described above, according to the present invention, by inserting an appropriate resistor on the collector side of the bipolar transistor connected to the MOS field effect transistor and Darlington, the loss at saturation of the switching circuit can be minimized. Since the structure is designed so as not to impair the switching characteristics, a switching circuit with good switching characteristics and prevention of abnormal heat generation can be obtained, making it reliable as a switching circuit for electrical discharge machine power supplies, motor controls, and switching regulators. A suitable one can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来のトランジスタスイッチング回路を示す
回路図、第2図は、第1図の回路の等価回路図、第3図
は、この発明によるトランジスタスイッチング回路の一
実施例を示す回路図、第4図は、第3図の回路の等飢回
路図、第5図は、この発明による他の実施例を示す回路
図である。 Q、・・・・・・・・・モス電界効果トランジスタQ2
・・・・・・・・・バイポーラトランジスタRc・・・
・・・・・・抵抗 Ron・・・・・・・・・モス電界効果トランジスタの
負荷時の抵抗(+& hfe・・・・・・・・・バイポーラトランジスタの電
流増幅率
FIG. 1 is a circuit diagram showing a conventional transistor switching circuit, FIG. 2 is an equivalent circuit diagram of the circuit in FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of a transistor switching circuit according to the present invention. FIG. 4 is an equivalent circuit diagram of the circuit of FIG. 3, and FIG. 5 is a circuit diagram showing another embodiment according to the present invention. Q, MOS field effect transistor Q2
...Bipolar transistor Rc...
・・・・・・Resistance Ron・・・・・・Resistance at load of MOS field effect transistor (+ & hfe・・・・・・Current amplification factor of bipolar transistor

Claims (1)

【特許請求の範囲】[Claims] モス電界効果トランジスタとバイポーラトランジスタと
のダーリントン接続回路において、前記モスη」界効果
トランジスタのドレインと前記バイポーラトランジスタ
のコレクタとの間を、前記モス電界効果トランジスタの
ドレイン−ソース間の負荷時の抵抗値を前記バイポーラ
トランジスタの電流増幅率で除した値およびその近似値
の抵抗値の抵抗で接続したことを特徴とするトランジス
タスイッチング回路。
In a Darlington connection circuit of a MOS field effect transistor and a bipolar transistor, a resistance value under load between the drain and source of the MOS field effect transistor is connected between the drain of the MOS field effect transistor and the collector of the bipolar transistor. A transistor switching circuit, characterized in that the transistor switching circuit is connected to a resistor having a resistance value obtained by dividing the current amplification factor of the bipolar transistor by the current amplification factor of the bipolar transistor and an approximate value thereof.
JP18604782A 1982-10-25 1982-10-25 Transistor switching circuit Pending JPS5975718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18604782A JPS5975718A (en) 1982-10-25 1982-10-25 Transistor switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18604782A JPS5975718A (en) 1982-10-25 1982-10-25 Transistor switching circuit

Publications (1)

Publication Number Publication Date
JPS5975718A true JPS5975718A (en) 1984-04-28

Family

ID=16181465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18604782A Pending JPS5975718A (en) 1982-10-25 1982-10-25 Transistor switching circuit

Country Status (1)

Country Link
JP (1) JPS5975718A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62279711A (en) * 1986-05-28 1987-12-04 Fuji Electric Co Ltd Composite semiconductor device
JP2012253752A (en) * 2011-05-06 2012-12-20 Semiconductor Energy Lab Co Ltd Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226181A (en) * 1975-08-22 1977-02-26 Nippon Telegr & Teleph Corp <Ntt> Semi-conductor integrated circuit unit
JPS55928A (en) * 1978-06-17 1980-01-07 Nippon Signal Co Ltd Change delivering device in automatic selling machine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226181A (en) * 1975-08-22 1977-02-26 Nippon Telegr & Teleph Corp <Ntt> Semi-conductor integrated circuit unit
JPS55928A (en) * 1978-06-17 1980-01-07 Nippon Signal Co Ltd Change delivering device in automatic selling machine

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62279711A (en) * 1986-05-28 1987-12-04 Fuji Electric Co Ltd Composite semiconductor device
JPH0560690B2 (en) * 1986-05-28 1993-09-02 Fuji Electric Co Ltd
JP2012253752A (en) * 2011-05-06 2012-12-20 Semiconductor Energy Lab Co Ltd Semiconductor device

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