JPH027714A - Protection device for component when fault current flows - Google Patents

Protection device for component when fault current flows

Info

Publication number
JPH027714A
JPH027714A JP63156765A JP15676588A JPH027714A JP H027714 A JPH027714 A JP H027714A JP 63156765 A JP63156765 A JP 63156765A JP 15676588 A JP15676588 A JP 15676588A JP H027714 A JPH027714 A JP H027714A
Authority
JP
Japan
Prior art keywords
gate
emitter
voltage
diode
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63156765A
Other languages
Japanese (ja)
Inventor
Satoshi Ibori
敏 井堀
Shigeyuki Baba
繁之 馬場
Hiroshi Fujii
洋 藤井
Koji Kanbara
神原 孝次
Kenji Nanto
謙二 南藤
Ikuo Okajima
岡島 郁夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63156765A priority Critical patent/JPH027714A/en
Publication of JPH027714A publication Critical patent/JPH027714A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08128Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in composite switches

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  • Electronic Switches (AREA)

Abstract

PURPOSE:To improve the reliability of a component even at the time of flowing a faulty current such as short-circuiting a load by providing a circuit clamping a gate-emitter of the component in a way that the gate-emitter voltage does not exceed the absolute maximum rating of the component. CONSTITUTION:Constant voltage diodes ZD1, ZD2 are provided between the gate and emitter of an electrostatic induction type self extinction component 1 and a gate-emitter voltage VGE at fault current is clamped to the Zener voltage. The Zener voltage of the diode ZD1 is selected over the absolute maximum rating of the gate-emitter voltage of the component 1. Moreover, since the diode ZD2 is connected in series, it is required to select the Zener voltage of the diode ZD1 lower by the forward voltage drop of the diode ZD2. Thus, the gate-emitter voltage of the electrostatic induction type self extinction component is clamped to the specified voltage at fault current such short-circuit of load and the positive feedback effect of the component is prevented thereby suppressing the increase of current at the time of short-circuiting and improving the reliability of the component.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は静電誘導形自己消孤素子の保護に係り、特に素
子の異常電流時に好適な素子の保護装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the protection of electrostatic induction type self-extinguishing elements, and more particularly to a protection device for the element suitable for the occurrence of abnormal current in the element.

〔従来の技術〕[Conventional technology]

MOS−FETのゲート・ソース間にVC!サージ電圧
保護を目的としてツェナーを挿入する事については、三
菱MOS−FET/B1−MOSモジュー)Li (H
B9756  B  昭和62年1゜月)のPLOに記
載されている。
VC between the gate and source of MOS-FET! Regarding inserting a Zener for the purpose of surge voltage protection, please refer to Mitsubishi MOS-FET/B1-MOS module) Li (H
B9756 B (January 1988) described in the PLO.

一方、三菱電機株式会社発行のMOS−FETモジュー
ル駆動用ベースアンプ(TSM−203)のP4/4に
上記ツェナー電圧(20V)が明示されている。現状M
O8−FET、Bi−MO5゜1GBT等の素子のゲー
ト電圧の絶対最大定格は20vであるから素子のゲート
の静電破壊、サージ電圧の保護のみを行なうのであれば
上記ツェナー電圧は20V以上に選定する事が公知技術
でありMOS−ic等も全てこのしそうで設計されてし
かし、負荷短絡の様な異常電流が流れた場合。
On the other hand, the Zener voltage (20V) is specified in P4/4 of a base amplifier for driving a MOS-FET module (TSM-203) published by Mitsubishi Electric Corporation. Current situation M
The absolute maximum rating of the gate voltage of elements such as O8-FET and Bi-MO5゜1GBT is 20V, so if you only want to protect the gate of the element from electrostatic damage and surge voltage, select the Zener voltage above 20V. It is a known technology to do this, and all MOS-ICs are designed to do this, but if an abnormal current such as a load short circuit flows.

例えば1GBTのコレクタ・エミッタ間のdv/dtに
より各端子間の容量に従い分圧されゲート・エミッタ間
の電位が上昇してしまう。
For example, due to the dv/dt between the collector and emitter of a 1GBT, the voltage is divided according to the capacitance between each terminal, and the potential between the gate and emitter increases.

上記上昇分をΔ■とするとゲート・エミッタ間の電圧は
(15+Δv)■となりみかけ上オーバードライブされ
一種の正帰還現象を示し、コレクタ電流を成長させ主素
子の信頼性をおびやかす要因となる。
If the above increase is Δ■, the voltage between the gate and emitter becomes (15+Δv)■, which is apparently overdriven and exhibits a kind of positive feedback phenomenon, which causes the collector current to grow and threatens the reliability of the main element.

つまり主素子の短絡の様な動的な状態を考えればゲート
電圧の上昇分はOv以下にクランプする事が理想的であ
る。
In other words, considering dynamic conditions such as short-circuiting of the main element, it is ideal to clamp the increase in gate voltage to below Ov.

以上の様に負荷短絡の様な異常電流時においても主素子
の信頼性を向上させるには公知技術である静電破壊、サ
ージ電圧保護のみを目的とするツェナー電圧(〉ゲート
電圧の絶対最大定格値)では目的を達成する事は出来な
い。
As mentioned above, in order to improve the reliability of the main element even during abnormal currents such as load short circuits, Zener voltage (>absolute maximum rating of gate voltage) is used for the sole purpose of electrostatic damage and surge voltage protection. value) cannot achieve the purpose.

本発明の目的は上記負荷短絡等の異常電流時に発生する
ゲート・エミッタ間の電圧上昇をゲート電圧の絶対最大
定格値以下にクランプ出来る様にツェナー電圧を選定し
、短絡時の異常電流の成長上記目的は、静電誘導形自己
消孤素子のゲート・エミッタ間に並列に定電圧ダイオー
ドを挿入し、この定電圧ダイオードのツェナー電圧を素
子のゲートエミッタ間の絶対最大定格値以上にする事に
より異常電流時のゲート・エミッタ間の電圧上昇を制御
する事で達成される。
The purpose of the present invention is to select a Zener voltage so that the voltage rise between the gate and emitter that occurs during abnormal currents such as the above-mentioned load short circuit can be clamped to below the absolute maximum rated value of the gate voltage, and to suppress the abnormal current growth during short circuits. The purpose is to insert a constant voltage diode in parallel between the gate and emitter of a static induction type self-extinguishing element, and to make the Zener voltage of this constant voltage diode higher than the absolute maximum rated value between the gate and emitter of the element. This is achieved by controlling the voltage rise between the gate and emitter during current flow.

つまり素子のゲート・エミッタ間に、このゲート・エミ
ッタ間の電圧が、素子の絶対最大定格値以上には、なら
ないようにクランプする回路を入れる。
In other words, a circuit is installed between the gate and emitter of the device to clamp it so that the voltage between the gate and emitter does not exceed the absolute maximum rating of the device.

〔作用〕[Effect]

定電圧ダイオードは静電誘導形自己消孤素子の異常電流
時のゲート・エミッタ間の上昇をあらかじめ選定された
ツェナー電圧にクランプするように動作する。それによ
って、異常時にゲート・エミッタ間の電圧を必要以上に
増加する事がない為短絡時に異常な電流を大幅に制御で
きるので、素子の短絡耐量を強化でき素子の信頼性を一
段と向上できる。
The constant voltage diode operates to clamp the rise between the gate and emitter of the electrostatic induction type self-extinguishing element to a preselected Zener voltage when an abnormal current occurs. This prevents the voltage between the gate and emitter from increasing more than necessary in the event of an abnormality, making it possible to significantly control abnormal current in the event of a short circuit, thereby strengthening the short circuit tolerance of the device and further improving the reliability of the device.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図により説明するR1−
R4は抵抗、icはインバータ、PH・CELは低圧側
と高圧側を電気的に絶縁するフォトカプラ、Ql、Q2
はnpnトランジスタ、Q3はpnp)’ランジスタ、
1は主スイツチング素子である静電誘導形自己消孤素子
であり、Elは主素子1を順バイアスする為の定電圧電
源、E2は送バイアスする為の定電圧電源である。
Hereinafter, one embodiment of the present invention will be explained with reference to FIG.
R4 is a resistor, IC is an inverter, PH/CEL is a photocoupler that electrically isolates the low voltage side and high voltage side, Ql, Q2
is an npn transistor, Q3 is a pnp transistor,
1 is an electrostatic induction type self-extinguishing element which is a main switching element, El is a constant voltage power source for forward biasing the main element 1, and E2 is a constant voltage power source for forward biasing.

インバータicの入力制御信号に従い主スイツチング素
子1を駆動する最も簡単な回路構成図である。
It is the simplest circuit configuration diagram for driving the main switching element 1 according to the input control signal of the inverter IC.

上記1cの出力が”L″の場合には、フォトカプラPH
−CELがオンとなりトランジスタQ1、Q3がオフ状
態、トランジスタQ2がオン状態となって主素子1に正
のゲート電圧が印加され主素子1がオン状態となる。一
方、icの出力がIIHFIの場合にはフォトカプラP
H−CELがオフとなりトランジスタQ2のみがオフ状
態、トランジスタQ1、Q3がオン状態となって主素子
1に負のゲート電圧が印加され主素子1がオフ状態とな
る。
If the output of 1c above is “L”, the photocoupler PH
-CEL is turned on, transistors Q1 and Q3 are turned off, transistor Q2 is turned on, a positive gate voltage is applied to the main element 1, and the main element 1 is turned on. On the other hand, if the IC output is IIHFI, the photocoupler P
H-CEL is turned off, only transistor Q2 is turned off, transistors Q1 and Q3 are turned on, a negative gate voltage is applied to main element 1, and main element 1 is turned off.

このようにicの入力信号に従い主素子である静電誘導
形自己消孤索子1にオン・オフ状態のスイッチングを行
なわせる事が出来る。
In this manner, the electrostatic induction type self-extinguisher 1, which is the main element, can be switched between on and off states according to the input signal to the IC.

ここで何らかの要因で第7図(a)の如き異常電流■。At this point, due to some reason, an abnormal current ■ as shown in FIG. 7(a) occurs.

が流れた場合、主素子である静電誘導形自己消孤素子の
基本構造に起因するコレクタとグー80間の容量Cc、
、ゲートGとエミッタE間の容量CaEコレクタCとエ
ミッタ間の容量C0によりゲート・エミッタ間電圧■6
.が上昇する。
flows, the capacitance Cc between the collector and the goo 80 due to the basic structure of the electrostatic induction type self-extinguishing element which is the main element,
, the gate-emitter voltage ■6 due to the capacitance CaE between the gate G and the emitter E, and the capacitance C0 between the collector C and the emitter.
.. rises.

第6図に記載の如く静電誘導形自己消孤素子はそのゲー
ト・エミッタ間の電位v6ゆの大きさにより流し得るコ
レクタ電流■。が決定される。又このICはvagが高
い程大きくなる。
As shown in FIG. 6, an electrostatic induction type self-extinguishing element can flow a collector current depending on the magnitude of the potential v6 between its gate and emitter. is determined. Also, the higher the vag, the larger this IC becomes.

以上の如く静電誘導形自己消孤素子の場合、コレクタに
異常電流が流れると上記記載の如くゲート電圧V GH
が順バイアス用定電圧電源E1よりも上昇し正帰還がか
かった状態となり主素子はオーバードライブされ、異常
電流を成長させ主素子を劣化せしめてしまう。
As described above, in the case of an electrostatic induction type self-extinguishing element, when an abnormal current flows through the collector, the gate voltage V GH increases as described above.
becomes higher than the constant voltage power source E1 for forward bias, and positive feedback is applied, and the main element is overdriven, causing an abnormal current to grow and deteriorating the main element.

本発明は上記点に鑑みなされたものであり、第1図に記
載されている如く主素子のゲート・エミッタ間に並列に
定電圧ダイオードを具備する事により、上記異常電流時
のゲート・エミッタ間電圧■6、をこのツェナー電圧に
クランプする事を目的とする。つまりZDIのツェナー
電圧を素子1のゲート・エミッタ間の絶対最大定格値以
上にする。
The present invention has been made in view of the above points, and by providing a constant voltage diode in parallel between the gate and emitter of the main element as shown in FIG. The purpose is to clamp the voltage (6) to this Zener voltage. In other words, the Zener voltage of ZDI is set to be equal to or higher than the absolute maximum rated value between the gate and emitter of element 1.

なお図示の実施例ではZDIに対してツェナーダイオー
ドZD2が直列に接続しであるからこのZD2の順方向
電圧降下分だけZDIのツェナー電圧を低く選定する必
要が有る。
In the illustrated embodiment, since the Zener diode ZD2 is connected in series with ZDI, it is necessary to select the Zener voltage of ZDI as low as the forward voltage drop of ZD2.

本発明によれば第7図(b)に記載の如く、異常電流時
にゲート・エミッタ間電圧をクランプする事が出来る為
、主素子のコレクタ電流の成長を抑制する事が可能とな
り主素子の信頼性を更に向上できる。一方第2図から第
5図は本発明の他の実施例であり、その目的とする所は
上記第1図の実施効果と同様である。
According to the present invention, as shown in FIG. 7(b), it is possible to clamp the voltage between the gate and emitter when an abnormal current occurs, so it is possible to suppress the growth of the collector current of the main element, and the reliability of the main element is increased. You can further improve your sexuality. On the other hand, FIGS. 2 to 5 show other embodiments of the present invention, and the purpose thereof is the same as the implementation effect shown in FIG. 1 above.

第2図は、ZD2の代わりにダイオードD2を用い順バ
イアス時のみクランプした実施例である。
FIG. 2 shows an example in which a diode D2 is used instead of ZD2 and clamped only during forward bias.

第3図は、ダイオードD1により異常電流時のゲート・
エミッタ間電位Vatを定電圧電源E1にクランプし、
電流の成長を抑制するよう構成した実施例であり同様の
効果が得られる。
Figure 3 shows how the diode D1 provides gate control during abnormal current.
Clamping the emitter potential Vat to a constant voltage power supply E1,
This embodiment is configured to suppress the growth of current, and similar effects can be obtained.

又第4図、第5図はゲート・エミッタ間を低インピーダ
ンスにする為の実施例である。
Further, FIGS. 4 and 5 show embodiments for making the impedance between the gate and emitter low.

以上の実施例を適時組み合わせて併用しても本発明の目
的とする所の効果は同様である。
Even if the above-mentioned embodiments are appropriately combined and used together, the same effect as the object of the present invention is achieved.

又、本発明をMOS−F、ET、Bi−MOS。Further, the present invention can be applied to MOS-F, ET, Bi-MOS.

1GBT等のモジュール内に実装しても全く同様の効果
が得られる。
Exactly the same effect can be obtained even if it is implemented in a module such as 1GBT.

〔発明の効果〕 本発明によれば、負荷短絡のような異常電流時に静電誘
導形自己消孤素子のゲート・エミッタ間の電圧を規定の
電圧にクランプし、素子の正帰還効果を防止するなど短
絡時の電流成長を抑制でき素子の信頼性を一段と向上で
きるという効果がある。
[Effects of the Invention] According to the present invention, the voltage between the gate and emitter of the electrostatic induction type self-extinguishing element is clamped to a specified voltage at the time of an abnormal current such as a load short circuit, thereby preventing the positive feedback effect of the element. This has the effect of suppressing current growth during short circuits and further improving device reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のゲート回路、第2〜5図は
本発明の他の実施例のゲート回路、第6図は静電誘導形
自己消孤素子のVC!−I。特性、第7図(a)は本発
明未実施時の短絡特性、第7図(b)は本発明実施時の
短絡特性である。 R1−R5:抵抗:C1:コンデンサ; i、 c :
インバータ;PH−CEL:フォトカプラ;Q1〜Q3
:トランジスタ;El:順バイアス用定電圧電源;Di
、D2:ダイオード=E2:逆バイアス用定電圧電源;
C:コレクタ端子;ZDI、ZD2:定電正大;G:ゲ
ート端子;1:静電誘導形自己消孤素子;E:エミッタ
端子;vCア:コレクタ・エミッタ間電圧;VeE:ゲ
ート・エミッタ間電圧;IC:コレクタ電流;t:時間
;Cca:コレクタ・エミッタ間等価容量;Cca:コ
レクタ・ゲート間等価容量;CGE:ゲート・エミッタ
間等価容量 ′−1\ど 第 図 7グ 第 図 (b
FIG. 1 shows a gate circuit of one embodiment of the present invention, FIGS. 2 to 5 show gate circuits of other embodiments of the invention, and FIG. 6 shows a VC! -I. FIG. 7(a) shows the short-circuit characteristics when the present invention is not implemented, and FIG. 7(b) shows the short-circuit characteristics when the present invention is implemented. R1-R5: Resistance: C1: Capacitor; i, c:
Inverter; PH-CEL: Photocoupler; Q1~Q3
: Transistor; El: Forward bias constant voltage power supply; Di
, D2: diode = E2: constant voltage power supply for reverse bias;
C: Collector terminal; ZDI, ZD2: Constant voltage positive; G: Gate terminal; 1: Electrostatic induction type self-extinguishing element; E: Emitter terminal; vC: Collector-emitter voltage; VeE: Gate-emitter voltage ; IC: Collector current; t: Time; Cca: Collector-emitter equivalent capacitance; Cca: Collector-gate equivalent capacitance; CGE: Gate-emitter equivalent capacitance '-1\do Figure 7 (b)

Claims (1)

【特許請求の範囲】 1、静電誘導形自己消孤素子(以下主素子という)と前
記主素子を駆動する定電圧電源と入力された制御信号に
応じ開閉動作する制御用素子を介して前記定電圧を前記
主素子のゲートに印加するゲート回路からなる装置にお
いて、前記主素子のゲート・エミッタ間に並列に、逆直
列に接続された定電圧ダイオードを具備し、この定電圧
ダイオードのツェナー電圧を前記素子のゲート・エミッ
タ間の絶対最大定格値よりも低くしたことを特徴とする
異常電流時の素子の保護装置。 2、上記主素子のゲート端子と上記定電圧電源との間に
前記主素子ゲート端子がアノード側に、前記電源の正電
位側がカソード側となるようにダイオードD1を接続し
たことを特徴とする請求項第1項記載の異常電流時の素
子の保護装置。 3、前記ダイオードは順方向電圧ドロップの低いショッ
トキーバリアダイオードで構成した事を特徴とする請求
項第2項記載の異常電流時の素子の保護装置。 4、上記主素子のゲート・エミッタ間に並列に抵抗R5
を具備した事を特徴とする請求項第1項、第2項記載の
いずれか一方の異常電流時の素子の保護装置。 5、前記ゲート・エミッタ間の並列抵抗R5は数百オー
ム以下の低抵抗で構成した事を特徴とする請求項第4項
記載の異常電流時の素子の保護装置。 6、前記素子のゲート・エミッタ間に並列に低インピー
ダンスのコンデンサC1を具備した事を特徴とする請求
項第1項・第2項・第4項記載のうちのいずれか1つの
異常電流時の素子の保護装置。
[Claims] 1. The above-mentioned device is connected through an electrostatic induction type self-extinguishing element (hereinafter referred to as the main element), a constant voltage power supply for driving the main element, and a control element that opens and closes in response to an input control signal. A device comprising a gate circuit that applies a constant voltage to the gate of the main element, comprising a constant voltage diode connected in parallel and in anti-series between the gate and emitter of the main element, the Zener voltage of the constant voltage diode being A protection device for an element at the time of abnormal current, characterized in that the voltage is lower than the absolute maximum rated value between the gate and emitter of the element. 2. A diode D1 is connected between the gate terminal of the main element and the constant voltage power supply so that the main element gate terminal is on the anode side and the positive potential side of the power supply is on the cathode side. A protection device for an element at the time of abnormal current according to item 1. 3. The device for protecting elements during abnormal current according to claim 2, wherein the diode is a Schottky barrier diode with a low forward voltage drop. 4. A resistor R5 is connected in parallel between the gate and emitter of the above main element.
The device for protecting an element at the time of abnormal current according to any one of claims 1 and 2, characterized by comprising: 5. The protection device for an element at the time of abnormal current according to claim 4, characterized in that the parallel resistance R5 between the gate and emitter is constructed with a low resistance of several hundred ohms or less. 6. At the time of abnormal current according to any one of claims 1, 2, and 4, a low impedance capacitor C1 is provided in parallel between the gate and emitter of the element. Element protection device.
JP63156765A 1988-06-27 1988-06-27 Protection device for component when fault current flows Pending JPH027714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63156765A JPH027714A (en) 1988-06-27 1988-06-27 Protection device for component when fault current flows

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63156765A JPH027714A (en) 1988-06-27 1988-06-27 Protection device for component when fault current flows

Publications (1)

Publication Number Publication Date
JPH027714A true JPH027714A (en) 1990-01-11

Family

ID=15634824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63156765A Pending JPH027714A (en) 1988-06-27 1988-06-27 Protection device for component when fault current flows

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Cited By (9)

* Cited by examiner, † Cited by third party
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JP2007259067A (en) * 2006-03-23 2007-10-04 Denso Corp Semiconductor element drive circuit
JP2008043003A (en) * 2006-08-03 2008-02-21 Fuji Electric Systems Co Ltd Gate drive unit of voltage-driven type semiconductor element
JP2008070680A (en) * 2006-09-15 2008-03-27 Fuji Electric Device Technology Co Ltd Display driver
JP2008211721A (en) * 2007-02-28 2008-09-11 Fuji Electric Device Technology Co Ltd Display device drive circuit
WO2011033733A1 (en) * 2009-09-15 2011-03-24 三菱電機株式会社 Gate drive circuit
US8217704B2 (en) 2009-05-13 2012-07-10 Fuji Electric Co., Ltd. Gate drive device
JP2014093892A (en) * 2012-11-06 2014-05-19 Fuji Electric Co Ltd Driving device for voltage drive type semiconductor element
US9401705B2 (en) 2011-07-07 2016-07-26 Fuji Electric Co., Ltd. Gate driving device
JP2019058056A (en) * 2017-09-20 2019-04-11 同方威視技術股▲分▼有限公司 Protection circuit, vibration compensation circuit and power feeding circuit in solid pulse modulator

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007259067A (en) * 2006-03-23 2007-10-04 Denso Corp Semiconductor element drive circuit
JP2008043003A (en) * 2006-08-03 2008-02-21 Fuji Electric Systems Co Ltd Gate drive unit of voltage-driven type semiconductor element
JP2008070680A (en) * 2006-09-15 2008-03-27 Fuji Electric Device Technology Co Ltd Display driver
JP2008211721A (en) * 2007-02-28 2008-09-11 Fuji Electric Device Technology Co Ltd Display device drive circuit
US8217704B2 (en) 2009-05-13 2012-07-10 Fuji Electric Co., Ltd. Gate drive device
WO2011033733A1 (en) * 2009-09-15 2011-03-24 三菱電機株式会社 Gate drive circuit
JP5270761B2 (en) * 2009-09-15 2013-08-21 三菱電機株式会社 Gate drive circuit
US8519751B2 (en) 2009-09-15 2013-08-27 Mitsubishi Electric Corporation Gate drive circuit
US9401705B2 (en) 2011-07-07 2016-07-26 Fuji Electric Co., Ltd. Gate driving device
JP2014093892A (en) * 2012-11-06 2014-05-19 Fuji Electric Co Ltd Driving device for voltage drive type semiconductor element
JP2019058056A (en) * 2017-09-20 2019-04-11 同方威視技術股▲分▼有限公司 Protection circuit, vibration compensation circuit and power feeding circuit in solid pulse modulator
US11152932B2 (en) 2017-09-20 2021-10-19 Nuctech Company Limited Protection circuit, oscillation compensation circuit and power supply circuit in solid state pulse modulator

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