JPS5975711A - Tuning circuit of radio receiver - Google Patents

Abstract

PURPOSE:To improve the Q factor of selectivity characteristics and increase reception precision during channel selection, and to lower the Q factor and obtain high fidelity after the channel selection, by controlling a switching means provided to a tuning circuit by a muting control signal. CONSTITUTION:The output of the inverting circuit 12 of a muting driving circuit 19 is at a high level in the channel selection, i.e. when a synthesizer part is in an asynchronous state. Its signal is applied to the base of a transistor (TR) 23, which is turned off to prevent the influence of a resistance 50 upon the operation of the tuning circuit 16a. Namely, the Q factor of the tuning circuit 16a is decreased in the asynchronous state. When the synthesizer part is placed in a synchronous state after the channel selection is completed, the output of the inverting circuit of the driving circuit 19 falls to a level ''0'', so the TR23 turns on to exert the influence of the resistance upon the operation of the tuning circuit 16a. Consequently, the selectivity characteristics of the tuning circuit 16a deteriorates to improve sound quality.

Description

[Detailed description of the invention] (Application field) The present invention relates to a tuning circuit for a radio receiver.

In particular, the present invention relates to a tuning circuit for a digital synthesizer type radio receiver.

(Prior Art) Figure A1 is a block diagram showing an example of a synthesizer section of a digital synthesizer type c7) radio receiver.

In the figure, 1 is a reference frequency oscillator, 2 is a wave U and phase comparator, 3 is a low-pass filter, 4 is a voltage controlled oscillator, and 5
is a programmable frequency divider, and 60 is a synchronous control circuit.

As is well known, the synthesizer method is
Output frequency j of pressure controlled oscillator 4. is divided into (1/#) by the programmable frequency divider 5, and this signal is supplied to the frequency and phase comparator 2, where first, this supplied signal and the reference frequency fr from the reference frequency oscillator 1 are and the difference component is generated as a DC voltage.

Next, this DC voltage is supplied to the voltage-controlled oscillator 4 through the low-pass filter 3, and the output frequency f of the voltage-controlled oscillator 4 is determined by this voltage.

is controlled so that the relationship of (Equation 11) is satisfied.

fo=N - fr (11) In FIG. 1, the synchronization control circuit 6o greatly changes the value of the reciprocal (N) of the frequency division of the programmable frequency divider 5 for channel selection switching.

This is because it may not be possible to restore normal synchronization only with the functions of the frequency and phase comparator 2.

This was provided taking such cases into consideration.

That is, the synchronous control circuit 6o inputs signals from the programmable frequency divider 5 and the reference frequency oscillator 1, respectively, and when it is determined that the asynchronous state is present, the control signal is input to the voltage via either one of the control loops C116. It is sent to either the controlled oscillator 4 or the reference/frequency oscillator 1, thereby momentarily interrupting its output and working to bring the synchronization state (ft-='/-9)K closer.

By the way, in a bad pre-synchronization situation, the voltage controlled oscillator 4
The output frequency f. However, the superheterodyne receiver 1 described later
It serves as the output of the local oscillation circuit of the g-machine (hereinafter simply referred to as receiver).

Therefore, in the synchronized state, if the frequency of the received signal is 1, and the intermediate frequency is 8, then 1, for example, the current domestic frequency
In the M band, the relationship expressed by equation (2) holds true, and as a result, the broadcast at the frequency f is also received.

f=-4-1m...(2) On the other hand, in the asynchronous state, the relationship in equation (2) is not satisfied,
The receiver is therefore out of tune. In this state, the receiver emits noise as is often seen.

Figure 2 is a block diagram showing an example of a muting circuit for reducing noise in such an asynchronous state.

In FIG. 2, the output terminal of the no-log grammable frequency divider 5 is wired to the set power I of the flip-flop circuit 6, and the reset power K is wired.

The output end of the reference frequency oscillator 1 is connected.

Further, one input terminal of the tenth gate door is connected to the output Q of the flip-flop circuit 6, and the other input terminal of the Nant gate 7 is connected to the sM+JfJe set manual J
is connected to.

Furthermore, one input terminal of the second Nant gate 8 is connected to the flip-flop circuit 6. The other input terminal is connected to the output Q of the pre-distribution set.

In the circuit shown in FIG. 2, diodes 9 and 10 are connected to the output terminal of the first Nandt gate 7.

As shown in the figure, one input terminal of an AND circuit connected in series is connected, and the output terminal of the second Nant gate 8 is connected to the other input terminal of the AND circuit. . The flip-flop circuit 6sJ'r1, the second Nandt gate 7.8, the AND circuit, and the capacitor 11 described later constitute the synchronous control circuit 30 described above. In the circuit of FIG. 2, the connection point between the diode 9 and the diode 10, that is, the output terminal of the AND circuit, is connected to the base of the transistor 15 through the capacitor 11 for normal fVt and the inverting circuit 12, which are connected as shown in the figure. It is connected.

By the way, the collector C of the previous transistor 13 is connected to the audio line of the received transmission. For this purpose 1
As is well known, when a suitable bias is applied to base B, a forward voltage is applied between base B and 19721.

The impedance between the collector C and 19721 decreases, resulting in the audio signal being grounded. In other words, it becomes a muting state.

Next, the operation of the terminating circuit shown in FIG.
This will be explained in more detail with reference to FIGS.

The pulses supplied to the set inputs "J, S, and KK of the flip-flop circuit 6 are 1, for example, the 3rd pulse.
When synchronized as shown in the figure, the outputs Q and Q of this flip-flop circuit 6 become as shown in the figure. As a result, the outputs of the first and second Nant gates 7.8, ie, J? Q and -Q&'f, as shown in the figure, both are 1 level.

On the other hand, if the number of set pulses supplied to the reset manual power K of the flip-flop circuit 6 is greater (has a higher frequency) than the number of set pulses supplied to the set manual power J, as shown in FIG. When a plurality of reset pulses are supplied after being reset by a pulse and being set by a set pulse (asynchronous state fr~1/H"fo), this flip-flop circuit 6 Since the output Q, 7:i is as shown in Figure 4, the output J-Q of the first tend gate 7
holds +1 levels, but the output of the second Nantes gate 8 - η generates a pulse of 10 levels during one hour t.

Conversely, in an asynchronous state where the number of set pulses supplied to the set input JK is greater than the number of set pulses supplied to the reset manual K, the output J-Q of the Nant gate 7 of @1 is It generates a pulse force of 10 lbel and r4z.

By the way, in the synchronous state, E 5
In the transistor 160 base B! 1g of 0 lebel
Since the symbol is stamped, the transistor 13 is in an off state and does not perform a muting operation.

On the other hand, in the non-identical state, it is clear from 1 and here that 7
1 to 5, first or second Nando game - 1 to 7, 8 I
Since the output pulse of the OI level V is smoothed to a certain level (low level) by the capacitor 11,
By passing this signal through the inversion circuit 12, a high level signal 1g is applied to the base B of the transistor 13. As a result, the transistor 16 is turned on,
The miniting circuit performs a muting operation.

Note that the first and second Nant gates are used as control signals to momentarily interrupt either the reference frequency oscillator 1 or the voltage controlled oscillator 4 at the time of non-synchronization.

Figure 5 is a block diagram showing an example of a conventional digital synthesizer type radio receiver ('iI! machine). In the figure, the same parts and equivalent parts as in Figures i1# and 2 are designated by the same reference numerals. High frequency amplifier circuit, 15 is an intermediate frequency amplifier circuit, 16 is a tuning circuit, 17 is a detection circuit, 19 is a muting drive circuit, 20 is a low frequency amplifier circuit, 21 is a power amplifier circuit, 22 is a frequency conversion circuit, 51 is a speaker Note that the muting drive circuit 19 includes a second
Four circuits are included in the figure, indicated by dashed lines.

In FIG. 5, the received high frequency signal inputted to the high frequency amplification circuit 14 is amplified by the high frequency amplification circuit 14 and supplied to the one frequency conversion circuit 22. On the other hand, this frequency conversion circuit 22 receives the output frequency f of the voltage controlled oscillator 4 as a local oscillation circuit. is entered. Note that this output frequency f. As described above, is controlled in the synthesizer section so as to be synchronized with the reference frequency of the reference frequency oscillator 10.

Therefore, in order to receive broadcasts at the above frequency,
First, the reciprocal (CN) of the division ratio of the programmable frequency divider 5 is varied to obtain a predetermined output frequency f. It is clear that it is sufficient to stop this (N) when .

i.e. by doing it this way.

The frequency conversion circuit 22 outputs the output frequency h.

Next, this intermediate frequency is amplified in an intermediate frequency amplification circuit 15 to determine the selectivity characteristics of the receiver.
6 and is further demodulated into an audio signal by a detection circuit 17. This demodulated audio signal is sent to the low frequency amplifier circuit 20
The signal also passes through the power amplifier circuit 21 and is output from the speaker 61.

In addition, the muting drive circuit I? As described above, a high level signal is applied to the base B of the transistor 160 of the transistor 519 when the synthesizer section is in the asynchronous state, so the output of the detection circuit 17 is in the meeting state. On the other hand, when the synthesizer section is in a synchronized state, a signal of 10 levels is applied to the transistor 130 base EIIC, so the output of the detection circuit 17 directly passes through the low frequency amplification circuit 20 and the power amplification circuit 21 to the speaker 61.
It will also be output.

Incidentally, an auto scan stop signal for stopping the reciprocal (N) of the frequency division ratio of the programmable frequency divider 5 at a predetermined value can be obtained from the detection circuit 17.

That is, in the detection circuit 17, due to the selectivity characteristics of the tuning circuit 16, the level of the intermediate frequency M is at the expected level, that is, approximately the center frequency fi of the intermediate frequency M. (Usually 10.7M1iz for FM, usually 450KB'z for AM
) was investigated using a well-known method.

This is because a signal corresponding to the level is supplied to the programmable frequency divider 5.

To describe this more specifically, in the case of the AM band, the detection circuit 17 determines the expected level of the audio signal using a well-known method, and in the case of the FM band, the expected level of the carrier signal is determined. Then, signals corresponding to the respective levels are supplied to the programmable frequency divider 5.

Therefore, the auto scan is stopped (if issue is.

It can be seen that it depends on the selectivity characteristics of the tuning circuit 16. That is, when Q of the 1 selectivity characteristic is sharp, compared to when Q is dull, the expected level of the audio 1g or the carrier signal is detected even closer to the center frequency f1°. becomes. In other words, this means that
This means that it is possible to set the desired 11IL even more accurately, and this also means that the frequency accuracy of the received key signal can be set to the same as above.

However, from the point of view of fidelity, that is, sound quality, as is often said, it is desirable that the Q of the selectivity characteristic be dull. This is because the output of the detection circuit 17, that is, audio No. 9, naturally deteriorates in terms of electrical fidelity as the band becomes narrower.

Therefore, what can be said from the above points is as follows.

When selecting a channel, that is, when the receiver moves from an untuned state to a tuned state (the synthesizer section goes from an asynchronous state to a synchronous state), it is desirable that the selectivity characteristic of the tuning circuit 16 has a sharp Q.
After selecting the channel again.

That is, when the receiver 1Nflk is in a synchronized state (the synthesizer section is in a synchronized state), it is desirable that the Q is dull.

However, in conventional receivers, as is clear from FIG. 5, the selectivity characteristic Q of the same disease circuit 16 remains unchanged both during and after tuning. However, when attempting to improve the frequency accuracy of the receiver, the electrical fidelity of the 100th audio signal after one channel selection deteriorated.

Conversely, if the Q is made duller, the electrical fidelity of the audio signal after tuning is improved.

As a result of the above, a disadvantage arises in that the frequency accuracy of the receiver deteriorates.

[Purpose] In response to the contradictory demands mentioned above, an object of the present invention is to improve the frequency accuracy of the received signal by sharpening the Q of the selectivity characteristic at the time of channel selection, and to dull the Q after tuning. An object of the present invention is to provide a tuning circuit for a radio receiver that can improve the sound quality of the receiver.

(Summary) The feature of the present invention is that by controlling the switching means newly provided in the tuning circuit by using the I-100 which controls the minting operation of the Mieteink drive circuit,
Similarly, the newly provided resistor in the same circuit casts a shadow on the tuned circuit in the synchronous state, but has no effect in the asynchronous state.

(Example) Hereinafter, the present invention will be explained using the drawings.

FIG. 6 is a block diagram showing an embodiment of a digital synthesizer type radio 5j-'liJ having a tuning circuit according to the present invention. In this figure, the same parts and parts as in FIG. 5 are indicated by the same reference numerals. 16α is a tuning circuit, 23
is a transistor, and 50 is a resistor.

Regarding the sixth factor, when a channel is selected, that is, when the synthesizer section is in an asynchronous state, the output of the miniting drive circuit 190 and the inverting circuit 12 becomes high level, as is clear from the explanation of FIG.

In this embodiment, in this asynchronous state, this high level signal is applied to the pace of the transistor 26, and the transistor 26 is turned off.
The resistor 5B was made not to affect the operation of α.

That is, by doing this, in the asynchronous state (also in the minting state), the selectivity characteristic of the tuning circuit 16α can be made as shown in FIG. can be sharpened.

On the other hand, when the tuning is completed and the synthesizer section is in a synchronized state, in this embodiment, the minting drive circuit 1
Since the output of the inverting circuit 12 of No. 9 is 10 Lebel, no base voltage is applied to the transistor 23. Therefore, the transistor 25 is also turned on and the resistor 50 is turned on.
will affect the operation of the tuning circuit 16α. As a result, the selectivity characteristic of the tuning circuit 16α becomes as shown in FIG. That is, compared to the same characteristics in the asynchronous state, the Q is dull.

In addition, in the above explanation, the resistor 50 is set to 1 of the tuning circuit 16α.
On the next side, it is rarely connected in parallel to the C circuit via the transistor 23, but the present invention is not limited to this. That is, the tuning circuit 16
Of course, the resistor 50 may be connected in parallel to the other path of α and the cB path via the transistor 25.

(Effects) As is clear from the above explanation, the present invention is achieved by adding a relatively simple circuit.

When selecting a channel, the selectivity characteristics can be sharpened, and as a result, the frequency and frequency of the received signal can be increased, and after selecting a channel, the Q can be made pure. As a result, the sound quality of the receiver can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a synthesizer section of a radio receiver using a digital synthesizer method; 5.4 is a waveform diagram for explaining the operation of the synchronous control circuit 60 in FIG.
FIG. 6 is a block diagram showing an example of a conventional digital synthesizer radio receiver, FIG. 6 is a block diagram showing an embodiment of a digital synthesizer radio receiver having a tuning circuit according to the present invention, and FIGS. is the tuning circuit 1 in Figure 6.
FIG. 6 is a characteristic diagram for explaining selectivity characteristics of 6α. 12... Inverting circuit 15, 23... Transistor 15... Intermediate frequency increase circuit 16a... LFF1 tone circuit 1? ...Mute ink drive Ig path 30 ... Synchronous control circuit 50 ... Resistance agent patent attorney Hiroshi 1) Toshiyuki −−−−−−−−−−−
------0 erase 2 figure 4 dark figure 5 figure 4 depositwa figure tiO porridge δ figure

Claims (1)

[Claims] (1) A synchronous control circuit that is part of the synthesizer/izer section and outputs each number according to the synchronous state or asynchronous state of the synthesizer section, and a signal whose output from the synchronous control circuit corresponds to the asynchronous state. a minting drive circuit that operates to ground the tuned audio signal and not to ground the audio signal when the output of the synchronization control circuit is a signal corresponding to a synchronous state; Provided at the next stage of the intermediate frequency dovetail width circuit. and a tuning circuit that determines the Q of the intermediate station/wave selectivity characteristic that is the output of the intermediate chest amplifier circuit, wherein the tuning circuit is configured to have a switching means so that the Q of the selectivity characteristic thereof can be varied. and a resistor connected through the synchronous control circuit, and the output from the synchronous control circuit turns off the switching means when in the asynchronous state, and turns off the switching means when the synchronous control circuit is in the asynchronous state. l? Sharpen the Q of the selectivity characteristic of J path,
A tuning circuit for a radio receiver, characterized in that when in the synchronized state, J switching means is turned on to dull the Q.