JPS5975630A - Dry etching device - Google Patents

Dry etching device

Info

Publication number
JPS5975630A
JPS5975630A JP18701982A JP18701982A JPS5975630A JP S5975630 A JPS5975630 A JP S5975630A JP 18701982 A JP18701982 A JP 18701982A JP 18701982 A JP18701982 A JP 18701982A JP S5975630 A JPS5975630 A JP S5975630A
Authority
JP
Japan
Prior art keywords
electrode
upper electrode
lower electrode
semiconductor substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18701982A
Other languages
Japanese (ja)
Inventor
Seiji Sagawa
誠二 寒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18701982A priority Critical patent/JPS5975630A/en
Publication of JPS5975630A publication Critical patent/JPS5975630A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor

Abstract

PURPOSE:To increase an etching rate, and to maintain the uniformity of the distribution of the etching rate by specifying the ratio of a distance between a lower electrode and an upper electrode to the diameter of the upper electrode. CONSTITUTION:An upper electrode 2 and a lower electrode 3 are placed in parallel in a vacuum chamber 1 at the distance (d), a gas introducing port is formed to the upper section of the upper electrode 2, and a large number of gas outflow ports are formed to the surface opposite to the lower electrode 3. Exhaust ports are formed to the vaccuum chamber 1, and a semiconductor substrate 5 to be etched is placed on the lower electrode 3. An etching gas 4 is introduced from the upper section of the upper electrode 2, advances toward the semiconductor substrate 5 from a lower surface, and is discharged from the exhaust ports 6. When a high-frequency power supply 7 is connected to the lower section of the lower electrode 3, the upper electrode 2 is kept at ground potential and high-frequency power is applied, plasma is generated in the vacuum chamber 1, and the semiconductor substrate 5 is etched. When the diameter of the upper electrode 2 is made to be (g) and the distance between the upper electrode 2 and the lower electrode 3 (d) in such constitution, the uniformity of the etching rate is improved largely by bringing the ratio of g/d to 3.4 or less.

Description

【発明の詳細な説明】 本発明は平行平板電極枚葉型のドライエツチング装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel plate electrode single wafer type dry etching apparatus.

従来、半導体装置の製造、特に半導体基板にノくターン
を形成するのにドライエツチング装置が用いられてきた
。特に平行平板電極枚葉型ドライエツチング装置を用い
るリアクティブイオンエツチングは、再現性が良く、良
好なパターン全形成できる点で1&れている。
Conventionally, dry etching equipment has been used in the manufacture of semiconductor devices, particularly in forming notches in semiconductor substrates. In particular, reactive ion etching using a parallel plate electrode single-wafer type dry etching apparatus is superior in that it has good reproducibility and can form a complete pattern.

第1図は平行平板電極枚葉型ドライエツチング装置の一
例の断面図である。
FIG. 1 is a sectional view of an example of a parallel plate electrode single wafer type dry etching apparatus.

真空チャンバl内に上部電極2と下部141.極3とが
平行に距離dをおいて置かれる。上部電極2の上部には
ガス導入口があり”、上部電極2の下部電極3に対向す
る而にはガスの流出口が多数設けられる。真空チャンバ
ー1には排気口6が設けられる。下部α極3には被エツ
チング半導体基板5が載置される。エッチングガス4I
′i上部′鷹極2の上部から導入され、上部′RL極2
の下面から半導体基板5に向って進み、排気口6から排
出される。下部電極3の下部に高周波電源7を接続し、
上部電極2を接地電位に保ち、高周波電力を印加すると
真空チャンバl内にプラズマを生じ、半導体基板5がエ
ツチングされる。
An upper electrode 2 and a lower electrode 141. The poles 3 are placed parallel to each other at a distance d. There is a gas inlet in the upper part of the upper electrode 2, and many gas outlet ports are provided in the upper electrode 2 facing the lower electrode 3.The vacuum chamber 1 is provided with an exhaust port 6. A semiconductor substrate 5 to be etched is placed on the pole 3. Etching gas 4I
'i upper' Hawk pole 2 is introduced from the upper part, upper 'RL pole 2
The gas advances from the bottom surface toward the semiconductor substrate 5 and is discharged from the exhaust port 6 . A high frequency power source 7 is connected to the lower part of the lower electrode 3,
When the upper electrode 2 is kept at ground potential and high frequency power is applied, plasma is generated in the vacuum chamber 1, and the semiconductor substrate 5 is etched.

上記のドライエツチング装置において、エツチング速度
を増大させようとすると、エツチングの均一性が悪くな
る傾向がある。つまり、エッチング深さが半導体基板5
の場所により異なる度合が大きくなる欠点があった。半
導体基板5のエツチング速度の分布が15%以下である
ことが望ましいが、従来のドライエツチング装置ではそ
の達成は困難であり、均一性を良くしようとするとエツ
チング速度を低下させなければならず、作業効率が低下
するといつ欠点があった。
In the above-mentioned dry etching apparatus, when an attempt is made to increase the etching rate, the uniformity of etching tends to deteriorate. In other words, the etching depth is 5
The disadvantage was that the degree of variation was large depending on the location. It is desirable that the etching rate distribution of the semiconductor substrate 5 is 15% or less, but this is difficult to achieve with conventional dry etching equipment, and in order to improve the uniformity, the etching rate must be lowered, resulting in an increase in work efficiency. There were drawbacks when efficiency decreased.

本発明は上記欠点を除去し、エツチング速度を上げ、し
かもエツチング速度の分布の均一性を保つことのできる
ドライエツチング装置を提供するものである。
The present invention provides a dry etching apparatus which can eliminate the above-mentioned drawbacks, increase the etching rate, and maintain the uniformity of the etching rate distribution.

本発明のドライエツチング装置は、被エツチング基板を
載置する平板状の下部電極と、該下部電極にf行に対向
する平板状の上部電極とを内蔵する平行平板電極枚葉1
°ライエツチング装置において、前記下部電極と上部′
成極との1屯離dと前記上部電極の直径gとの比を3.
4以下としたことを特徴とする。
The dry etching apparatus of the present invention includes a parallel plate electrode sheet 1 which includes a flat lower electrode on which a substrate to be etched is placed, and a flat upper electrode facing the lower electrode in row f.
° In the lyetching device, the lower electrode and the upper
The ratio of 1 ton distance d from the polarization to the diameter g of the upper electrode is 3.
It is characterized by being 4 or less.

本発明の実施例について図面を用いて説明す゛る。Embodiments of the present invention will be described with reference to the drawings.

第1図において、上部v1.極2の1■径をg、上部電
極2と下部電極3との距離をdとするとき、本発明では
g/dの比を3.4以下にする。このようにすることに
よりエツチング速度の均一性が大幅に改善される。
In FIG. 1, upper v1. When the diameter of the pole 2 is g and the distance between the upper electrode 2 and the lower electrode 3 is d, the ratio of g/d is set to 3.4 or less in the present invention. This greatly improves the uniformity of the etching rate.

第2図は第1図に示すドライエツチング装置を用いて半
導体基板上に設けられたAl膜をエツチングしたときの
A7エツチング深さ及び半導体基板内エツチング速度分
布をg/dに対して示した相関関係図である。
Figure 2 shows the relationship between g/d and the A7 etching depth and etching rate distribution within the semiconductor substrate when an Al film provided on a semiconductor substrate is etched using the dry etching apparatus shown in Figure 1. It is a relationship diagram.

実線11はA/のエツチング深さケ示し、破線12Fi
半導体基板内エツチング速度分布を示す。
The solid line 11 indicates the etching depth of A/, and the broken line 12 Fi
This shows the etching rate distribution within a semiconductor substrate.

このエツチングにおいて、エツチング速度は2000A
/mi n以上である。g/dを3.4へ向って小さく
すると、実線11で示すように、 Alのエツチング深
さが深くなって行っても、破線12で示すように半導体
基板内エツチング速度分布のばらつきは段々小さくな’
) s g / dが3.4以下になると5チ以下にな
る。分布の俤の比11砺をすると、十数チであったもの
が5係未満になるのであるから5゜慢以上の改善がなさ
れたことになる。これは上部電極径gに対してN、極間
距離dを大きくしたことによりプラズマ密I象が均一に
なるためと考えられる。
In this etching, the etching speed is 2000A
/min or more. As g/d decreases toward 3.4, as shown by the solid line 11, even if the Al etching depth becomes deeper, the variation in the etching rate distribution within the semiconductor substrate becomes smaller and smaller, as shown by the broken line 12. Na'
) When s g / d becomes 3.4 or less, it becomes 5 chi or less. If we increase the ratio of the distribution to 11, what used to be more than 10 chi becomes less than 5, which means that an improvement of more than 5 degrees has been achieved. This is considered to be because the plasma density I-effect becomes uniform by increasing N and the inter-electrode distance d relative to the upper electrode diameter g.

以上詳細に説明したように、本発明によれば、エツチン
グ速度を増大しても均一なエツチング速度分布を有する
ドライエツチング装置が得られるのでその効果は大きい
As described in detail above, according to the present invention, even if the etching rate is increased, a dry etching apparatus having a uniform etching rate distribution can be obtained, so the effect is significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は平行平板電極枚虜型ドライエツチング装置の一
例の断面図、第2図は第1図に示すドライエツチング−
載置を用いて半導体基板上に設けられたAl膜をエツチ
ングしたときのAlのエツチング深さ及び半導体基板内
エツチング速度分布をg/dに対して示した相関関係図
である。 l・・・・・・真空チャンバ、2・・・・・・上部電極
、計・・・・・下部電極、4・・・・・・エツチングガ
ス、5・・・・・・半導体基板、6・・・・・・排気口
、11・・・・・・Alのエツチング深さ、12・・・
・・・半導体基板内エツチング速度分布。 蔦1図 (97al l ′$Z図
FIG. 1 is a sectional view of an example of a parallel plate electrode single-capture type dry etching device, and FIG. 2 is a cross-sectional view of an example of the dry etching device shown in FIG.
FIG. 3 is a correlation diagram showing the etching depth of Al and the etching rate distribution in the semiconductor substrate with respect to g/d when an Al film provided on the semiconductor substrate is etched using a mounting method. 1...Vacuum chamber, 2...Upper electrode, Meter...Lower electrode, 4...Etching gas, 5...Semiconductor substrate, 6 ...Exhaust port, 11...Al etching depth, 12...
...Etching rate distribution within a semiconductor substrate. Ivy 1 diagram (97al l'$Z diagram

Claims (1)

【特許請求の範囲】[Claims] 被エツチング基板を載置する平板状の下部電極と、該下
部電極に平行に対向する平板状の上部電極とを内蔵する
平行平板電極枚葉型のドライエツチング装置において、
前記下部電極と上部電極との距離圧と前記上部電極の直
径gとの比を3.4以下としたことを特徴とするドライ
エツチング装置。
In a parallel plate electrode single-wafer type dry etching apparatus that includes a flat lower electrode on which a substrate to be etched is placed and a flat upper electrode facing parallel to the lower electrode,
A dry etching apparatus characterized in that the ratio of the distance pressure between the lower electrode and the upper electrode to the diameter g of the upper electrode is 3.4 or less.
JP18701982A 1982-10-25 1982-10-25 Dry etching device Pending JPS5975630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18701982A JPS5975630A (en) 1982-10-25 1982-10-25 Dry etching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18701982A JPS5975630A (en) 1982-10-25 1982-10-25 Dry etching device

Publications (1)

Publication Number Publication Date
JPS5975630A true JPS5975630A (en) 1984-04-28

Family

ID=16198769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18701982A Pending JPS5975630A (en) 1982-10-25 1982-10-25 Dry etching device

Country Status (1)

Country Link
JP (1) JPS5975630A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0822982A (en) * 1995-03-09 1996-01-23 Toshiba Corp Etching condition setting method for dry etching equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0822982A (en) * 1995-03-09 1996-01-23 Toshiba Corp Etching condition setting method for dry etching equipment

Similar Documents

Publication Publication Date Title
KR100352770B1 (en) Topology induced plasma enhancement for etched uniformity improvement
US4578559A (en) Plasma etching method
JPS61253823A (en) Plasma reactor
JPH0359573B2 (en)
JPS63122220A (en) Electrode for reactive ion etching system and reactive ion etching system employing the electrode
JPH05226258A (en) Plasma generation apparatus
JPS5975630A (en) Dry etching device
JPH0666301B2 (en) Plasma etching method
JPS62299031A (en) Electrode structure of parallel plate etching system
JPH02198138A (en) Electrode plate of parallel plate type dry etching apparatus
JPS6077427A (en) Dry etching device
JPS6324623A (en) Plasma treatment equipment
JPH0437126A (en) Dry etching apparatus
JPS6366394B2 (en)
JPS63102321A (en) Semiconductor manufacture equipment
JPS63166235A (en) Parallel flat plate type plasma cvd system
JPS62286227A (en) Dry etching apparatus
JPS6032972B2 (en) Etching device
JP3327285B2 (en) Plasma processing method and semiconductor device manufacturing method
JPH03129821A (en) Manufacture of semiconductor device
JPH02253618A (en) Plasma treatment device
JPS6129127A (en) Treating device
JPS62128526A (en) Dry etching device
JPH05234951A (en) Plasma etching system
JPS62108526A (en) Working method for semiconductor plate