JPS5975415A - Record and reproduction compensating circuit of pcm sound recording and reproducing device - Google Patents

Record and reproduction compensating circuit of pcm sound recording and reproducing device

Info

Publication number
JPS5975415A
JPS5975415A JP18601682A JP18601682A JPS5975415A JP S5975415 A JPS5975415 A JP S5975415A JP 18601682 A JP18601682 A JP 18601682A JP 18601682 A JP18601682 A JP 18601682A JP S5975415 A JPS5975415 A JP S5975415A
Authority
JP
Japan
Prior art keywords
circuit
recording
output
delay element
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18601682A
Other languages
Japanese (ja)
Inventor
Takaharu Noguchi
敬治 野口
Hiroyuki Kimura
寛之 木村
Hiroaki Takahashi
宏明 高橋
Shigeru Yamazaki
茂 山崎
Masahiro Ito
雅博 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18601682A priority Critical patent/JPS5975415A/en
Publication of JPS5975415A publication Critical patent/JPS5975415A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10527Audio or video recording; Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Digital Magnetic Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To reduce the error rate at the time of reproduction and improve the reliability, by providing a delay element corresponding to less than the detection window width of digital signals, coefficient instrument which changes the output gain of the delay element, a circuit for inverting the polarity of a signal, and their adder. CONSTITUTION:The high level and low level of input signals 61 are dependently detected by using two detecting circuits 83 through an inverter 84. The detecting circuit 83 for data width at a high level of the input signal 61 is constituted with a set of 2T- pulse detecting circuit 79 and coefficient instrument 81 and another set of 1.5T-pulse detecting circuit 80 and coefficient instrument 82 and, when 2T- and 1.5T-pulses of the input signal 61 are detected, the 2T-pulse output is intensified to a prescribed level as compared with the 1.5T-pulse, and then, outputted. This processing is also made in the case of an low level input. A synchronizing circuit 78 outputs the synchronizing circuit output signal 85 of input signals synchronizing to the 2T- and 1.5T-pulses detected by the detecting circuit 83 and a record compensating circuit output 91 is obtained by adding the signals 85-89 to each other at an adder circuit 90. Therefore, the error rate at the time of reproduction can be reduced and the reliability as a PCM sound recording and reproducing device can be improved.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、磁気テープに信号を記録再生する場合に符号
誤り回数を最小にするPCM録音再生機の記録再生補償
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a recording and reproducing compensation circuit for a PCM recording and reproducing machine that minimizes the number of code errors when recording and reproducing signals on a magnetic tape.

〔従来技術〕[Prior art]

従来のPCM録tfFj生機の構成および記録再生補償
回路の構成とその問題点を第1図から第4図により説明
する。第1図は、従来の固定ヘッド型PCM録音再生機
の磁気ヘッド,テープを含む変復調回路系の概略ブロツ
ク図である。
The configuration of a conventional PCM recording tfFj raw machine, the configuration of a recording/reproducing compensation circuit, and the problems thereof will be explained with reference to FIGS. 1 to 4. FIG. 1 is a schematic block diagram of a modulation/demodulation circuit system including a magnetic head and tape of a conventional fixed head type PCM recording/reproducing machine.

同図において、ディジタル入力信号1は、変調回路2、
記録アンプ3を経て、記録ヘッド4lごて磁気テープ5
に記録される。再生時ζこは、再生ヘッド6によって磁
気テープから読み出された信号は再生アンプ7で増幅さ
れ、再生補償回路8で伝送系の一波形歪を等化した後、
積分回路9に入力される。積分回路9により波形整形さ
れた信号は、コンパレータ10で方形波に変換された後
、復調回路11でクロック再生を行ない復調出力信月1
2となる。第2図に記録波形13と再生波形14を示す
。再生ヘッド6で微分検出された和牛波形は、一般に磁
気デープ,ヘッドおよび両者間のスペーシングを自めた
記録h生糸の帯域が不十分となり、単一ステップ入力信
号の微分出力波形のすそが広がってくる。才だ、この波
形は、磁気テープおよびヘッド系の特性により、図に示
すような最大振幅のAの所のパルス幅(通常半値幅W5
0という)か、t〉0ど1<0でアンハランスとなる。
In the figure, a digital input signal 1 is transmitted to a modulation circuit 2,
Through the recording amplifier 3, the recording head 4l magnetic tape 5
recorded in During playback, the signal read from the magnetic tape by the playback head 6 is amplified by the playback amplifier 7, and after equalizing one waveform distortion of the transmission system by the playback compensation circuit 8,
It is input to the integrating circuit 9. The signal whose waveform has been shaped by the integrating circuit 9 is converted into a square wave by the comparator 10, and then the clock is recovered by the demodulating circuit 11, and the demodulated output signal 1 is output.
It becomes 2. FIG. 2 shows a recording waveform 13 and a reproduction waveform 14. The Wagyu beef waveform differentially detected by the reproducing head 6 generally has an insufficient band of the magnetic tape, the head, and the recording h raw silk with the spacing between them, and the base of the differential output waveform of the single step input signal is widened. It's coming. Due to the characteristics of the magnetic tape and head system, this waveform has a pulse width (normally half width W5) at the maximum amplitude point A as shown in the figure.
0) or 1<0 such as t>0, an imbalance occurs.

このような記釘・和牛糸の周波数特性が不十分でかつ非
線形勃性を有す系を用いて、音響信号またはアナロク信
号などをディジタル信号に変換し、第2図に示すような
信号を例えばデータビットの変化点をt=T毎に伝送す
る場合、記録したデータピット相互の符号量干渉によっ
て再生信号の品質が劣化し、記録時のデータピット間隔
が再生時に変化し、ディジタル13号の識別が困難とな
り、符号誤りが増大する。そこで、伝送された信号を正
しく識別するための波形等化を行う従来の補償回路は記
録アンプ3を定電流アンプで構成し記録・\ラド4に一
定′1流を記録して、再生ヘッド6で微分検出された信
号を再生系0)みで補償する方式を用い第3図のような
構成としていた。第3図は遅延素子を2個用いた従来例
である。
Using a system in which the frequency characteristics of the nails and Wagyu thread are insufficient and non-linear, an acoustic signal or an analog signal is converted into a digital signal, and the signal shown in Fig. 2 is converted into a digital signal, for example. When transmitting data bit change points every t = T, the quality of the reproduced signal deteriorates due to code amount interference between the recorded data pits, the data pit interval during recording changes during reproduction, and the digital number 13 identification becomes difficult, and code errors increase. Therefore, in a conventional compensation circuit that performs waveform equalization to correctly identify the transmitted signal, the recording amplifier 3 is configured with a constant current amplifier, and a constant current is recorded in the recording/rad 4, and the reproducing head 6 A system was used in which the differentially detected signal was compensated for only by the reproduction system 0), and the configuration was as shown in FIG. 3. FIG. 3 shows a conventional example using two delay elements.

第3図Cこ昭いで、14は再生信号久方、15はデータ
・ピット間隔Tと同じ長さに和尚する遅延素子、16お
よび18は利得を変化させる係数器、19は極性反転回
路、23は加算器、24は再生補償回路出力である。こ
の図の波形等化の方法を第4図を用いて説明する。
In FIG. 3C, 14 is a reproduced signal, 15 is a delay element that adjusts to the same length as the data pit interval T, 16 and 18 are coefficient units that change the gain, 19 is a polarity inversion circuit, 23 is an adder, and 24 is the output of the regeneration compensation circuit. A method of waveform equalization in this figure will be explained using FIG. 4.

一般に、データビット間隔T毎に伝送された信号を正シ
,<識別するためには、第4図に示す1パルスピーク点
(t=0の点)を除くデータビット間隔(t=nT)で
零になりさえすれば基本的には識別できる。そこで、第
3図の従来回路では、再生信号人力14をデータビット
間隔Tだけ遅延素子15で遅延させ係数器17で利得を
変化させた信号20に対して遅延前の信号に係数器16
ヲ通して利得を変化させた後、極性反転回路19で極性
を反転させた信号21、および信号20よりさらにTた
け遅延素子15で遅延させた信号を同様に係数器18、
極性反転回路19に通して得た信号22を加算器231
と入力して係数器16〜18の値を設定することにより
、再生補償回路出力241こ示すように少なくとも隣り
合ったデータ変化点(1=±T)での振幅を零にしてい
る。この場合、再生信号人力14のパルスピーク点およ
びピーク点前後のデータ変化点t=−T、Tでのそれぞ
れの振幅値を1 、0.3 、0.7とすると、係数器
16.17.18の係数に〜+、ko、kxは、再生補
償回路出力24の条件より次式で一意的に定まる。すな
わち第4図において、 t=−Tでのイ直・・・k−1+0.3ko = □t
=Qでのイ直・・・0.7に−x +ko + 0.3
kt = 1t=Tでの値・・・0.7kO+ kl 
= 0  よりに−1= −0,52、ko −1,7
2、に1 = −1,21と求まり再生補償回路出力2
4を得ることができる。しかし、記録再生帯域が不十分
でかつ非線形特性を有す再生信号を従来の補償回路で波
形等化し2ても、データビット間隔T毎に補正するため
24に示すように半値幅W50の+〈0、十〉0の値が
アンバランスとなる。したがって、第5図に示すような
データビット間隔がTの信号25を記録した場合の再生
補償回路の出力信号26は上記したアンバランスの信号
24ヲデ一タピツト変化点ごとに加算するため(24,
24’ 、24″)、隣接ビットによる波形干渉でデー
タビットの変化点に対してdr 1.xT 2だけ大幅
に記録再生糸で変化する問題が生じていた。その結果、
出力信号26を積分回路9で波形整形し、コンパレータ
10で方形波に変換後復調回路11で復調する場合、上
記した記録再生時のデータビット間隔の変化により、デ
ータの識別のマージンを大幅に減少させ、データ誤り回
数を増加させる原因となっていた。さらに、従来のP 
CM録音再生機は、伝送するディジタル信号の最大記録
周波数において磁気ヘッドからの再生出力レベルが最大
となる記録電流値近傍に記録ヘッドの記録電流を設定し
て、定電流記録している。しかし、一般に磁気テープ、
磁気ヘッドを用いた磁気記録書化系においては、定電流
記録した場合に高域周波数成分における周波数特性劣化
の他に、直流から低周波成分までの帯域が伝送しにくい
という問題がある。このため、この低周波成分の帯域不
足により再生信号のDCレベル変動が生じ、その結果デ
ータ識別し/ベルのマージンをさらに減少させるととも
に、低域周波数成分の欠如を相対的に高域周波数成分を
再生補償回路で低下させることにより全体の帯域を補正
した場合はS 、/ N ヲ劣化さぜるこ々になり、デ
ータ誤り回数を増加させていた。
Generally, in order to identify the signal transmitted at every data bit interval T, it is necessary to identify the signal transmitted at every data bit interval T (t = nT) except for the one pulse peak point (t = 0 point) shown in Figure 4. Basically, it can be identified as long as it becomes zero. Therefore, in the conventional circuit shown in FIG. 3, the reproduced signal 14 is delayed by the data bit interval T by the delay element 15, and the gain is changed by the coefficient multiplier 17.
After changing the gain through the polarity inverting circuit 19, the signal 21 whose polarity has been inverted by the polarity inverting circuit 19, and the signal which has been further delayed from the signal 20 by T delay element 15 are similarly sent to the coefficient multiplier 18,
The signal 22 obtained through the polarity inversion circuit 19 is sent to the adder 231.
By inputting and setting the values of the coefficient multipliers 16 to 18, the amplitude of the reproduction compensation circuit output 241 is made zero at least at the adjacent data change points (1=±T) as shown. In this case, assuming that the amplitude values at the pulse peak point of the reproduced signal 14 and the data change points t=-T and T before and after the peak point are 1, 0.3, and 0.7, respectively, the coefficient multipliers 16, 17. The 18 coefficients ~+, ko, and kx are uniquely determined by the following equation based on the conditions of the reproduction compensation circuit output 24. That is, in Fig. 4, A direct at t=-T...k-1+0.3ko = □t
= A straight line at Q...0.7 to -x +ko + 0.3
kt = 1t=value at T...0.7kO+kl
= 0 so -1= -0,52, ko -1,7
2, 1 = -1,21 is found, and the reproduction compensation circuit output 2
You can get 4. However, even if a reproduced signal with an insufficient recording/reproducing band and nonlinear characteristics is waveform-equalized using a conventional compensation circuit, the half-width W50 +< A value of 0, 10>0 is unbalanced. Therefore, the output signal 26 of the reproduction compensation circuit when the signal 25 with the data bit interval T as shown in FIG. ,
24', 24''), there has been a problem in which the recording/reproducing thread changes significantly by dr 1.
When the output signal 26 is waveform-shaped by the integrating circuit 9, converted into a square wave by the comparator 10, and then demodulated by the demodulating circuit 11, the margin for data identification is significantly reduced due to the above-mentioned change in the data bit interval during recording and reproduction. This caused an increase in the number of data errors. Furthermore, conventional P
A CM recording/reproducing machine performs constant current recording by setting the recording current of the recording head near the recording current value at which the reproduction output level from the magnetic head is maximum at the maximum recording frequency of the digital signal to be transmitted. However, generally magnetic tape,
In a magnetic recording system using a magnetic head, in addition to deterioration of frequency characteristics in high frequency components when performing constant current recording, there is a problem in that it is difficult to transmit a band from direct current to low frequency components. Therefore, this lack of low-frequency component bandwidth causes DC level fluctuations in the reproduced signal, which further reduces the margin for data identification/belt, and the lack of low-frequency components can be compared to high-frequency components. If the entire band is corrected by lowering it with a reproduction compensation circuit, S,/N deteriorates and the number of data errors increases.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、従来技術の欠点をなくし磁気テープお
よび磁気ヘッドによる伝送波形のひずみを補正し、デー
タを正しく識別することが可能となるPCM録音再生機
の記録/再生補償回路を提供するにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a recording/playback compensation circuit for a PCM recording/playback machine that eliminates the drawbacks of the prior art, corrects distortion of transmission waveforms due to magnetic tape and magnetic heads, and makes it possible to correctly identify data. be.

〔発明の概要〕[Summary of the invention]

本発明は、従来の欠点が再生補償回路のみで波形等化を
行っていること、および再生補償回路の構成がデータビ
ット間隔Tζこ相当する遅延素子で補正したことによっ
て生じることに着目し、再生補償回路は補正・2行うデ
ータ点をデータビット間隔内に複数個殴り、位相補正の
正確さおよび制御範囲の拡大を計ったものである。
The present invention focuses on the fact that the conventional drawback is that waveform equalization is performed only by a reproduction compensation circuit, and that this occurs because the configuration of the reproduction compensation circuit corrects it with a delay element corresponding to the data bit interval Tζ. The compensation circuit has a plurality of data points for correction/second correction within the data bit interval to improve the accuracy of phase correction and expand the control range.

また、記録補償回路は位相特性を変化させることなく低
域周波数成分の記録電流を増加させたものである。
Further, the recording compensation circuit increases the recording current of the low frequency component without changing the phase characteristics.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第6図により説明する。M6
図は、再生補償回路の一実施例を示したものである。■
4は再生信号人力、27はデータビット間隔Tを2等分
した値に相当する遅延素子、28から32は各遅延素子
出力の利得を変化させる係数器、19は極性反転回路、
23は加算器、38は再生補償回路出力である。ここで
、波形ひずみを生じている再生信号人力】4に対しで、
データビット間隔T毎に伝送されてくる信号を正しく識
別する必要がある。このために、第6図に示す本実施例
では、再生補償回路出力38においてパルスピーク点の
振幅fi−1とすると、パルスピーク点を除く隣接デー
タビット点t=±Tにおいて振幅を零にするとともに、
データビット間隔′rの半分に相当する遅延素子27を
設けてt;十0.5Tでの振幅値を05にして位相ひず
みをなくしている。すなわち、再生信号人力14を従来
例と同一波形、パルスピーク点1t=Qとしたときt 
=−T 、−0,5’I”、0.0.5T、TニオFJ
ルそれぞれの振幅値を0.3 、0.8 、1 、0.
9 、0.7とした場合、各遅延素子出力27の利得を
変化させる係数器28から32の係数1−1,1−0.
5,10,10,5,11  は、再生補償回路出力3
8の条件より以下のように求めることができる。再生補
償回路出力38のパルスピーク点をtI+:+0とする
と、 t=−Tでのイ直・・・l−z 十0.81−o、a 
−4−0,3io = 0t=−0,5’l’・・・0
.91−1 +1−0.5+0.81o−4−Q、31
o、s =0.51=0・・・0.71−1+0.91
−0.5+IO+0.810.5+0.311=1t=
o、5’l”・・・0.71−0.5+0.91o+1
0.5+Q、811 =0.5t=1゛・・・0.71
0 +0.9io、s +11 = Qの4つの式より
、I−1= 1.9 、 l −o、s =−1,5、
l Q=−2,3、lo、s = 7.1 、 l 1
 =−4,7となる。
An embodiment of the present invention will be described below with reference to FIG. M6
The figure shows an example of a regeneration compensation circuit. ■
4 is a reproduced signal manually; 27 is a delay element corresponding to the value obtained by dividing the data bit interval T into two; 28 to 32 are coefficient units that change the gain of each delay element output; 19 is a polarity inversion circuit;
23 is an adder, and 38 is a reproduction compensation circuit output. Here, for the reproduction signal [manual power] 4 that causes waveform distortion,
It is necessary to correctly identify the signal transmitted every data bit interval T. For this reason, in the present embodiment shown in FIG. 6, if the amplitude at the pulse peak point in the reproduction compensation circuit output 38 is fi-1, the amplitude is made zero at the adjacent data bit point t=±T excluding the pulse peak point. With,
A delay element 27 corresponding to half the data bit interval 'r is provided, and the amplitude value at t:10.5T is set to 05 to eliminate phase distortion. That is, when the reproduced signal 14 has the same waveform as the conventional example and the pulse peak point 1t=Q, t
=-T, -0,5'I", 0.0.5T, TnioFJ
The amplitude values for each channel are set to 0.3, 0.8, 1, 0.
9, 0.7, the coefficients 1-1, 1-0, .
5, 10, 10, 5, 11 are reproduction compensation circuit output 3
It can be determined as follows from the conditions of 8. If the pulse peak point of the reproduction compensation circuit output 38 is tI+:+0, then the straight line at t=-T...l-z 10.81-o, a
-4-0,3io = 0t=-0,5'l'...0
.. 91-1 +1-0.5+0.81o-4-Q, 31
o,s =0.51=0...0.71-1+0.91
-0.5+IO+0.810.5+0.311=1t=
o, 5'l"...0.71-0.5+0.91o+1
0.5+Q, 811 =0.5t=1゛...0.71
From the four equations of 0 +0.9io, s +11 = Q, I-1 = 1.9, l -o, s = -1,5,
l Q=-2,3, lo, s = 7.1, l 1
=-4,7.

第6図の本実施例の動作を第7図を用いて説明する。第
7図において、第6図に上記した再生信号人力14が入
力されると、0.5’f’の遅延素子27ニヨリ再生信
号人力14ニij L/ TJ O、0,5’I’ 、
 T 。
The operation of this embodiment shown in FIG. 6 will be explained using FIG. 7. In FIG. 7, when the reproduced signal input 14 described above in FIG.
T.

x、s’f’、2Tだけ遅延した信号に上記の係数1−
1=1.9.1−〇、5=−1.6 、1o=−2,3
,10,5=7.1. I+=−4,7の係数器28か
ら32を経で、極性反転回路を通ることにより、それぞ
れ加算器23の入力信号33から37が得られる。これ
らの信号を加算器23で加算することにより、再生補償
回路出力38ヲ得る。この出力38は、パルスピーク点
を除く隣接ビット点t=±Tで振幅が零であるとともに
、±0.5Tでの振幅値はともにパルスピーク値の半分
となり非線形特性が大幅に数置できる。
The above coefficient 1- is applied to the signal delayed by x, s'f', 2T.
1=1.9.1-〇, 5=-1.6, 1o=-2,3
,10,5=7.1. The input signals 33 to 37 of the adder 23 are obtained by passing through the coefficient multipliers 28 to 32 with I+=-4 and 7 and the polarity inversion circuit, respectively. By adding these signals in the adder 23, a reproduction compensation circuit output 38 is obtained. This output 38 has zero amplitude at adjacent bit points t=±T excluding the pulse peak point, and the amplitude values at ±0.5T are both half of the pulse peak value, and the nonlinear characteristics can be greatly increased.

第8図は、第6図に示す本実施例の効果を示す図であり
、テークビット間隔がTの信号25を磁気テープにUt
 ’Elくし、角化ヘッドが微分検出した信郵を第6図
の再生補償回路で等化したものである。データビット間
隔′rの入力信号25を記録p+生した場合の再生補償
回路出力は、t==Qのときの出力38とt=−’1’
での出力39およびt=Tでの出力40との加算信号と
する。この加算信号は41となり、記録再生時のデータ
ビット点の変化もほとんとなく、その結果、÷ノ(分回
路およびコンパレータを通して後調回路でデータを復調
する場合、データの識別マージンが大幅に増加し、イg
稙性のあるPCM録音再生機を得ることかできる。
FIG. 8 is a diagram showing the effect of the present embodiment shown in FIG.
The mail differentially detected by the square head is equalized by the reproduction compensation circuit shown in FIG. When the input signal 25 with the data bit interval 'r is recorded p+, the reproduction compensation circuit output is the output 38 when t==Q and the output 38 when t=-'1'.
The signal is the sum of the output 39 at t=T and the output 40 at t=T. This addition signal becomes 41, and there is almost no change in the data bit point during recording and playback. Shi, Ig
It is possible to obtain a sophisticated PCM recording/playback device.

第6図から、68図に示す本実施例においては、データ
ヒツト間隔T内を・等間1拠で内押して遅延素子を配置
した例であるか、不等間隔で配置する場合およびパルス
ピーク点を除くデータビット点を除いた場合も、本実施
例と同様な効果が得られる。
In the present embodiments shown in FIGS. 6 to 68, the delay elements are arranged by pressing inward at equal intervals within the data hit interval T, or the delay elements are arranged at unequal intervals and the pulse peak point is Even when the excluded data bit points are excluded, the same effect as in this embodiment can be obtained.

第9図は、アナログ信号をディジタル信号に変換し、M
FM変調して記録再生したときの再生補償回路の一実施
例である。MFM変調記録においては、データビット長
は良く知られているようにT 、 1.5T、 2 T
の3種類であり、波形干渉をなくしデータの識別を正し
く行うためには0.5Tの間隔で微分出力波形の振幅を
零にする必要がある。第9図においては、データビット
長Tが約8.3μsのデータを1μs毎の遅延素子42
−¥設け、それぞれの係数器43〜53、極性反転回路
19を通して加算回路23で加算することにより、再生
信号入力の波形ひずみを等化したものである。この場合
の第9図に示す再生補償回路の振幅特性と郡遅延特性を
第10図の55 、56にそれぞれ示す。
Figure 9 shows how to convert an analog signal into a digital signal and convert the M
This is an example of a reproduction compensation circuit when recording and reproduction is performed with FM modulation. In MFM modulation recording, the data bit length is T, 1.5T, 2T, as is well known.
In order to eliminate waveform interference and correctly identify data, it is necessary to make the amplitude of the differential output waveform zero at intervals of 0.5T. In FIG. 9, data with a data bit length T of approximately 8.3 μs is transmitted to the delay element 42 every 1 μs.
-\, and the waveform distortion of the reproduced signal input is equalized by adding them in the adder circuit 23 through the coefficient multipliers 43 to 53 and the polarity inversion circuit 19. The amplitude characteristics and group delay characteristics of the reproduction compensation circuit shown in FIG. 9 in this case are shown at 55 and 56 in FIG. 10, respectively.

つぎに、本発明による記録補償回路の一実施例を第11
図により説明する。第11図は、記録補償回路60を変
調回路2の出力に接続し、位相特性をディジタル入力信
号1と変化させることなく低域周波数帯域を増強した後
、記録アンプ3に入力して記録ヘッド4にて磁気テープ
5に記録する。記録補償回路60の一実施例を第12図
および第13図により説明する。
Next, one embodiment of the recording compensation circuit according to the present invention will be described in the eleventh embodiment.
This will be explained using figures. In FIG. 11, a recording compensation circuit 60 is connected to the output of the modulation circuit 2 to enhance the low frequency band without changing the phase characteristics from the digital input signal 1, and then input to the recording amplifier 3 and output to the recording head 4. The information is recorded on the magnetic tape 5 at the same time. One embodiment of the recording compensation circuit 60 will be described with reference to FIGS. 12 and 13.

第12図の実施例は、MFM変調信号を磁気テープに記
録する場合の磁気テープおよび磁気ヘッドによる低域周
波数帯域の不足を遅延素子を用いて補償したものである
。ここでMFM変詞信号のデータビット長Tが約8.3
μsのとき、1μsの遅延素子を10個カスケード接続
し、各々の遅延素子出力を係数器63〜73により利得
を変化し加算器74で加算し7、変調回路2の出力信号
61を低域増強し、記録補償目録出力信号75を1得る
。第13図において、76は得られた振幅特性、77は
群遅延特性である。一般に、磁気記録において、磁気テ
ープの材料の相違(例えばに−Fez−03系、メタル
系など)および使用する記録ヘッドの性能により、低域
周波数特性が大幅に変化する場合がある。このような場
合においても、第12図に示す実施例においては、複数
個ある遅延素子の中央の遅延素子の出力の係数器68の
係数のみを調整することにより、第13図76に示すよ
うに簡単に低域周波数特性が可能であることより、磁気
テープ、ヘッドの性能に関する制御範囲が大きくとれる
ことより、PCM録音再生機としての性能2よび信頼性
を向上できる。係数器68以外の係数は、第12図にお
いては、係数器68に対して左右対称すなわち係数器6
7と69.66と70のようにこれらの係数は同一とな
っている。
The embodiment shown in FIG. 12 uses a delay element to compensate for the lack of a low frequency band caused by the magnetic tape and magnetic head when recording an MFM modulated signal on a magnetic tape. Here, the data bit length T of the MFM adverbial signal is approximately 8.3
In the case of μs, ten 1 μs delay elements are connected in cascade, and the gain of each delay element output is changed by coefficient multipliers 63 to 73 and added by an adder 74 7, and the output signal 61 of the modulation circuit 2 is amplified in the low frequency range. Then, a recording compensation list output signal 75 of 1 is obtained. In FIG. 13, 76 is the obtained amplitude characteristic, and 77 is the group delay characteristic. In general, in magnetic recording, low frequency characteristics may vary significantly depending on the material of the magnetic tape (for example, -Fez-03 type, metal type, etc.) and the performance of the recording head used. Even in such a case, in the embodiment shown in FIG. 12, by adjusting only the coefficient of the coefficient multiplier 68 of the output of the central delay element of the plurality of delay elements, the result as shown in FIG. 13 76 can be obtained. Since low frequency characteristics can be easily achieved, the control range regarding the performance of the magnetic tape and head can be widened, and the performance 2 and reliability of the PCM recording/reproducing machine can be improved. In FIG. 12, the coefficients other than the coefficient multiplier 68 are symmetrical with respect to the coefficient multiplier 68, that is, the coefficient multiplier 6
These coefficients are the same, such as 7 and 69.66 and 70.

第14図にMFM変調したときの記録補償回路の他の一
実施例を示す。第14図において、78は同期化回路、
79は2 Tパルス検出回路、80は15′rパルス検
出回路、81.82は係数器、83はデータ幅検出制御
回路、84はインバータ回路、85は同期化回路出力、
86は変調回路出力信号のhighレベルの2Tパルス
出力、87は1.5Tパルス出力、88は変調回路出力
信号のLowレベルの2Tパルス出力、89は1.5T
パルス出力、90は加算器、91は記録補償回路出力で
ある。
FIG. 14 shows another embodiment of the recording compensation circuit when performing MFM modulation. In FIG. 14, 78 is a synchronization circuit;
79 is a 2T pulse detection circuit, 80 is a 15'r pulse detection circuit, 81.82 is a coefficient unit, 83 is a data width detection control circuit, 84 is an inverter circuit, 85 is a synchronization circuit output,
86 is a high level 2T pulse output of the modulation circuit output signal, 87 is a 1.5T pulse output, 88 is a low level 2T pulse output of the modulation circuit output signal, and 89 is a 1.5T pulse output.
90 is an adder, and 91 is a recording compensation circuit output.

本実施例の動作を第15図を用いて説明する。The operation of this embodiment will be explained using FIG. 15.

データ幅検出回路83は、変調器出力信号である11t
4 F M入力信号610) 2 ’L’j6ヨU;1
.5’J’U)パルス幅を検出するものであり、2個の
データ幅検出回w!83を用いてインバータ84を介し
て入力信号61のhighレベル、LOWレベル独立に
検出しでいる。
The data width detection circuit 83 detects the modulator output signal 11t.
4 FM input signal 610) 2 'L'j6yoU;1
.. 5'J'U) It detects the pulse width, and there are two data width detection times w! 83 is used to independently detect the high level and low level of the input signal 61 via the inverter 84.

入力1g+f61のIt i g bレベルにおけるデ
ータ幅検出回路83は、2Tパルス検出回路79および
係数器81.1.5Tパルス検出回路80および係数器
82で構成され、入力信号61のそれぞれ2 T’ 、
 1.5Tパルスが検出された時、2Tパルス出力86
は1.5Tパルス出力87に比較して、PJ1定の振幅
レベル増強され出力される。入力信号61のl、owレ
ベルにおけるデータ幅検出回路も同様な動作により、2
Tパルス出力88.1.5Tバ′ルス出力89ヲ出力す
る。同期化回路78は、データ幅検出回路83で慣出さ
イtた2Tパルスどよび1,5Tパルスに同期した人力
信号の同期化回路出力信号85を出力し、加算回路90
で上記した信号85〜89ヲ加算することにより記録補
償回路出力91を得る。
The data width detection circuit 83 at the It i g b level of the input 1g+f61 is composed of a 2T pulse detection circuit 79 and a coefficient multiplier 81.
When 1.5T pulse is detected, 2T pulse output 86
Compared to the 1.5T pulse output 87, the PJ1 constant amplitude level is enhanced and output. The data width detection circuit at the l and ow levels of the input signal 61 also operates in a similar manner.
T pulse output 88.1.5T pulse output 89 is output. The synchronization circuit 78 outputs a synchronization circuit output signal 85 of a human input signal synchronized with the 2T pulse and the 1.5T pulse detected by the data width detection circuit 83,
By adding the signals 85 to 89 described above, a recording compensation circuit output 91 is obtained.

本実施例によれば、変調回路2のディジタル信号の位相
特性を変化するこさなく、簡単な構成で低域周波数帯域
を増強することが可能おなり、再生時におけるS/Nの
劣化およびデータの識別マージンを低下することなく信
頼性のある記録補償回路が夾現できる。
According to this embodiment, it is possible to enhance the low frequency band with a simple configuration without changing the phase characteristics of the digital signal of the modulation circuit 2, thereby reducing the deterioration of S/N during reproduction and the loss of data. A reliable recording compensation circuit can be realized without reducing the identification margin.

なお、本実施例はM F M変調信号入力に対して記述
したが他の変調信号3PM、FMflどの場合も同様の
効果が得られる。
Although this embodiment has been described with respect to the input of the MFM modulation signal, the same effect can be obtained with other modulation signals such as 3PM and FMfl.

本実施例による記録補償回路および再生補償回路を用い
てデータビット長’]’ = 8.3μsのMFM変調
信号を記録再生した場合、従来方式のエラーL−−1−
がJO−1に対して本方式により10−3のエラーレー
トが得られ信頼性が大幅ζζ向士した。
When an MFM modulated signal with a data bit length ']' = 8.3 μs is recorded and reproduced using the recording compensation circuit and reproduction compensation circuit according to this embodiment, the error L--1- of the conventional method is
However, compared to JO-1, an error rate of 10-3 was obtained using this method, and the reliability was significantly improved.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ディジタル信号f 4B気テープに記
録再生した場合のエラーレートが10−1から10  
に低減でき、PCM録音再生機としての信頼性が大幅に
向上できた。
According to the present invention, the error rate when recording and reproducing a digital signal f on a 4B tape is from 10-1 to 10
The reliability of the PCM recording/playback device was greatly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はPCM録音再生機の構成、第2図は記録再生波
形、第3図は再生補償回路、第4図は波形等化波形、第
5図は波形干渉波形、第6図は本発明による再生補償回
路、第7図は波形等化波形、第8図は波形干渉波形、第
9図は再生補償回路、第10図は再生補償特性、第11
図はI) CM記録系プロ2り図、第12図は記録補償
回路、第13図は記録補償等性、第14図は記録補償回
路、第15図は言C録補償動作図である。 8・・再生補償回路 15.27,42.62・・遅延素子 16〜18.28〜32.43〜53 、63〜73・
・・係数器23.74.90・・加算器   60・・
・記録補償回路78・・・同期化回路 79・・・2Tパルス検出回路 80・・・1.5Tパルス検出回路 81〜82・・・係数器 83・・・データ幅検出回路 84・・・インバータ 代理人弁理士 薄 1)利 幸 第 l 図 第 2 図 第 3 図 7に 埠 d 第 乙図 第 7 廓 $ ? 叫 −27−TI=OT  2T 第 70 図 周波数(m) 茅 /2 口 第 11  図
Figure 1 shows the configuration of the PCM recording/playback machine, Figure 2 shows the recording and playback waveforms, Figure 3 shows the playback compensation circuit, Figure 4 shows the waveform equalization waveform, Figure 5 shows the waveform interference waveform, and Figure 6 shows the invention. Figure 7 shows the waveform equalization waveform, Figure 8 shows the waveform interference waveform, Figure 9 shows the reproduction compensation circuit, Figure 10 shows the reproduction compensation characteristics, and Figure 11 shows the reproduction compensation circuit.
The figures are I) CM recording system professional diagram; FIG. 12 is a recording compensation circuit; FIG. 13 is a recording compensation equality; FIG. 14 is a recording compensation circuit; and FIG. 15 is a recording compensation operation diagram. 8...Reproduction compensation circuit 15.27, 42.62...Delay element 16-18.28-32.43-53, 63-73.
・・Coefficient unit 23.74.90・・Adder 60・・
- Recording compensation circuit 78...Synchronization circuit 79...2T pulse detection circuit 80...1.5T pulse detection circuits 81-82...Coefficient unit 83...Data width detection circuit 84...Inverter Representative Patent Attorney Usui 1) Tori Yukidai l Figure 2 Figure 3 Figure 7 is a port d Figure O 7 is $? Shout-27-TI=OT 2T Fig. 70 Frequency (m) Chi/2 Mouth Fig. 11

Claims (1)

【特許請求の範囲】 1、 アナログ信号をディジタル信号に変換して、磁気
記録媒体に記録再生するPCM録音再生機において、記
録ディジタル信号の検出窓幅以下に相当する遅延素子と
該遅延素子の出力の利得を変化させる係数器と、信号の
極性を反転する極性反転回路と、係数器の出力または極
性反転回路の出力を加算する加算器を具備し、遅延素子
をN個直列接続し、第1番目の遅延素子入力およびそれ
ぞれの遅延素子出力を各遅延素子に対応する係数器に入
力した(N+1)個の係数器出力を直接または極性反転
回路を経て加算器に入力しくN+1)個の信号を加算し
たことを特徴とするPCM録音再生機の再生補償回路。 2、前記N個の遅延素子のうち、少なくとも1個の遅延
素子の遅延量が異なる遅延素子をN個直列接続して構成
したことを特徴とする特許 生機の再生補償回路。 3、 アナログ信号をディジタル信号に変換して、磁気
記録媒体に記録再生するPCM録音再生機において、記
録ディジタル信号の検出窓幅以下に相当する遅延素子と
該遅延素子の出力の利得を変化させる係数器と、信号の
極性を反転する極性反転回路と、係数器の出力または極
性反転回路の出力を加算する加算器を具備し、遅延素子
をN個直列接続し、第1番目の遅延素子入力およびそれ
ぞれの遅延素子出力を各遅延素子に対応する係数器に入
力した(N+1)個の係数器出力を直接または極性反転
回路を経て加算器に入力し(N+1)個の信号を加算し
、前記遅延素子と遅延素子の出力の利得を変化させる係
数器と複数の係数器出力を加算する加算器を具備し、遅
延素子をN個直列接続し、第1番目の遅延素子入力およ
びそれぞれの遅延素子出力を各遅延素子に対応する係数
器に入力し、利得を変化させた(N+1)個の係数器出
力を加算器に入力し加算したことf %徴とするPCM
録音再生機の記録補償回路。 4、前記N個の遅延素子に接続される係数器のうち、遅
延素子をN個直列接続した全遅延値の中央に相当する遅
延素子に接続される係数器の係数に対して、それぞれ等
しい進みおよび遅れの遅延素子に接続した係数器の係数
を等しくしたことを特徴とする特許 範囲第3項記載のP C M録音再生機の記録補償回路
。 5、 前記N個の遅延素子のうち、少なくとも1個の遅
延素子の遅延量が異なる遅延素子をN個直列接続して構
成したことを特徴とする前記特許請求の範囲第3項記載
のI)CM録音再生機の記録補償回路。 6、 前記第3項記載のPCM録音再生機において、記
録ディジタル信号のデータピット長を検出し、検出され
たビット長に対応して所定の振幅レベルを変化するデー
タ幅検出回路と、前記データ幅検出回路で検出された信
号にディジタル入力信号を同期化する同期化回路と、同
期化回路出力とデータ幅検出回路出力とを加算する加算
器を具備したことを特徴とするPCM録音再生機の記録
補償回路。
[Claims] 1. In a PCM recording/playback machine that converts analog signals into digital signals and records and plays them on a magnetic recording medium, a delay element whose width is equal to or less than the detection window width of the recorded digital signal and an output of the delay element are provided. a coefficient multiplier that changes the gain of the signal, a polarity inversion circuit that inverts the polarity of the signal, and an adder that adds the output of the coefficient multiplier or the output of the polarity inversion circuit, N delay elements are connected in series, and the first The input of the delay element and the output of each delay element are input to the coefficient multiplier corresponding to each delay element.The outputs of the coefficient multipliers of (N+1) are input to the adder directly or via a polarity inverting circuit to generate N+1) signals. A playback compensation circuit for a PCM recording/playback device characterized by addition. 2. The reproduction compensation circuit of the patented product, characterized in that, among the N delay elements, N delay elements in which at least one delay element has a different delay amount are connected in series. 3. In a PCM recording/playback machine that converts an analog signal into a digital signal and records and reproduces it on a magnetic recording medium, a delay element corresponding to a detection window width of the recording digital signal or less and a coefficient that changes the gain of the output of the delay element. a polarity inversion circuit that inverts the polarity of a signal, and an adder that adds the output of the coefficient multiplier or the output of the polarity inversion circuit, N delay elements are connected in series, and the first delay element input and The outputs of each delay element are input to the coefficient multiplier corresponding to each delay element.The outputs of the (N+1) coefficient multipliers are input directly or through a polarity inverting circuit to an adder, and the (N+1) signals are added. It is equipped with a coefficient multiplier that changes the gains of the outputs of the elements and delay elements, and an adder that adds the outputs of a plurality of coefficient multipliers, and N delay elements are connected in series, and the first delay element input and each delay element output is input to the coefficient multiplier corresponding to each delay element, and the outputs of (N+1) coefficient multipliers with varying gains are input to the adder and summed.
Recording compensation circuit for recording/playback equipment. 4. Among the coefficient multipliers connected to the N delay elements, the coefficients of the coefficient multipliers connected to the delay element corresponding to the center of all delay values obtained by connecting N delay elements in series are each given an equal advance. 3. A recording compensation circuit for a PCM recording/reproducing machine according to claim 3 of the patent scope, characterized in that the coefficients of the coefficient multipliers connected to the delay elements and the delay elements are made equal. 5. I) as set forth in claim 3, characterized in that, among the N delay elements, N delay elements in which at least one delay element has a different delay amount are connected in series. Recording compensation circuit for commercial recording and playback equipment. 6. In the PCM recording/playback device described in the above item 3, a data width detection circuit detects the data pit length of the recorded digital signal and changes a predetermined amplitude level in accordance with the detected bit length; A record of a PCM recording/playback device, characterized in that it is equipped with a synchronization circuit that synchronizes a digital input signal with a signal detected by a detection circuit, and an adder that adds the output of the synchronization circuit and the output of the data width detection circuit. Compensation circuit.
JP18601682A 1982-10-25 1982-10-25 Record and reproduction compensating circuit of pcm sound recording and reproducing device Pending JPS5975415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18601682A JPS5975415A (en) 1982-10-25 1982-10-25 Record and reproduction compensating circuit of pcm sound recording and reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18601682A JPS5975415A (en) 1982-10-25 1982-10-25 Record and reproduction compensating circuit of pcm sound recording and reproducing device

Publications (1)

Publication Number Publication Date
JPS5975415A true JPS5975415A (en) 1984-04-28

Family

ID=16180905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18601682A Pending JPS5975415A (en) 1982-10-25 1982-10-25 Record and reproduction compensating circuit of pcm sound recording and reproducing device

Country Status (1)

Country Link
JP (1) JPS5975415A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289505A (en) * 1985-06-17 1986-12-19 Teac Co Digital magnetic reproducing circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413313A (en) * 1977-07-01 1979-01-31 Gen Corp Method of processing digital signal

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413313A (en) * 1977-07-01 1979-01-31 Gen Corp Method of processing digital signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289505A (en) * 1985-06-17 1986-12-19 Teac Co Digital magnetic reproducing circuit
JPH067403B2 (en) * 1985-06-17 1994-01-26 ティアツク株式会社 Digital magnetic reproducing circuit

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