JPS5975404A - Data output device - Google Patents

Abstract

PURPOSE:To output successively each code for every black by simultaneously outputting in parallel plural codes which are sent in time series by a clock pulse at the time when codes of one block are inputted by another clock pulse obtaied by dividing the former clock pulse. CONSTITUTION:The information of a disk 1 is reproduced by means of a pickup at a pickup circuit 2 and an MFM-demodulated by a decoder 4 through an FM demodulator 3. An audio signal is outputted from an output terminal 5 and, at the same time, a video signal is outputted from another output terminal 8 through a memory 6 and a DC converter 7. A time code and a chapter code from the decoder 4 are supplied to data bolding circuits 12a-12d through a shift register 9, synchronizing signal detectors 10a-10d, and a data fetch controlling circuit 11, and then, a control signal is sent to a 24-counter 15. On the other hand, a clock pulse (a) is divided at a dividing circuit 14 and each code of the holding circuits 12a-12d is outputted for every block through a gate circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data output device that outputs a plurality of codes sent in time series using clock pulses into one block of =1
− Divide the frequency of the clock pulse at the moment the code is sent and US°
The clock pulses obtained by C are output simultaneously in parallel, and each -1
- It is an object of the present invention to provide a data output device which can sequentially output each code block by block without particularly externally supplying a clock pulse for simultaneously outputting the codes.

FIG. 1 shows a block system diagram in which an embodiment of the device of the present invention is applied to a disk-shaped information recording medium reproducing device.
is a disc, for example, a digital audio signal obtained by digital pulse modulation of a Δ-DΔ signal, and a still image signal for one screen as additional information for listening to the reproduced sound of the audio A signal is digitally pulse modulated. After the digital video signals are frequency-modulated, they are recorded in the same 1-to-easily intermittent sequence. The signal recorded on the disk 1 is reproduced by the pickup circuit 2 as a known light intensity change or capacitance change, and after being FM demodulated by the FM demodulator 3, it is supplied to the decoder 4 and UMFM decoded. Ru.

Here, one block of the UMFM-decoded digital recording signal is shown in FIG. #8-bit synchronization signal pitch indicating the start of Niblock [-1ch-i to Ch-3 are 1 of 3 channels A7]
6-bit digital audio A signal, Ch-4 is 16
Accepts each multiplex position of one word (one horizontal scanning line of pixel data is composed of 684 words) of digital video low resolution bits. P.

Q No. 15 for error code correction of 16 bits for each LJ, CR
C (a 23-bit error code detection signal, Adr is a random access i of the pickup reproducing element to 1 bit 1,
There is a part of the control signal C. The final two bits 1~ are the recovery bits 1~.

M
is converted into an analog signal L by the DA converter in the decoder 4 and taken out from the output terminal 5, while the digital video A signal is output from memory 1 to low (not shown in the figure). M! is written in by a control signal from M!, read out by this control signal, and converted into an analog video A signal by the DA converter 7. ! It is taken out from the J terminal 8.

On the other hand, for random access control (ci number Adr is detected by the address detector in the decoder 4, for example, 196
The blocks are taken out in sets. The control signal Δdr is divided into data from each bin 1 and transmitted in 3 bits in one block, and is converted by the decoder 4 into a 196-bit control signal having the configuration shown in FIG.

The total 196-bit control signal is the first jumper code CP-1 to the 49-bit time code C149p1,
49-bit second chapter code CP-2, 49 bits
The third chapter to J3 is composed of '-1 to CP-3.
The time code TC indicates the position of the recording program on the disc 1 in total time from the recording start position, and the 1st and 2nd time code CP-1,C
P-2 indicates the number of the Δ-video program from the recording start position d, and the 3'f-(7 butaccord 1" CP, -33 indicates the recording start position of the video subprogram. This shows the number 11 from .

The time code TC is a 24-bit synchronization signal @s14 bits 1~ L-code signal m116 bits indicating minutes and seconds (1 day, 4-bit track time signal gtp
, the first to third jabuts]-do CP-1 to CF-)-3t,
l, 2. /I bit synchronization Fj m, 4-bit seventh-order signal 111.8-bit chapter signal C1l, 1
2 bits 1 to 17 pig local address ad, 1
It is made up of parity codes p from 1 to -C.

j'::l -1'II J, the extracted time code and di(7) code are supplied to the shift register 9, and are transferred from the resolver 1-1 to the shift register 4 as shown in FIG. 1-1 (△). The outputs 4.1 and -1 of shift 1 to register 9 are synchronized with the clock pulse a of shift 1 to register 9.
The synchronizing signal of the time code TC and each of the synchronizing signals of the time codes Cl]-1 to CP-3 are detected and supplied to the data acquisition control circuit 11.

When the respective synchronization signals of the time code and the jab code are detected, the lζ data capture control signal is taken out from the j'-event capture control circuit 11 corresponding to the respective ]-code, and the data holding circuits 12a to 12d supplied to

On the other hand, the time code T taken out from the shift register 9
C and Chi I77"; Z: ] -toCP -1~CP
-3 are supplied in parallel to the data holding circuits 12a to 12d, and are taken into the data holding circuits 12a to 12d, respectively, by a data taking control signal from the data taking control circuit 11. Each of the data holding circuits 12a to 12d:
1- point n; y where the code is taken (・control signal is taken out,
It is supplied to AND gate 13. A signal is taken out from the AND gate 13 when all the control signals from the data holding circuits 12a to 12d are supplied, and this signal is supplied to the 24 counter 15.

In addition, the 1-1 pulse a is supplied to the frequency dividing circuit 14. The frequency is divided into 1/8 and is made into I cock pulse b as shown in FIG. 4 (8).
6. [jTsuku pulse b is 24 counter 1
5, the signal Rc shown in FIG. 4(C) is taken out and supplied to the gate circuit 16. 244 times are counted from the occurrence of A5 in the AND gate 13 at J3, and when 24 times are counted, the signal Rc shown in FIG. be done. Goo 1 - circuit 16 is signal C
is passed for a 1-rubel period.

The clock pulse b taken out from the frequency dividing circuit 111 is taken out through the gates 1 to '1G which are open during the H level period of the signal C, and the clock pulse b is taken out as shown in FIG. 4 (D>).
The one taken out from the output terminal 17 is supplied to the data holding circuits 12a to 12d.

f- Tights held in all holding circuits 12a to 12d, -1-do-o C and f-! 7 p]-do cp-i~CP
-3(, t) are simultaneously read out by the clock pulse d from the gate circuit 1G, and taken out from the output terminals 18a to 18d.

Time taken out from output terminals 18a to 18d
C and A7 adapter cords CP-1 to CP-3 are microphones ``1'' and CP-3 that are used for high-speed location searches, etc.
- supplied to a computer (not shown). Here, the time code or output terminal 18a to 1 of the desired program that has been set by one person or the like is retrieved.
The time code or chapter code from 8d is compared, and the pickup Fj generating element is displaced to the desired program based on the comparison error signal.

On the other hand, the time code, chapter code, and output y taken out from the output terminals 18a to 18d; and the clock pulse d taken out from the output terminal 17 are supplied to a display device driver (not shown). A display device (not shown) displays a time code and/or a time code in response to a drive signal from a display device driver.

As described above, the data output device according to the present invention time-sequentially outputs a code indicating the recording position of a plurality of programs recorded on an information recording medium and a synchronization signal that identifies the code as one block. a clock pulse of a predetermined frequency and a clock pulse of a predetermined frequency to shift the synchronous signal to a clock pulse of a predetermined frequency, and detect a synchronous signal corresponding to each synchronous signal taken out from the shifting means. When the code is loaded into each data holder, such as a data loading means that loads the code corresponding to each synchronization signal into each data holder in several stages of codes in one block, By dividing the frequency of the 11 pulses, the obtained code is obtained by dividing the frequency of the 11 pulses.For example, the recording position of 1 pulse is indicated at 1 time. Multiple codes such as code and A/F tag can be output simultaneously without special commands from the control circuit, programming of the control circuit is easy, and
In order to output each code at the same time, clock pulses are not supplied externally, and each code is set to one block [sequentially in one corner], and special control is provided for external microphones and monitors, etc. It can be drawn at low cost without having to set up a circuit! l, l, I'm annoyed with Ai.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram in which an embodiment of the device of the present invention is applied to a disk-shaped information recording medium reproducing device, and FIG.
The signal format of one block of the digital signal MFM-decoded in the -j-da is not shown. Figure 4 (
A) to (D> are signal waveform diagrams for explaining the operation of the device shown in FIG. 1. 11... Decoder, 9... Shift register, 1oa
~10d...Synchronization signal detector, 11...Data acquisition control circuit, 12a-12d...Data holding circuit, 1
3...andgoo 1~. 1/1... Frequency divider circuit, 15
...24 counter, 16... gate circuit, 18a-
・18d...]-Double horn terminal.

Claims (1)

[Claims] ii' A plurality of leads indicating the recording positions of the plurality of programs recorded on the information recording medium and synchronization signals identifying the codes, respectively, are supplied in chronological order;
The code and the synchronization signal are changed to a predetermined frequency by one pulse - (shift 1 - C extraction = shift means, and the synchronization signal corresponding to each code taken out from the shift means is detected and each time is detected. a data acquisition means for loading one code corresponding to each signal into each data holder in several stages of codes in the one block; - when the data is taken in, it is characterized by comprising means for simultaneously outputting (each of the data taken in by the data acquisition means) a tally pulse obtained by frequency-dividing the corresponding 1' clock pulse. Dozuru data output device.